Large-scale circuit partitioning method and device based on space filling curve

Abstract

The invention relates to a large-scale circuit partitioning method and device based on a space filling curve, and the method comprises the steps: dividing component entities recorded by a netlist according to attribute requirements after the netlist is imported, taking the connection relation recorded by the netlist as the basis, and optimizing the circuit partitioning process through employing various characteristics of the space filling curve. And the efficiency of circuit physical design is improved. As the whole geometric space of the actual circuit partition space can be filled with the space filling curve, the partition sequence after sorting and partitioning can be directly mapped into the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the assistance of the size of the component. In addition, the partitioning process is combined with the number of the components, it can be guaranteed that the number of the components in all the partitions is balanced, the density of the components is reasonably controlled, the partitioning quality is improved, and all the partitions can execute follow-up partitioning content in parallel so as to accelerate the partitioning process and reduce time expenditure.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation (EDA), and relates to a large-scale circuit partitioning method and device based on a space filling curve. Background Art

[0002] With the promotion of the wave of informatization and intelligence, the scale of its application computing has continued to surge, resulting in the continuous expansion of the number of semiconductor electronic components in integrated circuits. Since the layout and wiring (also known as physical design) of electronic components accounts for more than 30% of the design time of the entire integrated circuit and PCB (printed circuit board), designing large-scale integrated circuits is a technical challenge. Its design content generally includes module division, chip planning, layout, clock tree synthesis, wiring and timing convergence. In addition, high-quality design must also consider factors such as transmission signal delay, electromagnetic interference and crosstalk, and heat dissipation performance, all of which can be quantified as module properties. It can be seen that efficient circuit partitioning methods play a vital role in improving the efficiency and quality of integrated circuit design. Summary of the invention

[0003] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a large-scale circuit partitioning method based on space-filling curves and a large-scale circuit partitioning device based on space-filling curves, which can efficiently realize circuit partitioning and improve the efficiency and design quality of integrated circuit design.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: In one aspect, a method for partitioning a large-scale circuit based on a space filling curve is provided, comprising the steps of: Read the network table of a large-scale circuit to obtain circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set, the component list includes component name, value and packaging method, and the component network connection relationship includes network name, component and its used pins; Cut off the attribute network and divide all components connected to the integrated chip into functional modules based on whether they are connected to the integrated chip and divide all components not connected to the integrated chip into discrete device sets; the attribute network includes power network, ground network, timing network, data network, address network and control network; Construct an attribute vector with the attribute values ​​required by the functional module and map it to a one-dimensional value via a space filling curve, so as to obtain an ordered sequence of attribute vectors and evenly divide them into multiple partitions; Assign the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partition into an independent partition; A clustering algorithm is used to divide discrete devices in an independent partition into independent auxiliary modules according to topological relationships, thereby obtaining an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

[0005] On the other hand, a large-scale circuit partitioning device based on a space filling curve is also provided, comprising: An information acquisition module is used to read the network table of a large-scale circuit and obtain circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set, the component list includes component name, value and packaging method, and the component network connection relationship includes network name, component and its used pins; The device division module is used to cut off the attribute network and divide all the components connected to the integrated chip into various functional modules based on whether they are connected to the integrated chip, and divide all the components not connected to the integrated chip into a discrete device set; the attribute network includes the power network, the ground network, the timing network, the data network, the address network and the control network; A vector partitioning module is used to construct an attribute vector with the attribute values ​​required by the functional module and map it to a one-dimensional value via a space filling curve, so as to obtain an ordered sequence of attribute vectors and evenly divide them into multiple partitions; A partition arrangement module is used to allocate discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge discrete devices that have no connection relationship with the current existing partition into an independent partition; The auxiliary partition module is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship by using a clustering algorithm to obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned large-scale circuit partitioning method and device based on space-filling curves divides the component entities recorded in the network table according to the attribute requirements after importing the network table. The division is based on the connection relationship recorded in the network table and uses various characteristics of the space-filling curve to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with the existing circuit partitioning technology, the above scheme is first based on the attribute vector. The functional module sequence after sorting by the space filling curve will show corresponding characteristics and facilitate subsequent processing. For example, the space filling curve with good locality can allow the functional modules requiring the same voltage to be concentrated in a certain section of the partition sequence. During layout, this section can be placed in the same area to reduce the use of power conversion modules; secondly, since the space filling curve itself can fill the entire geometric space of the actual circuit partition space, the partition sequence after sorting and partitioning can be directly mapped to the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the help of the size of the components; in addition, the partitioning process is combined with the number of components to ensure the balance of the number of components in each partition, reasonably control the density of components, and improve the quality of partitioning; finally, when the order of the space filling curve is small, if the scale of components in the partition is still too large, each partition can execute subsequent partitioning content in parallel to speed up the partitioning process and reduce time overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 A schematic diagram of a flow chart of a large-scale circuit partitioning method based on a space filling curve in one embodiment; Figure 2 A schematic diagram of a process for evenly partitioning functional modules in an embodiment; Figure 3 A schematic diagram of a process of arranging partitions according to attribute requirements in one embodiment; Figure 4 A schematic diagram showing an example of an expected effect of circuit partitioning in one embodiment; Figure 5 A schematic diagram of a flow chart of a Hilbert curve sorting function module in one embodiment; Figure 6 A schematic diagram of a process for allocating discrete devices to each partition in one embodiment; Figure 7 It is a schematic diagram of generating the first three orders of a 2D Hilbert curve in one embodiment, wherein: Figure 7 (a) is the first order, Figure 7 (b) is of order 2, Figure 7 (c) is of order 3; Figure 8 A schematic diagram of a growth mode of a 2-dimensional Hilbert curve in one embodiment; Fig. 9 Schematic diagram of the sequence number of the functional module M in one embodiment; Fig.10 Schematic diagram of a module framework of a large-scale circuit partitioning device based on a space filling curve in one embodiment. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0011] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0012] In electronic design automation (EDA), a netlist is a list used to describe the various electronic components and their connection relationships in an integrated circuit. It is the logical basis of physical design and contains various component information and their pin connections. A netlist usually exists in text form, which records information such as component entities, ports, connection points, connection networks, attributes, and parameters. With this information, designers can clearly understand how the various electronic components in the integrated circuit are connected, ensuring that the expected circuit logic and functions can be achieved in chip manufacturing.

[0013] A space-filling curve is a continuous curve that can cover a multidimensional space. In theory, all points in a multidimensional space can be arranged on a one-dimensional curve according to certain rules. It is often used to optimize space-related operations such as graph partitioning, data processing, and grid generation. There are many types and characteristics of space-filling curves. For example, the Hilbert curve has good locality and symmetry, while the dragon curve has good fractal characteristics. Circuit partitioning is essentially a space-related operation. Different space-filling curves can be used to optimize different properties and reduce the time overhead of the design process.

[0014] The existing circuit partitioning method regards the network table as a graph and uses the graph partitioning method to partition. The graph partitioning method can include heuristic method, graph cut method and combination method. In addition, there is a partitioning method based on network attributes and patterns. Its main steps are as follows: read the network table to obtain component information and its topological relationship; take the integrated chip with a large number of pins as the core, cut off the attribute network, and naturally divide the circuit into multiple basic modules; obtain discrete device information, and distribute the discrete devices to each module according to the three methods of classification, forced allocation and pattern matching.

[0015] However, the above-mentioned graph partitioning method is to divide the circuit based on the topological relationship, which is difficult to meet the attribute requirements of the component arrangement. In addition, the large-scale graph calculation involved in the graph partitioning method requires too much computing power, which increases the cost of circuit design. The partitioning method based on network attributes and patterns is centered on multi-pin integrated chips. There is no more attribute arrangement information to support the implementation of the physical design process. During layout and routing, it is necessary to reconsider the arrangement of voltage and clock. Therefore, an efficient circuit partitioning method remains to be developed to improve the efficiency and quality of integrated circuit design.

[0016] In one embodiment, Figure 1 As shown, a large-scale circuit partitioning method based on a space filling curve is provided, which may include the following steps S10 to S18: S10, read the network table of the large-scale circuit to obtain the circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set; the component list includes component names, values ​​and packaging methods; the component network connection relationship includes network names, components and the pins used.

[0017] Specifically, the component list can be expressed as E={E1,E2,…,E l}, E1 to E l The network table can be stored in a text file, such as a commonly used NET file, to facilitate subsequent retrieval.

[0018] S12, cutting off the attribute network, dividing all components connected to the integrated chip into functional modules based on whether they are connected to the integrated chip, and dividing all components not connected to the integrated chip into a discrete device set.

[0019] It can be understood that by cutting off the attribute network Ni (1≤i≤s), the components are divided based on whether the integrated chip is connected, and k functional modules with the integrated chip as the core are obtained (represented as the functional module sequence M={M1,M2,…,Mk}, M1 to Mk represent each functional module respectively) and the remaining discrete devices that do not belong to the functional module. The discrete device set composed of each discrete device can be recorded as Sd. The number of components corresponding to each functional module can be expressed as W={W1,W2,…,Wk}, W1 to Wk represent the number of components corresponding to each functional module respectively; the attribute network in the circuit can include power network, ground network, timing network, data network, address network and control network, etc. Multi-pin integrated chips are generally connected through these networks. Cutting off these attribute networks can divide the functional modules with the multi-pin integrated chip as the core.

[0020] S14, constructing an attribute vector with the attribute values ​​required by the functional module and mapping it to a one-dimensional value via a space filling curve, obtaining an ordered attribute vector sequence and evenly dividing it into a plurality of partitions.

[0021] It can be understood that the constructed attribute vector can be expressed as Ai=(a1,a2,a3,…)(i=1,2,…,n), and the multi-dimensional attribute value is mapped to a one-dimensional value through a space filling curve to obtain an ordered attribute vector sequence and evenly divide the attribute vector sequence into multiple partitions. The specific process is as follows Figure 2 As shown, it may include: S141, select a space filling curve that meets the requirements and initialize the space filling curve growth mode. The set of growth modes can be recorded as D={D1,D2,…,Dj}, and the growth mode Di(1≤i≤j) contains a string of serial numbers; the optional space filling curves include but are not limited to Hilbert curves, Z curves, and Peano curves. Different space filling curves have different characteristics. For example, the Hilbert curve has good locality and self-similarity. After being sorted by the Hilbert curve, adjacent vectors in the vector space are also adjacent in the sequence, and it can generate space filling curves of different orders by recursion. Different space filling curves have different ways and quantities of initialization sequence numbers. This type of implementation technology is mature, and the latest generation algorithm of the corresponding curve can be selected to ensure processing efficiency.

[0022] S142, sorting the functional modules in the attribute space according to the growth direction of the space filling curve; S143, using a dynamic programming method to evenly partition the sorted functional modules.

[0023] S16, allocating the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtaining a partition sequence arranged according to attribute requirements, and merging discrete devices that have no connection relationship with the current existing partition into an independent partition.

[0024] The specific allocation process can be as follows Figure 3 As shown, the steps include: S161, constructing anchor coordinates with a dimension size equal to the number of partitions for each discrete device in the discrete device set, wherein the value of each dimension is the number of pins of the discrete device connected to the corresponding partition; S162, merging a set of discrete devices whose coordinates are all 0 (which can be recorded as set Z) into an independent partition; S163, for a set of discrete devices whose coordinates are not all zero (which may be recorded as set Q), select a space-filling curve with good locality and sort the discrete devices into an ordered sequence according to steps S141 and S142; S164, establishing an array (which may be recorded as array B) of the same length as the set of discrete devices whose coordinates are not all zero, and saving the position of each discrete device in the ordered sequence of the set Q on the same order space filling curve; S165, assigning discrete devices whose coordinates are not all zero to the partitions with the closest connection, to obtain a partition sequence arranged according to the attribute requirements.

[0025] S18, using a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, to obtain an independent partition composed of auxiliary modules; wherein, It can be understood that after step S16, the number of discrete devices in the independent partition has been greatly reduced compared to the initial situation. At this time, a clustering algorithm is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, and an independent partition composed of auxiliary modules is obtained. At this point, the partitioning process ends. A partition sequence arranged according to attribute requirements and an independent partition composed of auxiliary modules are obtained, which can be used for the subsequent layout and routing of large-scale circuits. Specifically, the discrete devices in the partition sequence obtained after partitioning can be arranged in sequence in the actual circuit partition space according to the growth order of the space filling curve in the actual circuit partition space. There is no order requirement for the auxiliary modules in the independent partition. They can be inserted where needed in the actual circuit partition space or laid out separately in an area. One example of a partitioning effect can be as follows Figure 4 As shown, C1, C2, M1 and M2 are circuit modules of each chip respectively.

[0026] The above-mentioned large-scale circuit partitioning method based on space-filling curves divides the component entities recorded in the network table according to the attribute requirements after importing the network table. The division is based on the connection relationship recorded in the network table and uses various characteristics of the space-filling curve to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with the existing circuit partitioning technology, the above scheme is first based on the attribute vector. The functional module sequence after sorting by the space filling curve will show corresponding characteristics and facilitate subsequent processing. For example, the space filling curve with good locality can allow the functional modules requiring the same voltage to be concentrated in a certain section of the partition sequence. During layout, this section can be placed in the same area to reduce the use of power conversion modules; secondly, since the space filling curve itself can fill the entire geometric space of the actual circuit partition space, the partition sequence after sorting and partitioning can be directly mapped to the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the help of the size of the components; in addition, the partitioning process is combined with the number of components to ensure the balance of the number of components in each partition, reasonably control the density of components, and improve the quality of partitioning; finally, when the order of the space filling curve is small, if the scale of components in the partition is still too large, each partition can execute subsequent partitioning content in parallel to speed up the partitioning process and reduce time overhead.

[0027] In one embodiment, Figure 5 As shown, the above step S142, sorting the functional modules in the attribute space according to the growth direction of the space filling curve, may include the steps of: Get the maximum value of each dimension in the attribute vector to form a bounding box containing all vectors; the bounding box is the first parent space; The parent space is evenly divided into the same number of subspaces according to the number of sequence numbers in the growth pattern, and the sequence numbers are matched one by one with the subspaces according to the growth direction of the space filling curve; If the order of the current space-filling curve is 1, the sequence number of the subspace where the attribute vector is located is the sequence number of the subspace in the growth mode; If the order of the current space filling curve is greater than 1, the sequence number of the subspace where the attribute vector is located is the number of subspaces that already existed in the parent space where the attribute vector is located, plus the sequence number of the subspace where the attribute vector is located in the growth mode; Treat the current subspace as the parent space, and repeat the steps of evenly dividing the parent space into the same number of subspaces according to the number of serial numbers in the growth pattern, and corresponding the serial numbers to the subspaces one by one according to the growth direction of the space filling curve until, if the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces in front of the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth pattern, until each subspace contains only one attribute vector; The functional module sequences are exchanged and sorted according to the relative positions of the attribute vectors on the space filling curve.

[0028] Specifically, (1) obtain the maximum value of each dimension in the attribute vector to form a bounding box containing all vectors; the bounding box is the first parent space; (2) divide the parent space evenly into the same number of subspaces according to the number of serial numbers in the growth pattern Di, and correspond the serial numbers to the subspaces one by one according to the growth direction of the space filling curve; (3) if the order of the current space filling curve is 1, then for the attribute vector Ai (1≤i≤n), the serial number of the subspace in which it is located is the serial number of the subspace in the growth pattern Di, and jump to (5); (4) if the order of the current space filling curve is greater than 1, then for the attribute vector Ai, the serial number of the subspace in which the attribute vector Ai is located is the number of subspaces in front of the parent space in which the attribute vector Ai is located, plus the serial number of the subspace in which the attribute vector Ai is located in the growth pattern Di. Among them, for different space filling curves, the number of subspaces in front of the current subspace can be calculated according to the parent space number of the current subspace; (5) Repeat steps (2) to (4) with the current subspace as the parent space until each subspace contains only one attribute vector; (6) Exchange and sort the functional module sequence according to the relative position of the attribute vector on the space filling curve.

[0029] In one embodiment, the above step S143, using dynamic programming to evenly partition the sorted functional modules, may include the following steps: If the number of partitions is not entered, each functional module is a partition; If the number of partitions y is entered, the functional module sequence is evenly divided into y parts using a dynamic programming method in combination with the number of components sequence; Create a new array Ep with the same length as the component list and initialize it; the initialization rule of array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

[0030] Specifically, if the number of partitions is not entered, each functional module is a partition, and the process jumps to step S16; if the number of partitions y is entered, the functional module sequence M is evenly divided into y parts using the existing dynamic programming method in combination with the component quantity sequence W; a new array Ep with the same length as the component list E is created and initialized; wherein, the initialization rule of the array Ep is as follows: if the component is not in an existing partition, the corresponding position is set to -1; if the component is in a certain partition, the corresponding position is the partition number of the partition in which it is located.

[0031] In one embodiment, Figure 6As shown, the above step S161, establishing a y-dimensional anchor coordinate P for each discrete device in the discrete device set, wherein the value of each dimension is the number of pins connecting the current component to the corresponding partition, may include the following processing: Initialize all coordinate values ​​of the anchor coordinates to 0; Search the position with value -1 in array Ep for the name Ename of the component corresponding to it; Retrieve the target network in the network table that contains Ename according to the name, and obtain the name array C of other components connected to the pins of the component in the target network; If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; If the name array C is empty, repeat the steps of searching the target network containing Ename in the network table according to the name, and obtaining the name array C of other components connected to the pin of the component by the target network. If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P until the anchor coordinate is constructed.

[0032] Specifically, (a) initialize all coordinate values ​​of the anchor coordinate P to 0; (b) search the name Ename of the component corresponding to the position with a value of -1 in the array Ep in turn; (c) retrieve the target network containing Ename in the network table according to the name, and obtain the name array C of other components connected to the pin of the component in the target network; (d) if the name array C is empty, jump to step (f); (e) otherwise, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; (f) repeat steps (c) to (e) until the anchor coordinate P is constructed.

[0033] In one embodiment, in the above step S165, the discrete devices whose coordinates are not all zero are allocated to the partitions with the closest connection, so as to obtain a partition sequence arranged according to the attribute requirements. Specifically, the process of allocating the ordered discrete device set Q to y partitions may include the following processing: Divide the ordered discrete device set Q into a plurality of subsets according to the arranged order; For each subset, add the coordinate values ​​of all coordinates in the subset on each coordinate axis to get the y sum value; The set of discrete devices corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest y sum value.

[0034] Specifically: (I) the ordered discrete device set Q is divided into a plurality of subsets according to the arranged order; wherein, Figure 6As shown, the partitioning method is: starting from the second component, traverse the ordered sequence of the set Q, use array B to calculate the position difference between each component and the previous component on the space filling curve, and cut where the position difference is too large to ensure that the positions of the components in the same subset on the same order space filling curve are not much different, wherein the judgment value of whether the specific position difference is too large can be set according to the specific component density on the same order space filling curve, for example, the judgment value of the component with relatively large density can be reduced, and the judgment value of the component with relatively small density can be increased. The most specific value can be set according to the specific component density on the space filling curve combined with experience; (II) for each subset obtained after cutting, add the coordinate values ​​of all coordinates on each coordinate axis in the subset to obtain y sum values; (III) the discrete device set corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest y sum values.

[0035] In one embodiment, regarding the above step S18, the process of using a clustering algorithm to divide the components into independent partitions may include: Read the network table information, and construct an undirected graph with the components of the independent partitions as the node set and the connections between the components as the edge set; The spectral clustering algorithm is used to divide the undirected graph into independent auxiliary modules. The process of spectral clustering algorithm is as follows: the similarity matrix and adjacency matrix of the undirected graph are used to construct the Laplacian matrix, the eigenvectors of the first k smallest eigenvalues ​​of the Laplacian matrix are calculated using the lanczos (an iterative algorithm) method, and the eigenvectors are clustered by kmeans to obtain the auxiliary modules, where k is an integer greater than 0.

[0036] Specifically: First, read the network table information, and construct an undirected graph G (V, E) with independently partitioned components as the node set V and the connections between devices as the edge set E; then, use the similarity matrix and adjacency matrix of the undirected graph G to construct the Laplacian matrix; then, use the Lanczos method to calculate the eigenvectors of the first k smallest eigenvalues ​​of the Laplacian matrix; finally, perform kmeans clustering (an unsupervised learning algorithm used to divide data points into different categories (clusters)) on the eigenvectors to obtain various auxiliary modules.

[0037] In some implementations, one example may be: obtaining the voltage and clock attribute vector A=(V, C) of the functional module M with the arrangement requirement, requiring the devices with similar voltage and similar clock to be similar in position, selecting the Hilbert curve to map the 2D vector space to the 1D space to obtain a functional module sequence that meets the attribute arrangement requirements, and the first 3 orders of the Hilbert curve are generated as follows Figure 7 As shown, Figure 7 (a) is the first order, Figure 7 (b) is of order 2, Figure 7(c) is level 3; its process includes: Step 1: Initialize the growth mode of the Hilbert curve. Here, the attribute vector is a 2D vector. The 2D Hilbert curve has 8 modes, such as Figure 8 shown.

[0038] Step 2: Sort the functional modules in the attribute space according to the growth direction of the Hilbert curve, including: Step 2-1, obtain the maximum and minimum values ​​Vmax, Vmin, Cmax, Cmin of each dimension in the attribute vector, and form a bounding box Bd containing all attribute vectors. The bounding box Bd is the first parent space; Step 2-2, divide the parent space into the same number of subspaces evenly according to the number of serial numbers in the growth pattern Di (1≤i≤8), and correspond the serial numbers to the subspaces one by one according to the growth direction of the space filling curve; In step 2-3, if the order of the current space-filling curve is 1, then for vector A, the sequence number of its subspace is the sequence number of the subspace in the pattern Di (1≤i≤8), and jump to step 2-5; Step 2-4: If the order of the current space filling curve is greater than 1, then for vector A, the parent space number x and the current subspace number y in the pattern, the subspace number is 4. x+y+1; Step 2-5: Repeat steps 2-2 to 2-4 using the existing subspace as the parent space until each subspace contains only one vector; In step 2-6, the sequence of functional modules is exchanged according to the relative position of the vectors on the space-filling curve; the sequence number of the functional module M is equal to the sequence number of its corresponding vector A on the Hilbert curve, such as Fig. 9 As shown, the circular dots represent functional modules.

[0039] It should be understood that although Figures 1 to 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figures 1 to 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0040] In one embodiment, Fig.10As shown, a large-scale circuit partitioning device 100 based on a space filling curve is provided, which may include an information acquisition module 11, a device partitioning module 13, a vector partitioning module 15, a partition arrangement module 17 and an auxiliary partitioning module 19. Among them, the information acquisition module 11 is used to read the network table of the large-scale circuit and obtain the circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set, the component list includes the component name, value and packaging method, and the component network connection relationship includes the network name, the component and the pins used. The device partitioning module 13 is used to cut off the attribute network and divide all the components connected to the integrated chip into various functional modules based on whether the integrated chip is connected as a criterion, and divide all the components not connected to the integrated chip into a discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network and a control network. The vector partitioning module 15 is used to construct an attribute vector with the attribute value required by the functional module and map it to a one-dimensional value through a space filling curve, so as to obtain an ordered attribute vector sequence and evenly divide it into multiple partitions. The partition arrangement module 17 is used to allocate the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to the attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partition into an independent partition. The auxiliary partition module 19 is used to use a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, and obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

[0041] The above-mentioned large-scale circuit partitioning device 100 based on space-filling curves, after importing the network table, divides the component entities recorded in the network table according to the attribute requirements. The division is based on the connection relationship recorded in the network table, and uses various characteristics of the space-filling curve to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with the existing circuit partitioning technology, the above scheme is first based on the attribute vector. The functional module sequence after sorting by the space filling curve will show corresponding characteristics and facilitate subsequent processing. For example, the space filling curve with good locality can allow the functional modules requiring the same voltage to be concentrated in a certain section of the partition sequence. During layout, this section can be placed in the same area to reduce the use of power conversion modules; secondly, since the space filling curve itself can fill the entire geometric space of the actual circuit partition space, the partition sequence after sorting and partitioning can be directly mapped to the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the help of the size of the components; in addition, the partitioning process is combined with the number of components to ensure the balance of the number of components in each partition, reasonably control the density of components, and improve the quality of partitioning; finally, when the order of the space filling curve is small, if the scale of components in the partition is still too large, each partition can execute subsequent partitioning content in parallel to speed up the partitioning process and reduce time overhead.

[0042] In one embodiment, the vector partitioning module 15 may include: The box construction submodule is used to obtain the maximum value of each dimension in the attribute vector and construct a bounding box containing all vectors; the bounding box is the first parent space; The space correspondence submodule is used to evenly divide the parent space into the same number of subspaces according to the number of sequence numbers in the growth pattern, and to correspond the sequence numbers to the subspaces one by one according to the growth direction of the space filling curve; The serial number determination submodule is used to determine that when the order of the current space filling curve is 1, the serial number of the subspace where the attribute vector is located is the serial number of the subspace in the growth mode; when the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces in front of the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth mode; The loop submodule is used to treat the current subspace as the parent space and jump to the submodule corresponding to the space until each subspace contains only one attribute vector; The exchange sorting submodule is used to exchange and sort the functional module sequence according to the relative position of the attribute vector on the space filling curve.

[0043] In one embodiment, the vector partitioning module 15 uses the dynamic programming method to evenly partition the sorted functional modules: if the partition number is not entered, each functional module is a partition; if the partition number y is entered, the functional module sequence is evenly divided into y parts using the dynamic programming method in combination with the component quantity sequence; a new array Ep with the same length as the component list is created and initialized; wherein the initialization rule of the array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

[0044] In one embodiment, the partition arrangement module 17 constructs anchor coordinates with a dimension size of the number of partitions for each discrete device in the discrete device set, and when the value of each dimension is the number of pins of the discrete device connected to the corresponding partition, it is used to: initialize all coordinate values ​​of the anchor coordinates to 0; sequentially search for the name Ename of the component corresponding to the position with a value of -1 in the array Ep; retrieve the target network containing Ename in the network table according to the name, and obtain the array C of other component names connected to the pins of the component by the target network; if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; if the name array C is empty, repeat the steps of retrieving the target network containing Ename in the network table according to the name, obtaining the array C of other component names connected to the pins of the component by the target network, and if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P, until the anchor coordinate is constructed.

[0045] It can be understood that the explanation of each feature in the above-mentioned large-scale circuit partitioning device 100 based on space filling curve can be understood in the same way as the corresponding explanation in each embodiment of the above-mentioned large-scale circuit partitioning method based on space filling curve. Each module in the above-mentioned large-scale circuit partitioning device 100 based on space filling curve can be fully or partially implemented by software, hardware and a combination thereof. The above-mentioned components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The aforementioned device can be but not limited to various types of circuit design computers already available in the art.

[0046] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0047] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A large-scale circuit partitioning method based on space filling curves, characterized in that: Includes steps: Read the network table of a large-scale circuit to obtain circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set, the component list includes component name, value and packaging method, and the component network connection relationship includes network name, component and its used pins; Cut off the attribute network and divide all components connected to the integrated chip into functional modules based on whether the integrated chip is connected or not, and divide all components not connected to the integrated chip into discrete device sets; the attribute network includes a power network, a ground network, a timing network, a data network, an address network and a control network; Construct an attribute vector with the attribute values ​​required by the functional module and map it to a one-dimensional value via a space filling curve, so as to obtain an ordered sequence of attribute vectors and evenly divide them into multiple partitions; Assign the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partition into an independent partition; A clustering algorithm is used to divide discrete devices in an independent partition into independent auxiliary modules according to topological relationships, thereby obtaining an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

2. The large-scale circuit partitioning method based on space filling curve according to claim 1, characterized in that: In the step of constructing an attribute vector with the attribute values ​​required by the functional module and mapping it to a one-dimensional value via a space filling curve, obtaining an ordered attribute vector sequence and evenly dividing it into a plurality of partitions, when the functional modules are sorted in the attribute space according to the growth direction of the space filling curve, the steps include: Get the maximum value of each dimension in the attribute vector to form a bounding box containing all vectors; the bounding box is the first parent space; The parent space is evenly divided into the same number of subspaces according to the number of sequence numbers in the growth pattern, and the sequence numbers are matched one by one with the subspaces according to the growth direction of the space filling curve; If the order of the current space-filling curve is 1, the sequence number of the subspace where the attribute vector is located is the sequence number of the subspace in the growth mode; If the order of the current space filling curve is greater than 1, the sequence number of the subspace where the attribute vector is located is the number of subspaces that already exist in the parent space where the attribute vector is located, plus the sequence number of the subspace where the attribute vector is located in the growth mode; The currently existing subspace is regarded as the parent space, and the steps of uniformly dividing the parent space into the same number of subspaces according to the number of serial numbers in the growth pattern, and corresponding the serial numbers to the subspaces one by one according to the growth direction of the space filling curve are repeated until the step of if the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces that existed before the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth pattern, until each subspace contains only one attribute vector; The functional module sequences are exchanged and sorted according to the relative positions of the attribute vectors on the space filling curve.

3. The large-scale circuit partitioning method based on space filling curve according to claim 1 or 2, characterized in that: In the step of constructing an attribute vector with the attribute values ​​required by the functional module and mapping it to a one-dimensional value via a space filling curve, obtaining an ordered attribute vector sequence and evenly dividing it into a plurality of partitions, the steps of evenly partitioning the ordered functional modules using a dynamic programming method include: If the number of partitions is not entered, each functional module is a partition; If the number of partitions y is entered, the functional module sequence is evenly divided into y parts using a dynamic programming method in combination with the number of components sequence; Create a new array Ep with the same length as the component list and initialize it; the initialization rule of array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

4. The method for partitioning a large-scale circuit based on a space filling curve according to claim 3, characterized in that: The discrete devices in the discrete device set are assigned to the partitions that are most closely connected to the discrete devices, and a partition sequence arranged according to the attribute requirements is obtained. In the step of merging the discrete devices that have no connection relationship with the current existing partition into an independent partition, an anchor coordinate with a dimension size of the number of partitions is constructed for each discrete device in the discrete device set, and the value of each dimension is the number of pins of the discrete device connected to the corresponding partition, including the steps of: Initialize all coordinate values ​​of the anchor coordinates to 0; Search the position with value -1 in array Ep for the name Ename of the component corresponding to it; Retrieve the target network in the network table that contains Ename according to the name, and obtain the name array C of other components connected to the pins of the component in the target network; If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; If the name array C is empty, repeat the steps of retrieving the target network containing Ename in the network table according to the name, obtaining the name array C of other components connected to the pin of the component by the target network, and if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P until the anchor coordinate is constructed.

5. The large-scale circuit partitioning method based on space filling curve according to claim 4, characterized in that: The discrete devices in the discrete device set are assigned to the partitions that are most closely connected to the discrete devices to obtain a partition sequence arranged according to the attribute requirements, and the discrete devices that have no connection relationship with the current existing partitions are merged into an independent partition. The discrete devices whose coordinates are not all 0 are assigned to the partitions that are most closely connected to obtain the partition sequence arranged according to the attribute requirements, including the steps of: Divide the ordered discrete device set Q into a plurality of subsets according to the arranged order; For each subset, add the coordinate values ​​of all coordinates in the subset on each coordinate axis to get the y sum value; The set of discrete devices corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest y sum value.

6. The large-scale circuit partitioning method based on space filling curve according to claim 3, characterized in that: In the process of using a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, the division process includes: Read the network table information, and construct an undirected graph with the components of the independent partitions as the node set and the connections between the components as the edge set; The spectral clustering algorithm is used to partition the undirected graph into independent auxiliary modules.

7. A large-scale circuit partitioning device based on space filling curves, characterized in that: include: An information acquisition module is used to read the network table of a large-scale circuit and obtain circuit diagram information; The circuit diagram information includes a component list set and a component network connection relationship set, wherein the component list includes component names, values ​​and packaging methods, and the component network connection relationship includes network names, components and pins used by them; A device division module is used to cut off the attribute network and divide all components connected to the integrated chip into functional modules based on whether they are connected to the integrated chip and divide all components not connected to the integrated chip into a discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network and a control network; A vector partitioning module is used to construct an attribute vector with the attribute values ​​required by the functional module and map it to a one-dimensional value via a space filling curve, so as to obtain an ordered sequence of attribute vectors and evenly divide them into multiple partitions; A partition arrangement module is used to allocate discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge discrete devices that have no connection relationship with the current existing partition into an independent partition; The auxiliary partition module is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship using a clustering algorithm to obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

8. The large-scale circuit partitioning device based on space filling curve according to claim 7, characterized in that: The vector partitioning module includes: The box construction submodule is used to obtain the maximum value of each dimension in the attribute vector and construct a bounding box containing all vectors; the bounding box is the first parent space; The space correspondence submodule is used to evenly divide the parent space into the same number of subspaces according to the number of sequence numbers in the growth pattern, and to correspond the sequence numbers to the subspaces one by one according to the growth direction of the space filling curve; The serial number determination submodule is used to determine that when the order of the current space filling curve is 1, the serial number of the subspace where the attribute vector is located is the serial number of the subspace in the growth mode; when the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces in front of the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth mode; A loop submodule is used to treat the current subspace as a parent space and jump to the submodule corresponding to the space until each subspace contains only one attribute vector; The exchange sorting submodule is used to exchange and sort the functional module sequence according to the relative position of the attribute vector on the space filling curve.

9. The large-scale circuit partitioning device based on space filling curve according to claim 7 or 8, characterized in that: When the vector partitioning module uses dynamic programming to evenly partition the sorted functional modules: If the number of partitions is not entered, each functional module is a partition; If the number of partitions y is entered, the functional module sequence is evenly divided into y parts using a dynamic programming method in combination with the number of components sequence; Create a new array Ep with the same length as the component list and initialize it; the initialization rule of array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

10. The large-scale circuit partitioning device based on space filling curve according to claim 9, characterized in that: The partition arrangement module constructs anchor coordinates with a dimension size equal to the number of partitions for each discrete device in the discrete device set, and the value of each dimension is the number of pins of the discrete device connected to the corresponding partition, and is used to: Initialize all coordinate values ​​of the anchor coordinates to 0; Search the position with value -1 in array Ep for the name Ename of the component corresponding to it; Retrieve the target network in the network table that contains Ename according to the name, and obtain the name array C of other components connected to the pins of the component in the target network; If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; If the name array C is empty, repeat the steps of retrieving the target network containing Ename in the network table according to the name, obtaining the name array C of other components connected to the pin of the component by the target network, and if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P until the anchor coordinate is constructed.

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