Large-scale circuit partitioning method and device based on space-filling curve

Abstract

The present invention relates to a large-scale circuit partitioning method and device based on space-filling curves. After importing a netlist, component entities recorded in the netlist are partitioned according to attribute requirements. This partitioning is based on the connection relationships recorded in the netlist, and various characteristics of space-filling curves are used to optimize the circuit partitioning process, improving the efficiency of circuit physical design. Since the space-filling curve itself can fill the entire geometric space of the actual circuit partitioning space, the partition sequence after sorting and partitioning can be directly mapped into the actual circuit partitioning space, and subsequent layout design in the actual circuit partitioning space can be automatically completed with the assistance of the sizes of components. In addition, by combining the number of components in the partitioning process, the number of components in each partition can be balanced, the component density can be reasonably controlled, and the partitioning quality can be improved. Each partition can execute subsequent partitioning content in parallel to accelerate the partitioning process and reduce time overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation (EDA), and relates to a large-scale circuit partitioning method and device based on a space-filling curve. Background Art

[0002] With the promotion of the informationization and intelligentization wave, the scale of its application computing has been increasing rapidly, resulting in the continuous expansion of the number of semiconductor electronic components in integrated circuits. Since the layout and wiring of electronic components (also known as physical design) account for more than 30% of the design time of the entire integrated circuit and PCB (printed circuit board), designing a large-scale integrated circuit is a technical challenge, and its design content generally includes module partitioning, chip planning, layout, clock tree synthesis, wiring, and timing convergence. In addition, high-quality design also needs to consider factors such as transmission signal delay, electromagnetic interference and crosstalk, and heat dissipation performance, and these factors can be quantified as module attributes. It can be seen that an efficient circuit partitioning method plays a crucial role in improving the design efficiency and quality of integrated circuits. Summary of the Invention

[0003] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a large-scale circuit partitioning method based on a space-filling curve and a large-scale circuit partitioning device based on a space-filling curve, which can efficiently implement circuit partitioning and improve the design efficiency and quality of integrated circuits.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a large-scale circuit partitioning method based on a space-filling curve is provided, including the steps of:

[0006] Reading the netlist of a large-scale circuit to obtain circuit diagram information; the circuit diagram information includes a set of component lists and a set of network connection relationships of components, the component list includes component names, values, and packaging methods, and the component network connection relationships include network names, components, and pins used by them;

[0007] Cutting off the attribute network and, based on whether it is connected to an integrated chip, dividing all the components connected to the integrated chip into each functional module and dividing all the components not connected to the integrated chip into a discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network, and a control network;

[0008] Constructing an attribute vector based on the attribute values required by the functional module and mapping it to a one-dimensional value via a space-filling curve to obtain an ordered sequence of attribute vectors and evenly dividing it into multiple partitions;

[0009] Assign the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to the attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partitions into an independent partition;

[0010] Use a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, and obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of the large-scale circuit.

[0011] On the other hand, a large-scale circuit partitioning device based on a space-filling curve is also provided, including:

[0012] An information acquisition module, configured to read the netlist of the large-scale circuit and obtain circuit diagram information; the circuit diagram information includes a set of component lists and a set of network connection relationships of the components. The component list includes the component name, value, and package method, and the component network connection relationship includes the network name, component, and pins used by the component;

[0013] A device partitioning module, configured to cut off the attribute network and, based on whether it is connected to the integrated chip, divide all the components connected to the integrated chip into each functional module and divide all the components not connected to the integrated chip into the discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network, and a control network;

[0014] A vector partitioning module, configured to construct an attribute vector with the attribute values required by the functional module and map it to a one-dimensional value via a space-filling curve, obtain an ordered attribute vector sequence, and evenly divide it into multiple partitions;

[0015] A partition arrangement module, configured to assign the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to the attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partitions into an independent partition;

[0016] An auxiliary partition module, configured to use a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, and obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of the large-scale circuit.

[0017] One of the above technical solutions has the following advantages and beneficial effects:

[0018] The above-mentioned large-scale circuit partitioning method and device based on space-filling curves divide the component entities recorded in the netlist according to attribute requirements after importing the netlist. This division is based on the connection relationships recorded in the netlist, and uses various characteristics of space-filling curves to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with existing circuit partitioning technologies, the above solution is first based on an attribute vector. The functional module sequence sorted by the space-filling curve will exhibit corresponding characteristics for subsequent processing. For example, a space-filling curve with good locality can make functional modules that require the same voltage concentrated in a certain segment of the partitioning sequence. When laying out, this segment can be placed in the same area to reduce the use of power conversion modules. Secondly, since the space-filling curve itself can fill the entire geometric space of the actual circuit partitioning space, the partitioning sequence after sorting and partitioning can be directly mapped into the actual circuit partitioning space, and combined with the sizes of the components, the subsequent layout design in the actual circuit partitioning space can be automatically completed. In addition, the partitioning process combines the number of components to ensure the balance of the number of components in each partition, reasonably control the component density, and improve the partitioning quality. Finally, when the order of the space-filling curve is small, if the scale of the components in a partition is still too large, each partition can execute the subsequent partitioning content in parallel to speed up the partitioning process and reduce the time overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a schematic flowchart of a large-scale circuit partitioning method based on space-filling curves in an embodiment;

[0021] Figure 2 It is a schematic flowchart of uniform partitioning of functional modules in an embodiment;

[0022] Figure 3 It is a schematic flowchart of arranging partitions according to attribute requirements in an embodiment;

[0023] Figure 4 It is a schematic diagram of an example of the expected effect of a circuit partition in an embodiment;

[0024] Figure 5 It is a schematic flowchart of sorting functional modules using the Hilbert curve in an embodiment;

[0025] Figure 6 It is a schematic flowchart of allocating discrete devices to each partition in an embodiment;

[0026] Figure 7 Schematic diagram of the generation of the first 3 orders of the 2D Hilbert curve in an embodiment, where, Figure 7 (a) is of the 1st order, Figure 7 (b) is of the 2nd order, Figure 7 (c) is of the 3rd order;

[0027] Figure 8 Schematic diagram of the growth mode of the 2D Hilbert curve in an embodiment;

[0028] Figure 9 Schematic diagram of the serial numbers of the functional module M in an embodiment;

[0029] Figure 10 Schematic diagram of the module framework of a large-scale circuit partitioning device based on a space-filling curve in an embodiment. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0031] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term " / and / or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0033] A netlist is a list used to describe the various electronic components and their connection relationships in an integrated circuit in Electronic Design Automation (EDA). It is the logical basis for physical design and contains information about various components and their pin connections. A netlist usually exists in text form, recording information such as component entities, ports, connection points, connection networks, attributes, and parameters. Through this information, designers can clearly know how the various electronic components in the integrated circuit are connected, ensuring that the expected circuit logic and functions can be achieved during chip manufacturing.

[0034] A space-filling curve is a continuous curve that can cover a multi-dimensional space. In theory, all points in the multi-dimensional space can be arranged on a one-dimensional curve according to a certain rule, and it is often used to optimize space-related operations such as graph partitioning, data processing, and mesh generation. The types and characteristics of space-filling curves are diverse. For example, the Hilbert curve has good locality and symmetry, while the dragon curve has better fractal characteristics. Circuit partitioning is essentially a space-related operation, and different space-filling curves can be used to optimize different attributes, reducing the time overhead in the design process.

[0035] Existing circuit partitioning methods regard the netlist as a graph and use graph partitioning methods for partitioning. Graph partitioning methods can include heuristic methods, graph cut methods, and combinatorial methods, etc. In addition, there are also partitioning methods based on network attributes and patterns, and their main steps are as follows: read the netlist to obtain component information and its topological relationship; take the integrated chip with more pins as the core, cut off the attribute network, and naturally divide the circuit into multiple basic modules; obtain discrete device information, and distribute the discrete devices to each module according to the three methods of classification, forced assignment, and pattern matching.

[0036] However, the above graph partitioning method is a topological partitioning of the circuit, which is difficult to meet the attribute requirements of component arrangement, and the large-scale graph calculation involved in the graph partitioning method has too high computing power requirements, increasing the cost of circuit design. The partitioning method based on network attributes and patterns takes the multi-pin integrated chip as the core and lacks more attribute arrangement information to support the implementation of the physical design process. Issues such as the layout of voltage and clock still need to be reconsidered during placement and routing. Therefore, there is still a need to develop an efficient circuit partitioning method to improve the design efficiency and quality of integrated circuits.

[0037] In one embodiment, as Figure 1 shown, a large-scale circuit partitioning method based on space-filling curves is provided, which can include the following steps S10 to S18:

[0038] S10. Read the netlist of the large-scale circuit to obtain circuit diagram information. The circuit diagram information includes a set of component lists and a set of network connection relationships of the components. The component list includes the component name, value, and package type. The network connection relationship of the component includes the network name, the component, and the pins it uses.

[0039] Specifically, the component list can be expressed as E = {E1, E2, …, E l}, where E1 to E l respectively represent each component, and the set of network connection relationships can be expressed as N = {N1, N2, …, Ns}, where N1 to Ns respectively represent each network connection relationship. The netlist can be stored in a text file, such as a common NET file, etc., for convenient subsequent retrieval.

[0040] S12. Cut off the attribute network. Based on whether it is connected to the integrated chip, divide all the components connected to the integrated chip into each functional module and divide all the components not connected to the integrated chip into the discrete device set.

[0041] It can be understood that by cutting off the attribute network Ni (1 ≤ i ≤ s) and dividing the components based on whether they are connected to the integrated chip, k functional modules centered on the integrated chip are obtained (expressed as the functional module sequence M = {M1, M2, …, Mk}, where M1 to Mk respectively represent each functional module) and the remaining discrete devices that do not belong to the functional module. The discrete device set composed of each discrete device can be denoted as Sd. The number of components corresponding to each functional module can be expressed as W = {W1, W2, …, Wk}, where W1 to Wk respectively represent the number of components corresponding to each functional module; the attribute networks in the circuit can include the power network, the ground network, the timing network, the data network, the address network, and the control network, etc. Multi-pin integrated chips are generally connected through these networks. Cutting off these attribute networks can divide the functional modules centered on the multi-pin integrated chip.

[0042] S14. Construct an attribute vector based on the attribute values required by the functional module and map it to a one-dimensional value via a space-filling curve to obtain an ordered sequence of attribute vectors and evenly divide it into multiple partitions.

[0043] It can be understood that the constructed attribute vector can be expressed as Ai = (a1, a2, a3, …) (i = 1, 2, …, n). By using a space-filling curve, the multi-dimensional attribute values are mapped to one-dimensional values, obtaining an ordered sequence of attribute vectors and evenly dividing this sequence of attribute vectors into multiple partitions. The specific process is as Figure 2 shown and may include:

[0044] S141. Select a space-filling curve that meets the requirements and initialize the growth mode of the space-filling curve. The set of growth modes can be denoted as D = {D1, D2, …, Dj}, and the growth mode Di (1 ≤ i ≤ j) contains a series of serial numbers. Optional space-filling curves include, but are not limited to, Hilbert curves, Z curves, Peano curves, etc. Different space-filling curves have different characteristics. For example, Hilbert curves have good locality and self-similarity. After sorting by Hilbert curves, vectors that are adjacent in the vector space are also adjacent in the sequence, and different orders of space-filling curves can be generated recursively. Different space-filling curves also differ in the way and quantity of initializing and generating serial numbers. Such implementation technologies are already mature, and the latest generation algorithms corresponding to the curves can be selected to ensure processing efficiency.

[0045] S142. Sort the functional modules in the attribute space according to the growth direction of the space-filling curve.

[0046] S143. Use dynamic programming to evenly partition the sorted functional modules.

[0047] S16. Assign the discrete devices in the discrete device set to the partition with the closest connection to the discrete device, obtaining a partition sequence arranged according to the attribute requirements. Combine the discrete devices that have no connection relationship with the current existing partitions into an independent partition.

[0048] The specific assignment process can be as Figure 3 shown, including the steps:

[0049] S161. For each discrete device in the discrete device set, construct an anchor coordinate with the dimension size equal to the number of partitions, and the value of each dimension is the number of pins of the discrete device connected to the corresponding partition.

[0050] S162. Combine the set of discrete devices with all-zero coordinates (which can be denoted as set Z) into an independent partition.

[0051] S163. For the set of discrete devices with non-all-zero coordinates (which can be denoted as set Q), select a space-filling curve with good locality and sort the discrete devices into an ordered sequence according to steps S141 and S142.

[0052] S164. Establish an array (which can be denoted as array B) with the same length as the set of discrete devices with non-all-zero coordinates, and save the positions of each discrete device in the ordered sequence of set Q on the space-filling curve of the same order.

[0053] S165. Assign the discrete devices with non-all-zero coordinates to the partition with the closest connection, obtaining a partition sequence arranged according to the attribute requirements.

[0054] S18, using a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, to obtain an independent partition composed of auxiliary modules; wherein,

[0055] It can be understood that after step S16, the number of discrete devices in the independent partition has been greatly reduced compared to the initial situation. At this time, a clustering algorithm is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, and an independent partition composed of auxiliary modules is obtained. At this point, the partitioning process ends. A partition sequence arranged according to attribute requirements and an independent partition composed of auxiliary modules are obtained, which can be used for the subsequent layout and routing of large-scale circuits. Specifically, the discrete devices in the partition sequence obtained after partitioning can be arranged in sequence in the actual circuit partition space according to the growth order of the space filling curve in the actual circuit partition space. There is no order requirement for the auxiliary modules in the independent partition. They can be inserted where needed in the actual circuit partition space or laid out separately in an area. One example of a partitioning effect can be as follows Figure 4 As shown, C1, C2, M1 and M2 are circuit modules of each chip respectively.

[0056] The above-mentioned large-scale circuit partitioning method based on space-filling curves divides the component entities recorded in the network table according to the attribute requirements after importing the network table. The division is based on the connection relationship recorded in the network table and uses various characteristics of the space-filling curve to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with the existing circuit partitioning technology, the above scheme is first based on the attribute vector. The functional module sequence after sorting by the space filling curve will show corresponding characteristics and facilitate subsequent processing. For example, the space filling curve with good locality can allow the functional modules requiring the same voltage to be concentrated in a certain section of the partition sequence. During layout, this section can be placed in the same area to reduce the use of power conversion modules; secondly, since the space filling curve itself can fill the entire geometric space of the actual circuit partition space, the partition sequence after sorting and partitioning can be directly mapped to the actual circuit partition space, and the subsequent layout design in the actual circuit partition space can be automatically completed with the help of the size of the components; in addition, the partitioning process is combined with the number of components to ensure the balance of the number of components in each partition, reasonably control the density of components, and improve the quality of partitioning; finally, when the order of the space filling curve is small, if the scale of components in the partition is still too large, each partition can execute subsequent partitioning content in parallel to speed up the partitioning process and reduce time overhead.

[0057] In one embodiment, Figure 5 As shown, the above step S142, sorting the functional modules in the attribute space according to the growth direction of the space filling curve, may include the steps of:

[0058] Obtain the maximum value on each dimension of the attribute vector to form a bounding box that encloses all vectors; the bounding box is the first parent space;

[0059] Divide the parent space evenly into the same number of subspaces according to the number of sequence numbers in the growth pattern, and correspond the sequence numbers to the subspaces one by one according to the growth direction of the space-filling curve;

[0060] If the current order of the space-filling curve is 1, the sequence number of the subspace where the attribute vector is located is the sequence number of the subspace in the growth pattern;

[0061] If the current order of the space-filling curve is greater than 1, the sequence number of the subspace where the attribute vector is located is the number of subspaces that already exist in front of its parent space, plus the sequence number of the subspace where it is located in the growth pattern;

[0062] Take the currently existing subspaces as parent spaces, and repeat the steps of dividing the parent space evenly into the same number of subspaces according to the number of sequence numbers in the growth pattern and corresponding the sequence numbers to the subspaces one by one according to the growth direction of the space-filling curve until, if the current order of the space-filling curve is greater than 1, the sequence number of the subspace where the attribute vector is located is the number of subspaces that already exist in front of its parent space, plus the sequence number of the subspace where it is located in the growth pattern, until each subspace contains only 1 attribute vector;

[0063] Exchange and sort the functional module sequences according to the relative positions of the attribute vectors on the space-filling curve.

[0064] Specifically, (1) Obtain the maximum value on each dimension of the attribute vector to form a bounding box that encloses all vectors; the bounding box is the first parent space; (2) Divide the parent space evenly into the same number of subspaces according to the number of sequence numbers in the growth pattern Di, and correspond the sequence numbers to the subspaces one by one according to the growth direction of the space-filling curve; (3) If the current order of the space-filling curve is 1, for the attribute vector Ai (1 ≤ i ≤ n), the sequence number of the subspace where it is located is the sequence number of this subspace in the growth pattern Di, and jump to (5); (4) If the current order of the space-filling curve is greater than 1, for the attribute vector Ai, the sequence number of the subspace where the attribute vector Ai is located is the number of subspaces that already exist in front of the parent space where the attribute vector Ai is located, plus the sequence number of the subspace where the attribute vector Ai is located in the growth pattern Di. Among them, for different space-filling curves, the number of subspaces in front of the current subspace can be calculated according to the serial number of the parent space of the current subspace; (5) Take the currently existing subspaces as parent spaces and repeat steps (2) to (4) until each subspace contains only 1 attribute vector; (6) Exchange and sort the functional module sequences according to the relative positions of the attribute vectors on the space-filling curve.

[0065] In one embodiment, step S143 above, which evenly partitions the sorted functional modules using the dynamic programming method, may include the steps:

[0066] If the number of partitions is not input, then each functional module is a partition;

[0067] If the number of partitions y is input, then the functional module sequence is evenly divided into y parts using the dynamic programming method in combination with the component quantity sequence;

[0068] Create and initialize an array Ep of the same length as the component list; among them, the initialization rule of the array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a certain partition, the corresponding position is the partition number of the partition where it is located.

[0069] Specifically, if the number of partitions is not input, then each functional module is a partition, and jump to step S16; if the number of partitions y is input, then the functional module sequence M is evenly divided into y parts using the existing dynamic programming method in combination with the component quantity sequence W; create and initialize an array Ep of the same length as the component list E; among them, the initialization rule of the array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a certain partition, the corresponding position is the partition number of the partition where it is located.

[0070] In one embodiment, as Figure 6 shown, step S161 above, which respectively establishes a y-dimensional anchoring coordinate P for each discrete device in the discrete device set, and the value of each dimension is the number of pins connecting the current component to the corresponding partition, may include the following processing:

[0071] Initialize all coordinate values of the anchoring coordinate to 0;

[0072] Sequentially find the name Ename of the component corresponding to the position where the value in the array Ep is -1;

[0073] Retrieve the target network containing Ename in the netlist according to the name, and obtain the array C of the names of other components connecting the pins of the target network to this component;

[0074] If the name array C is not empty, then traverse the name array C, query the partition number corresponding to the name in the array Ep, and increment the dimension corresponding to the partition number in the anchoring coordinate P by 1;

[0075] If the name array C is empty, repeat the steps of retrieving the target network containing Ename in the netlist according to the name, and obtaining the name array C of other components connected to the pins of the component until the name array C is not empty. Then, traverse the name array C, query the partition number corresponding to the name in the array Ep, and increment the dimension of the anchor coordinate P corresponding to the partition number until the anchor coordinate is constructed.

[0076] Specifically: (a) Initialize all coordinate values of the anchor coordinate P to 0; (b) Sequentially find the name Ename of the component corresponding to the position where the value in the array Ep is -1; (c) Retrieve the target network containing Ename in the netlist according to the name, and obtain the name array C of other components connected to the pins of the component; (d) If the name array C is empty, jump to step (f); (e) Otherwise, traverse the name array C, query the partition number corresponding to the name in the array Ep, and increment the dimension of the anchor coordinate P corresponding to the partition number; (f) Repeat steps (c) to (e) until the anchor coordinate P is constructed.

[0077] In one embodiment, for step S165 above, the discrete devices with non - all - zero coordinates are assigned to the most closely connected partition to obtain a partition sequence arranged according to the attribute requirements. Specifically, the process of assigning the sorted discrete device set Q to y partitions may include the following processing:

[0078] Divide the ordered discrete device set Q into multiple subsets in the arranged order;

[0079] For each subset, add up the coordinate values on each coordinate axis of all coordinates in the subset to obtain y sum values;

[0080] The discrete device set corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest of the y sum values.

[0081] Specifically: (I) Divide the ordered discrete device set Q into multiple subsets in the arranged order; among them, as Figure 6As shown, the partitioning method is as follows: starting from the second component, traverse the ordered sequence of set Q, calculate the position difference between each component and the previous component on the space-filling curve using array B, and perform cutting at places where the position difference is too large to ensure that the components in the same subset have a small difference in position on the same-order space-filling curve. Among them, the determination value for whether the specific position difference is too large can be set according to the specific component density on the same-order space-filling curve. For example, for a relatively large component density, the determination value can be decreased, and for a relatively small component density, the determination value can be increased. The most specific value can be set based on the specific component density on the space-filling curve combined with experience; (II) for each subset obtained after cutting, add up the coordinate values of all coordinates on each coordinate axis of the subset to obtain y sum values; (III) the discrete device set corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest of the y sum values.

[0082] In one embodiment, regarding step S18 above, the partitioning of the components in the independent partition using the clustering algorithm may include:

[0083] Read the netlist information, and construct an undirected graph with the components in the independent partition as the node set and the connections between devices as the edge set;

[0084] Use the spectral clustering algorithm to partition the undirected graph to obtain independent auxiliary modules. Among them, the process of spectral clustering using the spectral clustering algorithm is as follows: construct a Laplacian matrix using the similarity matrix and adjacency matrix of the undirected graph, use the lanczos (an iterative algorithm) method to calculate the eigenvectors of the first k smallest eigenvalues of the Laplacian matrix, and perform kmeans clustering on the eigenvectors to obtain each auxiliary module, where k is an integer greater than 0.

[0085] Specifically: First, read the netlist information, and construct an undirected graph G(V, E) with the components in the independent partition as the node set V and the connections between devices as the edge set E; then, construct a Laplacian matrix using the similarity matrix and adjacency matrix of the undirected graph G; next, use the lanczos method to calculate the eigenvectors of the first k smallest eigenvalues of the Laplacian matrix; finally, perform kmeans clustering (an unsupervised learning algorithm for partitioning data points into different classes (clusters)) on the eigenvectors to obtain each auxiliary module.

[0086] In some embodiments, one example may be: obtain the attribute vectors A = (V, C) of voltage and clock for which the functional module M has arrangement requirements, require that devices with similar voltage and similar clock are also close in position, and select the Hilbert curve to map the 2D vector space to a 1D space to obtain a functional module sequence that meets the attribute arrangement requirements. The first 3 orders of the Hilbert curve are generated as Figure 7 shown Figure 7 (a) is the 1st orderFigure 7 (b) is of order 2, Figure 7 (c) is of order 3; its process includes:

[0087] Step 1, initialize the growth pattern of the Hilbert curve; here the attribute vector is a 2D vector, and there are 8 patterns for the 2D Hilbert curve, as Figure 8 shown.

[0088] Step 2, sort the functional modules in the attribute space according to the growth direction of the Hilbert curve, including:

[0089] Step 2-1, obtain the maximum and minimum values Vmax, Vmin, Cmax, Cmin on each dimension of the attribute vector, and form a bounding box Bd that contains all the attribute vectors. The bounding box Bd is the first parent space;

[0090] Step 2-2, evenly divide the parent space into the same number of subspaces according to the number of serial numbers in the growth pattern Di (1 ≤ i ≤ 8), and correspond the serial numbers to the subspaces one by one according to the growth direction of the space-filling curve;

[0091] Step 2-3, if the current order of the space-filling curve is 1, then for vector A, the serial number of the subspace it is in is the serial number of this subspace in the pattern Di (1 ≤ i ≤ 8), and jump to Step 2-5;

[0092] Step 2-4, if the current order of the space-filling curve is greater than 1, then for vector A, with the serial number x of its parent space and the serial number y of the current subspace in the pattern, the serial number of the subspace it is in is 4 x + y + 1;

[0093] Step 2-5, regard the existing subspaces as parent spaces and repeat Steps 2-2 to 2-4 until each subspace contains only 1 vector;

[0094] Step 2-6, exchange the functional module sequence according to the relative positions of the vectors on the space-filling curve; the serial number of the functional module M is equal to the serial number of its corresponding vector A arranged on the Hilbert curve, as Figure 9 shown, where the circular dots represent the functional modules.

[0095] It should be understood that although Figures 1 to 3 the steps in are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover Figures 1 to 3At least a part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0096] In one embodiment, as Figure 10 shown, a large-scale circuit partitioning device 100 based on a space-filling curve is provided, which may include an information acquisition module 11, a device partitioning module 13, a vector partitioning module 15, a partitioning arrangement module 17, and an auxiliary partitioning module 19. Among them, the information acquisition module 11 is used to read the netlist of the large-scale circuit and obtain circuit diagram information; the circuit diagram information includes a set of component lists and a set of network connection relationships of the components. The component list includes the component name, value, and package method, and the component network connection relationship includes the network name, the component, and the pins used by the component. The device partitioning module 13 is used to cut off the attribute network and, based on whether it is connected to an integrated chip, divide all the components connected to the integrated chip into each functional module and divide all the components not connected to the integrated chip into the discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network, and a control network. The vector partitioning module 15 is used to construct an attribute vector with the attribute values required by the functional module and map it to a one-dimensional value via a space-filling curve, obtain an ordered sequence of attribute vectors, and evenly divide it into multiple partitions. The partitioning arrangement module 17 is used to allocate the discrete devices in the discrete device set to the partition that is most closely connected to the discrete device, obtain a partition sequence arranged according to the attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partition into an independent partition. The auxiliary partitioning module 19 is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship by using a clustering algorithm, and obtain an independent partition composed of the auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and wiring of the large-scale circuit.

[0097] The above large-scale circuit partitioning device 100 based on space-filling curves divides the component entities recorded in the netlist according to attribute requirements after importing the netlist. This division is based on the connection relationships recorded in the netlist and utilizes various characteristics of space-filling curves to optimize the circuit partitioning process and improve the efficiency of circuit physical design. Compared with existing circuit partitioning technologies, the above solution is first based on the attribute vector. The functional module sequence sorted by the space-filling curve will exhibit corresponding characteristics for subsequent processing. For example, a space-filling curve with good locality can make the functional modules that require the same voltage concentrated in a certain segment of the partitioning sequence. During layout, this segment can be placed in the same area to reduce the use of power conversion modules. Secondly, since the space-filling curve itself can fill the entire geometric space of the actual circuit partitioning space, the partitioning sequence after sorting and partitioning can be directly mapped into the actual circuit partitioning space, and combined with the sizes of the components, the subsequent layout design in the actual circuit partitioning space can be automatically completed. In addition, the partitioning process combines the number of components to ensure that the number of components in each partition is balanced, reasonably control the component density, and improve the partitioning quality. Finally, when the order of the space-filling curve is small, if the scale of the components in the partition is still too large, each partition can execute the subsequent partitioning content in parallel to accelerate the partitioning process and reduce the time overhead.

[0098] In one embodiment, the vector partitioning module 15 may include:

[0099] A box construction sub-module, configured to obtain the maximum value on each dimension of the attribute vector to form a bounding box containing all the vectors; the bounding box is the first parent space;

[0100] A space correspondence sub-module, configured to evenly divide the parent space into the same number of sub-spaces according to the number of serial numbers in the growth mode, and correspond the serial numbers to the sub-spaces one by one according to the growth direction of the space-filling curve;

[0101] A serial number determination sub-module, configured to, when the current order of the space-filling curve is 1, the serial number of the sub-space where the attribute vector is located is the serial number of the sub-space in the growth mode; when the current order of the space-filling curve is greater than 1, the serial number of the sub-space where the attribute vector is located is the number of sub-spaces existing in front of its own parent space, plus the serial number of its own sub-space in the growth mode;

[0102] A loop sub-module, configured to regard the currently existing sub-spaces as parent spaces and jump to the space correspondence sub-module until each sub-space contains only 1 attribute vector;

[0103] An exchange sorting sub-module, configured to perform exchange sorting on the functional module sequence according to the relative positions of the attribute vectors on the space-filling curve.

[0104] In one embodiment, when the vector partitioning module 15 evenly partitions the sorted functional modules using dynamic programming: if the number of partitions is not input, each functional module is a partition; if the number of partitions y is input, the functional module sequence is evenly divided into y parts using dynamic programming in combination with the component quantity sequence; a new array Ep of the same length as the component list is created and initialized; wherein, the initialization rule of the array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a certain partition, the corresponding position is the partition number of the partition where it is located.

[0105] In one embodiment, when the partition arrangement module 17 constructs an anchoring coordinate with a dimension size of the number of partitions for each discrete device in the discrete device set, and the value of each dimension is the number of pins of the discrete device connecting to the corresponding partition, it is used for: initializing all coordinate values of the anchoring coordinate to 0; sequentially searching for the name Ename of the component corresponding to the position where the value in the array Ep is -1; retrieving the target network containing Ename in the netlist according to the name, and obtaining the array C of the names of other components connecting the pins of this component; if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and increment the dimension corresponding to the partition number in the anchoring coordinate P by 1; if the name array C is empty, repeat the step of retrieving the target network containing Ename in the netlist according to the name and obtaining the array C of the names of other components connecting the pins of this component until the name array C is not empty, then traverse the name array C, query the partition number corresponding to the name in the array Ep, and increment the dimension corresponding to the partition number in the anchoring coordinate P by 1 until the anchoring coordinate is constructed.

[0106] It can be understood that for the explanations of the features in the above large-scale circuit partitioning device 100 based on the space-filling curve, the corresponding explanations in the respective embodiments of the above large-scale circuit partitioning method based on the space-filling curve can be referred to and understood in the same way. Each module in the above large-scale circuit partitioning device 100 based on the space-filling curve can be implemented in whole or in part through software, hardware, and their combination. The above components can be embedded in or independent of a device with data processing functions in hardware form, or stored in the memory of the aforementioned device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules. The aforementioned device can be, but is not limited to, various types of circuit design computers existing in the art.

[0107] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, abbreviated as RDRAM), and interface dynamic random access memory (DRDRAM), etc.

[0108] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0109] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A large-scale circuit partitioning method based on space filling curves, characterized in that: Includes steps: Read the network table of a large-scale circuit to obtain circuit diagram information; the circuit diagram information includes a component list set and a component network connection relationship set, the component list includes component name, value and packaging method, and the component network connection relationship includes network name, component and its used pins; Cut off the attribute network and divide all components connected to the integrated chip into functional modules based on whether the integrated chip is connected or not, and divide all components not connected to the integrated chip into discrete device sets; the attribute network includes a power network, a ground network, a timing network, a data network, an address network and a control network; An attribute vector is constructed with the attribute values ​​required by the functional module and mapped to a one-dimensional value via a space filling curve, so as to obtain an ordered attribute vector sequence and evenly divide it into a plurality of partitions; wherein, a space filling curve is selected and a space filling curve growth mode is initialized, the functional modules are sorted in the attribute space according to the growth direction of the space filling curve, and the sorted functional modules are evenly partitioned using a dynamic programming method, wherein the space filling curve is a Hilbert curve, a Z curve or a Peano curve; Assign the discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge the discrete devices that have no connection relationship with the current existing partition into an independent partition; A clustering algorithm is used to divide discrete devices in an independent partition into independent auxiliary modules according to topological relationships, thereby obtaining an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

2. The large-scale circuit partitioning method based on space filling curve according to claim 1, characterized in that: In the step of constructing an attribute vector with the attribute values ​​required by the functional module and mapping it to a one-dimensional value via a space filling curve, obtaining an ordered attribute vector sequence and evenly dividing it into a plurality of partitions, when the functional modules are sorted in the attribute space according to the growth direction of the space filling curve, the steps include: Get the maximum value of each dimension in the attribute vector to form a bounding box containing all vectors; the bounding box is the first parent space; The parent space is evenly divided into the same number of subspaces according to the number of sequence numbers in the growth pattern, and the sequence numbers are matched one by one with the subspaces according to the growth direction of the space filling curve; If the order of the current space-filling curve is 1, the sequence number of the subspace where the attribute vector is located is the sequence number of the subspace in the growth mode; If the order of the current space filling curve is greater than 1, the sequence number of the subspace where the attribute vector is located is the number of subspaces that already exist in the parent space where the attribute vector is located, plus the sequence number of the subspace where the attribute vector is located in the growth mode; The currently existing subspace is regarded as the parent space, and the steps of uniformly dividing the parent space into the same number of subspaces according to the number of serial numbers in the growth pattern, and corresponding the serial numbers to the subspaces one by one according to the growth direction of the space filling curve are repeated until the step of if the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces that existed before the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth pattern, until each subspace contains only one attribute vector; The functional module sequences are exchanged and sorted according to the relative positions of the attribute vectors on the space filling curve.

3. The large-scale circuit partitioning method based on space filling curve according to claim 1 or 2, characterized in that: In the step of constructing an attribute vector with the attribute values ​​required by the functional module and mapping it to a one-dimensional value via a space filling curve, obtaining an ordered attribute vector sequence and evenly dividing it into a plurality of partitions, the steps of evenly partitioning the ordered functional modules using a dynamic programming method include: If the number of partitions is not entered, each functional module is a partition; If the number of partitions y is entered, the functional module sequence is evenly divided into y parts using a dynamic programming method in combination with the number of components sequence; Create a new array Ep with the same length as the component list and initialize it; the initialization rule of array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

4. The method for partitioning a large-scale circuit based on a space filling curve according to claim 3, characterized in that: The discrete devices in the discrete device set are assigned to the partitions that are most closely connected to the discrete devices, and a partition sequence arranged according to the attribute requirements is obtained. In the step of merging the discrete devices that have no connection relationship with the current existing partition into an independent partition, an anchor coordinate with a dimension size of the number of partitions is constructed for each discrete device in the discrete device set, and the value of each dimension is the number of pins of the discrete device connected to the corresponding partition, including the steps of: Initialize all coordinate values ​​of the anchor coordinates to 0; Search the position with value -1 in array Ep for the name Ename of the component corresponding to it; Retrieve the target network in the network table that contains Ename according to the name, and obtain the name array C of other components connected to the pins of the component in the target network; If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; If the name array C is empty, repeat the steps of retrieving the target network containing Ename in the network table according to the name, obtaining the name array C of other components connected to the pin of the component by the target network, and if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P until the anchor coordinate is constructed.

5. The large-scale circuit partitioning method based on space filling curve according to claim 4, characterized in that: The discrete devices in the discrete device set are assigned to the partitions that are most closely connected to the discrete devices to obtain a partition sequence arranged according to the attribute requirements, and the discrete devices that have no connection relationship with the current existing partitions are merged into an independent partition. The discrete devices whose coordinates are not all 0 are assigned to the partitions that are most closely connected to obtain the partition sequence arranged according to the attribute requirements, including the steps of: Divide the ordered discrete device set Q into a plurality of subsets according to the arranged order; For each subset, add the coordinate values ​​of all coordinates in the subset on each coordinate axis to get the y sum value; The set of discrete devices corresponding to the subset belongs to the partition corresponding to the coordinate axis with the largest y sum value.

6. The large-scale circuit partitioning method based on space filling curve according to claim 3, characterized in that: In the process of using a clustering algorithm to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship, the division process includes: Read the network table information, and construct an undirected graph with the components of the independent partitions as the node set and the connections between the components as the edge set; The spectral clustering algorithm is used to partition the undirected graph into independent auxiliary modules.

7. A large-scale circuit partitioning device based on space filling curves, characterized in that: include: An information acquisition module is used to read the network table of a large-scale circuit and obtain circuit diagram information; The circuit diagram information includes a component list set and a component network connection relationship set, the component list includes component names, values ​​and packaging methods, and the component network connection relationship includes network names, components and pins used by them; A device division module is used to cut off the attribute network and divide all components connected to the integrated chip into functional modules based on whether they are connected to the integrated chip and divide all components not connected to the integrated chip into a discrete device set; the attribute network includes a power network, a ground network, a timing network, a data network, an address network and a control network; A vector partitioning module is used to construct an attribute vector with the attribute values ​​required by the functional module and map it to a one-dimensional value via a space filling curve, so as to obtain an ordered attribute vector sequence and evenly divide it into a plurality of partitions; wherein, a space filling curve is selected and a growth mode of the space filling curve is initialized, the functional modules are sorted in the attribute space according to the growth direction of the space filling curve, and the sorted functional modules are evenly partitioned by a dynamic programming method, wherein the space filling curve is a Hilbert curve, a Z curve or a Peano curve; A partition arrangement module is used to allocate discrete devices in the discrete device set to the partition that is most closely connected to the discrete devices, obtain a partition sequence arranged according to attribute requirements, and merge discrete devices that have no connection relationship with the current existing partition into an independent partition; The auxiliary partition module is used to divide the discrete devices in the independent partition into independent auxiliary modules according to the topological relationship using a clustering algorithm to obtain an independent partition composed of auxiliary modules; the partition sequence and the independent partition are used to indicate the layout and routing of large-scale circuits.

8. The large-scale circuit partitioning device based on space filling curve according to claim 7, characterized in that: The vector partitioning module includes: The box construction submodule is used to obtain the maximum value of each dimension in the attribute vector and construct a bounding box containing all vectors; the bounding box is the first parent space; The space correspondence submodule is used to evenly divide the parent space into the same number of subspaces according to the number of sequence numbers in the growth pattern, and to correspond the sequence numbers to the subspaces one by one according to the growth direction of the space filling curve; The serial number determination submodule is used to determine that when the order of the current space filling curve is 1, the serial number of the subspace where the attribute vector is located is the serial number of the subspace in the growth mode; when the order of the current space filling curve is greater than 1, the serial number of the subspace where the attribute vector is located is the number of subspaces in front of the parent space where the attribute vector is located, plus the serial number of the subspace where the attribute vector is located in the growth mode; A loop submodule is used to treat the current subspace as a parent space and jump to the submodule corresponding to the space until each subspace contains only one attribute vector; The exchange sorting submodule is used to exchange and sort the functional module sequence according to the relative position of the attribute vector on the space filling curve.

9. The large-scale circuit partitioning device based on space filling curve according to claim 7 or 8, characterized in that: When the vector partitioning module uses dynamic programming to evenly partition the sorted functional modules: If the number of partitions is not entered, each functional module is a partition; If the number of partitions y is entered, the functional module sequence is evenly divided into y parts using a dynamic programming method in combination with the number of components sequence; Create a new array Ep with the same length as the component list and initialize it; the initialization rule of array Ep is: if the component is not in the existing partition, the corresponding position is set to -1; if the component is in a partition, the corresponding position is the partition number of the partition.

10. The large-scale circuit partitioning device based on space filling curve according to claim 9, characterized in that: The partition arrangement module constructs anchor coordinates with a dimension size equal to the number of partitions for each discrete device in the discrete device set, and the value of each dimension is the number of pins of the discrete device connected to the corresponding partition, and is used to: Initialize all coordinate values ​​of the anchor coordinates to 0; Search the position with value -1 in array Ep for the name Ename of the component corresponding to it; Retrieve the target network in the network table that contains Ename according to the name, and obtain the name array C of other components connected to the pins of the component in the target network; If the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P; If the name array C is empty, repeat the steps of retrieving the target network containing Ename in the network table according to the name, obtaining the name array C of other components connected to the pin of the component by the target network, and if the name array C is not empty, traverse the name array C, query the partition number corresponding to the name in the array Ep, and add 1 to the dimension corresponding to the partition number in the anchor coordinate P until the anchor coordinate is constructed.

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