LLM-based mixed size clustering method in chip design layout stage

Abstract

The embodiment of the invention provides a hybrid size clustering method based on LLM in a chip design layout stage, which belongs to the technical field of data processing, and specifically comprises the following steps: step 1, converting line net list information into an undirected graph according to an interconnection relationship; step 2, acquiring an element initial clustering result of the undirected graph by using a community discovery algorithm; and step 3, inputting the element initial clustering result into the large language model, and performing incremental adjustment on the clustering constraint of the element initial clustering result by using the large language model to obtain a final clustering result. According to the scheme of the invention, incremental adjustment is carried out on clustering constraints by using natural language processing and reasoning capabilities of a large language model. In order to further improve the efficiency and accuracy of the process, a ReAct framework is introduced, and reasoning and actions are combined, so that a large language model can generate more intelligent and context-aware responses, and accurate and efficient layout is realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data processing technology, and in particular to a mixed-size clustering method based on LLM in the chip design layout stage. Background Art

[0002] Very Large-Scale Integration (VLSI) design is a very difficult problem, spanning multiple directions such as high-performance computing, numerical optimization, and computer systems. Due to the huge number of transistors in modern chip design, up to tens of billions, it is very complex. Therefore, electronic design automation (EDA) is needed to assist chip design. Among them, starting from the logic netlist, the design process includes floorplanning, layout, clock tree synthesis, wiring and other steps. Completing the placement of macro cells and standard cells in the layout stage determines the location of circuit elements on the chip. It is a critical and time-consuming step in physical design, which is not only related to the performance, reliability and cost of the circuit, but also directly affects the success rate of the design. Accurate and efficient layout plays a decisive role in improving chip performance, reducing power consumption and enhancing reliability.

[0003] Layout is usually divided into three stages: 1) Global layout performs preliminary placement of all circuit components to ensure that the relative positions between components are reasonable and optimize layout goals, such as line length. 2) Legalization stage adjusts component positions according to global layout results to ensure legal placement, such as overlapping and row placement. 3) Detailed layout is a stage for fine-tuning component positions to further improve optimization goals such as circuit performance. Modern layout tools support mixed sizes, i.e. macro modules and standard cells. However, due to the huge difference in size between standard cells and macro modules, mixed size layout problems are more complicated than pure standard cell layout problems.

[0004] It can be seen that there is an urgent need for a mixed-size clustering method based on LLM in the chip design layout phase with high layout performance to assist in optimizing the mixed-size layout. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a mixed-size clustering method based on LLM in the chip design layout stage, which at least partially solves the problem of poor layout performance in the prior art.

[0006] The embodiment of the present invention provides a mixed-size clustering method based on LLM in the chip design layout stage, comprising: Step 1, converting the line network netlist information into an undirected graph according to the interconnection relationship; Step 2, using a community discovery algorithm to obtain the initial clustering results of the components of the undirected graph; Step 3: Input the initial clustering results of the components into the large language model, and use the large language model to incrementally adjust the clustering constraints of the initial clustering results of the components to obtain the final clustering results.

[0007] According to a specific implementation of the embodiment of the present invention, step 1 specifically includes: Step 1.1, process the network netlist information and convert it into an undirected graph G=(V,E), where V represents the set of components in the circuit and E represents the set of connection edges in the netlist; Step 1.2, set the weight of the edge in the undirected graph G to the number of connection relationships between the starting point and the end point of the undirected graph G.

[0008] According to a specific implementation of the embodiment of the present invention, step 2 specifically includes: Step 2.1: Run the modularity-based community discovery algorithm Louvain in the undirected graph G, treat each node in the undirected graph G as an independent community, traverse the neighbors of the node, select the node with the largest modularity increment to merge, and repeat the same operation on all nodes until the modularity no longer increases, and obtain the community corresponding to the new node; Step 2.2, merge the communities corresponding to each new node into a new node to generate a new undirected graph G'. In the new undirected graph G', each node represents each community, the edge is the sum of the edge weights between the two corresponding communities, and the weight of each point is the number of self-connections of the corresponding community; Step 2.3, count the components in each community in the new undirected graph G', and obtain the sum of the component areas, the number of macromodules, the number of self-connections, and the number of connections with other clusters in each community as the initial clustering result of the components.

[0009] According to a specific implementation of the embodiment of the present invention, step 3 specifically includes: Step 3.1, setting a tool set for the large language model to be automatically called in the subsequent tool chain, wherein the tool set includes merging clusters, splitting clusters, undoing the last modification operation, and viewing the current clustering information; Step 3.2, set the clustering optimization goal to obtain the minimum evaluation score; Step 3.3, the initial clustering results of the integrated components, the tool set and the clustering optimization goals are used to form user prompt words and input into the large language model. The ReAct prompt mechanism is used to control the large language model to perform dynamic reasoning to create and adjust the action plan based on the current clustering results and clustering optimization goals, and compare the two adjacent evaluation scores. When the evaluation score no longer decreases, the final clustering result is obtained.

[0010] According to a specific implementation of the embodiment of the present invention, the expression of the evaluation score is: ; in, is the standard deviation of the area of ​​all clusters in the current partition result, Q is the modularity of the current partition result, k is the number of clusters, represents the area of ​​the ith cluster, represents the mean value of cluster area; in, represents the actual edge between nodes v and w, and are the degrees of the nodes, m is the total number of edges in the graph, is an indicator of whether v and w are in the same community.

[0011] The mixed-size clustering scheme based on LLM in the chip design layout stage in the embodiment of the present invention includes: step 1, converting the wire net list information into an undirected graph according to the interconnection relationship; step 2, obtaining the initial clustering result of the components of the undirected graph by using the community discovery algorithm; step 3, inputting the initial clustering result of the components into the large language model, and using the large language model to incrementally adjust the clustering constraints of the initial clustering result of the components to obtain the final clustering result.

[0012] The beneficial effects of the embodiments of the present invention are as follows: through the scheme of the present invention, hierarchical clustering technology is used to deeply explore the interconnection relationship in the wire net list, generate multiple clusters, thereby converting complex large-scale circuit information into more easily processed small-scale cluster information, and delivering it to the large language model, using the natural language processing and reasoning capabilities of the large language model to incrementally adjust the cluster constraints. In order to further improve the efficiency and accuracy of this process, the ReAct framework is introduced, which combines reasoning and action, enabling the large language model to generate more intelligent, context-aware responses, and achieve accurate and efficient layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 A schematic diagram of a flow chart of a mixed-size clustering method based on LLM in a chip design layout stage provided by an embodiment of the present invention; Figure 2 A schematic diagram of an example of a mixed-size layout problem provided by an embodiment of the present invention; Figure 3 A schematic diagram of a large language model process for clustering optimization provided by an embodiment of the present invention; Figure 4 A schematic diagram of a process of performing clustering optimization using a large language model calling tool set provided by an embodiment of the present invention; Figure 5 An example schematic diagram of a ReAct-based Thought-Action-Observation clustering optimization step provided in an embodiment of the present invention; Figure 6 A schematic diagram of the running time of Louvain and LLM in 8 ISPD 2005 data sets provided by an embodiment of the present invention; Figure 7 A schematic diagram of a layout process framework combined with clustering provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0016] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0017] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present invention, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0018] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention. The drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0019] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0020] An embodiment of the present invention provides a mixed-size clustering method based on LLM in the layout stage of chip design. The method can be applied to the layout stage optimization process of a very large-scale integrated circuit design scenario.

[0021] See also Figure 1 , is a flow chart of a mixed-size clustering method based on LLM in a chip design layout stage provided by an embodiment of the present invention. Figure 1 As shown, the method mainly comprises the following steps: Step 1, converting the line network netlist information into an undirected graph according to the interconnection relationship; Furthermore, the step 1 specifically includes: Step 1.1, process the network netlist information and convert it into an undirected graph G=(V,E), where V represents the set of components in the circuit and E represents the set of connection edges in the netlist; Step 1.2, set the weight of the edge in the undirected graph G to the number of connection relationships between the starting point and the end point of the undirected graph G.

[0022] When implementing it, Figure 2 As shown in the figure, macro cells usually refer to larger circuit modules with complex functions, such as processors, memory arrays, data converters, etc. Standard cells refer to smaller, standardized circuit modules, such as logic gates, triggers, etc. The height of a standard cell is one or several times the row height, and the width varies according to the complexity of its function. The layout requires the standard cells to be placed in rows. The layout of macro cells is usually done manually, or mixed with standard cells.

[0023] Layout is usually divided into three stages: 1) Global layout performs preliminary placement of all circuit components to ensure that the relative positions between components are reasonable and optimize layout goals, such as line length. 2) Legalization stage adjusts component positions according to global layout results to ensure legal placement, such as overlapping and row placement. 3) Detailed layout is a stage for fine-tuning component positions to further improve optimization goals such as circuit performance. Modern layout tools support mixed sizes, i.e. macro modules and standard cells. However, due to the huge difference in size between standard cells and macro modules, mixed size layout problems are more complicated than pure standard cell layout problems.

[0024] Clustering technology plays a vital role in modern integrated circuit design. In order to improve design efficiency and optimize performance, power consumption and area (PPA) indicators. Since the system design adopts a hierarchical modular approach, the clustering technology of the wire net can be combined in the mixed-size layout to cluster the components with the same module or close interconnection relationship together, guide the layout to help design optimization, and improve design efficiency, such as reducing wiring length, optimizing signal transmission delay, and improving overall circuit performance. These advantages make clustering an indispensable part of modern integrated circuit design.

[0025] In specific implementation, the wire network netlist information can be processed first and converted into an undirected graph G=(V,E), where V represents the set of components in the circuit, E represents the set of connection edges in the netlist, and the weight of the edge in the undirected graph G is set to the number of connection relationships between the starting point and the end point of the undirected graph G.

[0026] Step 2, using a community discovery algorithm to obtain the initial clustering results of the components of the undirected graph; Based on the above embodiment, step 2 specifically includes: Step 2.1: Run the modularity-based community discovery algorithm Louvain in the undirected graph G, treat each node in the undirected graph G as an independent community, traverse the neighbors of the node, select the node with the largest modularity increment to merge, and repeat the same operation on all nodes until the modularity no longer increases, and obtain the community corresponding to the new node; Step 2.2, merge the communities corresponding to each new node into a new node to generate a new undirected graph G'. In the new undirected graph G', each node represents each community, the edge is the sum of the edge weights between the two corresponding communities, and the weight of each point is the number of self-connections of the corresponding community; Step 2.3, count the components in each community in the new undirected graph G', and obtain the sum of the component areas, the number of macromodules, the number of self-connections, and the number of connections with other clusters in each community as the initial clustering result of the components.

[0027] In the specific implementation, in order to merge and reduce the dimension of the circuit, we use hierarchical clustering technology to deeply explore the interconnection relationship in the wire netlist and generate multiple clusters, thereby converting complex large-scale circuit information into more easily processable small-scale cluster information. For example, the community discovery algorithm Louvain based on the greedy strategy can be used to obtain the initial clustering results. It identifies the community structure in the network by maximizing the modularity (Equation 2). The core idea of ​​the Louvain algorithm is to continuously aggregate nodes into communities and maximize the connectivity within the community while weakening the connection between communities. This community attribute has a natural correlation with circuit layout: by mining the community of all components in the circuit, a community can be regarded as a cluster of components after clustering. By placing components in the same cluster closer, the line length can be significantly optimized.

[0028] Step 3: Input the initial clustering results of the components into the large language model, and use the large language model to incrementally adjust the clustering constraints of the initial clustering results of the components to obtain the final clustering results.

[0029] Based on the above embodiment, step 3 specifically includes: Step 3.1, setting a tool set for the large language model to be automatically called in the subsequent tool chain, wherein the tool set includes merging clusters, splitting clusters, undoing the last modification operation, and viewing the current clustering information; Step 3.2, set the clustering optimization goal to obtain the minimum evaluation score; Step 3.3, the initial clustering results of the integrated components, the tool set and the clustering optimization goals are used to form user prompt words and input into the large language model. The ReAct prompt mechanism is used to control the large language model to perform dynamic reasoning to create and adjust the action plan based on the current clustering results and clustering optimization goals, and compare the two adjacent evaluation scores. When the evaluation score no longer decreases, the final clustering result is obtained.

[0030] Furthermore, the expression of the evaluation score is: ; in, is the standard deviation of the area of ​​all clusters in the current partition result, Q is the modularity of the current partition result, k is the number of clusters, represents the area of ​​the ith cluster, represents the mean value of cluster area; in, represents the actual edge between nodes v and w, and are the degrees of the nodes, m is the total number of edges in the graph, is an indicator of whether v and w are in the same community.

[0031] In specific implementation, the Louvain method can effectively identify closely connected components, thereby achieving bottom-up hierarchical clustering and guiding the placement of components in subsequent layout. However, Louvain only considers the connection relationship of the "graph", which is logically very consistent with the needs of layout; but on the other hand, Louvain does not consider factors such as cluster area and the number of macro modules in the cluster. These factors may cause the generated clusters to be unbalanced, thus affecting the subsequent layout effect. Therefore, LLM can be introduced to further optimize the clustering results.

[0032] In order to obtain better pre-layout results in the layout stage, the key is to adopt a reasonable and efficient mixed-size component clustering strategy. This strategy aims to group components into multiple component clusters according to specific rules, and strives to achieve two major goals: first, to ensure that the areas of each component cluster remain highly consistent after clustering, so as to avoid the positioning difficulties caused by component clusters that are too large or too small in the pre-layout stage; second, to control the number of macro modules in each component cluster within a reasonable range to prevent the subsequent layout process from being difficult to converge due to too many macro modules. In addition, an ideal component cluster should exhibit the characteristics of tight internal connections and sparse external connections, which can be quantitatively evaluated by modularity. The closer the modularity (Equation 2) value is to 1, the clearer the community structure division in the network, that is, the connection within the community (or component cluster) is highly tight, while the connection between communities is relatively sparse. This paper gives the following mathematical description for this clustering problem: Given a layout instance , represents the set V of n layout objects (standard cells and macro modules), and the set E of wire nets. The goal is to obtain a clustering partition ,in and and , k is the number of clusters, so that the number of macro modules in each cluster is less than the parameter When , the cluster evaluation score Cluster_score (Formula 1) is the smallest. .

[0033] Among them, the numerator is the standard deviation of the areas of all clusters in the current partitioning result, and the denominator Q is the modularity of the current partitioning result (Formula 2). k is the number of clusters. represents the area of ​​the ith cluster, represents the average cluster area. The modularity (Q) is a measure of the quality of community division and is defined as in, represents the actual edge between nodes v and w, and are the degrees of the nodes, m is the total number of edges in the graph, is an indicator of whether v and w are in the same community.

[0034] Large Language Model (LLM) is a natural language processing technology based on deep learning. It learns the laws and patterns of language by training a large amount of text data. At present, the application of LLM in place and routing (P&R) is still being explored. Contemporary designs often contain millions of cells and networks, which makes it impractical for large language models to directly solve the location and routing assignment of each component. However, the initial hierarchical clustering results based on network connectivity relationships themselves merge and reduce the dimensions of the circuits, reducing the scale of the problem. Therefore, we propose a method for large language models to optimize the results produced by hierarchical clustering to more reasonably guide subsequent layout.

[0035] The complex large-scale circuit information is converted into more tractable small-scale clustering information and delivered to the large language model (LLM). Then, we leverage the natural language processing and reasoning capabilities of the LLM to incrementally adjust the clustering constraints. To further improve the efficiency and accuracy of this process, we introduced the ReAct framework, which is an advanced high-level language model architecture that combines reasoning and action to enable large language models to generate more intelligent, context-aware responses. It involves multiple core components that work together to automate complex tasks. The following is an explanation of the core components of the ReAct framework.

[0036] Chain of Thought: It breaks down a large, complex task into multiple manageable steps of thought. This process of breaking down allows the model to reason and solve the problem step by step, rather than trying to solve the entire problem at once. In this way, the model can plan its path of action more clearly and make necessary adjustments at each step.

[0037] Reasoning: The reasoning component is responsible for analyzing and processing input data to generate effective decisions.

[0038] Action: The action component selects and executes specific operations based on the reasoning results.

[0039] Observation: The observation component is responsible for monitoring and collecting data from the environment.

[0040] We use the ReAct framework to enable large language models (LLMs) to act as agents for autonomous clustering design. Figure 3As shown: In the initial stage, LLM receives prompts provided by the user, which include initial clustering information, text describing specific optimization goals, and description text of the external function tool Tool. Next, in the reasoning stage, LLM analyzes the input information, generates a series of reasoning steps or "thinking chains", and plans subsequent clustering optimization plans. In the action stage, based on the reasoning results, LLM selects and performs specific operations. At this time, the external function tool Tool can be called to query or adjust the optimization clustering results. In the observation stage, LLM monitors the return results of the external function tool Tool, updates its internal state and decision basis based on the new data, and then reasons and acts again. This process will be repeated until the task is completed or iterates to the specified number of rounds.

[0041] The designer inputs the initial clustering information as features. The specific clustering related features and their types are shown in Table 1, including the area of ​​each cluster, the number of macromodules contained, the number of self-connections in the cluster, and the connection relationship with other clusters (the names of other clusters and the number of connections between them and this cluster are stored in a list).

[0042] Table 1

[0043] LLM receives this information and a description of the clustering goal, which is to minimize the clustering result to obtain the minimum Cluster_score. The ReAct prompt method allows LLM to perform dynamic reasoning based on the current clustering information and clustering goals to create and adjust the action plan (from reasoning to action), while also interacting with external tools. Therefore, we set up clustering-related tools with the following functions for LLM to call to optimize the current clustering results: merge clusters (Merge_clusters), split clusters (Split_clusters), undo the modification operation (Undo_the_modify_operation), and view the current cluster information (Get_current_cluster_info).

[0044] Merge clusters (Merge_clusters): This tool is used to merge two closely connected clusters into one Cluster, update the current clustering result, and return the evaluation score of the current clustering result.

[0045] Split clusters (Split_clusters): This tool is used to split a large cluster into several small clusters. The splitting method is to call the Louvain partitioning method again in this large cluster, update the current clustering result, and return the evaluation score of the current clustering result.

[0046] Undo_the_modify_operation: This tool will undo the previous modification step, return the clustering state to the state before the most recent modification, and return the evaluation score of the clustering result at this time.

[0047] View current cluster information (Get_current_cluster_info): This tool is used to obtain information about the current cluster status, including the area of ​​each cluster, the number of macro modules it contains, the number of self-connections, the connection relationship with other clusters, and return the evaluation score of the clustering result at this time.

[0048] Figure 4 The figure shows the possible operations that LLM may perform during cluster optimization. The gray circles represent macro modules, the white circles represent standard units, the lines between the components represent the connections between clusters, and the connections within the clusters are not drawn. Before optimization, there are multiple connections between C1 and C2, and the areas of these two clusters are relatively small. LLM tends to merge these clusters in the action phase, and C1 and C2 are merged into C1_C2_merge. For C4, before optimization, the area of ​​C4 is relatively large. LLM may infer that splitting these clusters can reduce the overall area standard deviation of all clusters, and ultimately reduce Cluster_Score. In the figure, C4 is decomposed into C4_1_split and C4_2_split of appropriate area sizes.

[0049] Through the ReAct prompt mechanism, we enable LLM to act as an agent that updates clustering autonomously, using reasoning, action, and observation components to complete the cycle of reasoning clustering optimization plan (Reason) and executing actions (Action). In the action phase, the agent calls the clustering related tools described in IV-C, and the results returned are used as the prompt words required for Observation. Then the agent continues to reason and act until the "Final answer" action is selected or a certain number of iterations are reached. Figure 5An example of optimizing clustering results is shown. The user prompts the Agent to obtain a better clustering, requiring the area standard deviation of the new clustering result to be as small as possible, the modularity to be as high as possible, and the number of macromodules in each cluster to be maintained at an appropriate value, so as to obtain a better score. At first, the Agent used Get_current_cluster_info to view the information of the current cluster. In order to obtain better results, the Agent performed reasoning analysis, and then called Split_the_cluster to decompose the current large area c41. The overall cluster area standard deviation was reduced from 7761662 to 7415746. After further trial and error optimization steps, the Agent finally determined that the current clustering result was the best and selected the "Final answer" action.

[0050] The mixed-size clustering method based on LLM in the chip design layout stage provided in this embodiment uses hierarchical clustering technology to deeply explore the interconnection relationship in the wire net list and generate multiple clusters, thereby converting complex large-scale circuit information into more easily processed small-scale cluster information, and delivering it to the large language model, using the natural language processing and reasoning capabilities of the large language model to incrementally adjust the clustering constraints. In order to further improve the efficiency and accuracy of this process, the ReAct framework is introduced, which combines reasoning and action, enabling the large language model to generate more intelligent, context-aware responses and achieve accurate and efficient layout.

[0051] The method of the present invention will be further described below in conjunction with a specific embodiment. The work in this paper is implemented in Python and LangChain. We performed all experiments with gpt-4o-mini as LLM through the OpenAI api. We set the sampling temperature of the LLM to 0.7. For ReAct, we limited the LLM to a maximum of 20 think-act-observe iterations. The evaluation was then performed on a server equipped with an Intel Xeon Core (@3.20 GHz) and 256 GB DDR4 memory.

[0052] To verify the superiority of our method in hybrid layout performance, we applied our clustering method to the ISPD 2005 competition benchmark and large industrial designs. Table 2 gives the parameters of the experimental circuit design. All cases are relatively large, containing hundreds or thousands of macro modules.

[0053] Table 2

[0054] Clustering effect analysis based on LLM: Table 3 shows the effect of using LLM to optimize the Louvain clustering results. Among them, the "Clusters" column indicates the number of component clusters contained in the final clustering result, and the "Final score" indicates the score of the final clustering result, which is calculated by the indicator introduced in Part II (see Formula 1) and is used to evaluate the quality of the clustering results. As can be seen from the table, for the Adaptec2, Adaptec3, Adaptec4 and Bigblue1 datasets, the Louvain clustering results are already quite reasonable, so LLM did not further optimize them, and their "Clusters" and "Final score" remained unchanged. For the Adaptec1, Bigblue2, Bigblue3 and Bigblue4 datasets, the initial clustering results obtained a smaller cluster area standard deviation and a higher modularity Q value after further splitting and merging operations by LLM, thereby obtaining a higher score.

[0055] Table 3

[0056] Figure 6 The figure shows the running time of Louvain and LLM steps in the ISPD2005 competition benchmark. In Adaptec2, Adaptec3, and Adaptec4, the LLM judged that the results were reasonable at the beginning of the iteration, so the optimization was completed early and the running time was short. Bigblue1 tried to make some optimizations but failed, so the running time is similar to Adaptec1, Bigblue2, Bigblue3, and Bigblue4, mainly due to the ReAct reasoning and action loop.

[0057] Line length verification during layout phase: To further verify the effect of our clustering method on line length optimization in the layout stage, we integrated the method into the open source layouter Dreamplace and obtained the final layout line length after optimization based on the LLM clustering method. We compared it with the previous baselines (Human, DREAMPlace, and Chipformer). Specifically, we applied our method in the baseline to verify the optimization process of the layout line length after clustering, which includes the mixed-size pre-layout stage and the layout stage, while our clustering method is mainly applied in the pre-layout stage.

[0058] like Figure 7As shown in the figure, the pre-layout stage aims to obtain a reasonable initial solution for mixed-size layout. We performed a hierarchical clustering analysis on standard cells and macro modules, and obtained the final clustering results through LLM optimization. Each cluster obtained a rough layout position through the simulated annealing method. In order to determine the approximate layout position of each component, we first disassembled the cluster. For macro module components, the simulated annealing algorithm is continued to be used to optimize their position within the cluster, so as to be accurate to the specific coordinates in the layout area; while the standard components are simply set to the approximate location before the cluster to which they belong is split. This completes the pre-layout stage under mixed sizes.

[0059] In the layout phase, the main task is to further refine the final coordinates of the components. All components undergo two global layout adjustment processes: the first global layout treats the macro modules as fixed units; the second global layout is performed while allowing the macro modules to move, while performing legalization checks and detailed layout operations. After this series of steps, all components are placed in the most appropriate positions, achieving good line length performance while ensuring mixed-size layout and limited density. It is worth noting that the final layout result is closely related to the pre-layout stage.

[0060] The statistical results of DREAMPlace, Chipformer and the method in this paper are all counted after the server completes one run. The process of DREAMPlace is to set all macro modules and standard cells to be movable, complete a global layout, and then perform legalization layout and detailed layout implementation. The process of Chipformer is similar to that of this paper. After completing a pre-layout by their respective algorithms, they perform two global layouts (one to fix the macro modules and one to set all components to be movable global layout), and then perform legalization layout and detailed layout implementation.

[0061] The difference lies in the pre-layout stage: Chipformer uses the offline reinforcement learning method proposed by the author to determine the position of each macro module, while our method uses Louvain clustering and LLM optimized clustering results, and uses the simulated annealing algorithm to determine the position of each cluster, thereby determining the approximate position of each macro module and standard unit. When performing global layout, Chipformer and our parameter settings are unified using the instructions in the document "Transferable Chip Placement viaOffline Decision Transformer" (Density weight is set to 1e-4 and the number of iterations is 300 for the first global layout; Density_weight is 1e-3 for the second global layout).

[0062] Table 4 shows the comparison results of half-perimeter long lines (HPWL) after placement on the ISPD2005 competition benchmark test set. It can be seen from the table that on most datasets, our placement results have obvious advantages over DREAMPlace and Chipformer in HPWL. Except for Bigblue1, our method outperforms DREAMPlace in HPWL on all circuits. It is worth noting that Bigblue1 is characterized by the small number of large-area macro modules it contains, so our method is more suitable for circuits with more large macro modules. Compared with Chipformer, our method is still slightly better except for Bigblue1. Even considering the time consumption of Louvain clustering and LLM optimized clustering, we significantly outperform Chipformer in total placement time.

[0063] Taking into account the total HPWL on all datasets, our method is 21.81% lower than DREAMPlace and 4.39% lower than Chipformer. At the same time, our LLM optimized clustering method also shows the advantage of line length on Adaptec1, Bigblue2, and Bigblue4 over the method that only uses Louvain for clustering.

[0064] Table 4

[0065] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof.

[0066] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A mixed-size clustering method based on LLM in the chip design layout stage, characterized in that: include: Step 1, converting the line network netlist information into an undirected graph according to the interconnection relationship; Step 2, using a community discovery algorithm to obtain the initial clustering results of the components of the undirected graph; Step 3: Input the initial clustering results of the components into the large language model, and use the large language model to incrementally adjust the clustering constraints of the initial clustering results of the components to obtain the final clustering results.

2. The method according to claim 1, characterized in that The step 1 specifically includes: Step 1.1, process the network netlist information and convert it into an undirected graph G=(V,E), where V represents the set of components in the circuit and E represents the set of connection edges in the netlist; Step 1.2, set the weight of the edge in the undirected graph G to the number of connection relationships between the starting point and the end point of the undirected graph G.

3. The method according to claim 2, characterized in that The step 2 specifically includes: Step 2.1: Run the modularity-based community discovery algorithm Louvain in the undirected graph G, treat each node in the undirected graph G as an independent community, traverse the neighbors of the node, select the node with the largest modularity increment to merge, and repeat the same operation on all nodes until the modularity no longer increases, and obtain the community corresponding to the new node; Step 2.2, merge the communities corresponding to each new node into a new node to generate a new undirected graph G'. In the new undirected graph G', each node represents each community, the edge is the sum of the edge weights between the two corresponding communities, and the weight of each point is the number of self-connections of the corresponding community; Step 2.3, count the components in each community in the new undirected graph G', and obtain the sum of the component areas, the number of macromodules, the number of self-connections, and the number of connections with other clusters in each community as the initial clustering result of the components.

4. The method according to claim 3, characterized in that: The step 3 specifically includes: Step 3.1, setting a tool set for the large language model to be automatically called in the subsequent tool chain, wherein the tool set includes merging clusters, splitting clusters, undoing the last modification operation, and viewing the current clustering information; Step 3.2, set the clustering optimization goal to obtain the minimum evaluation score; Step 3.3, the initial clustering results of the integrated components, the tool set and the clustering optimization goals are used to form user prompt words and input into the large language model. The ReAct prompt mechanism is used to control the large language model to perform dynamic reasoning to create and adjust the action plan based on the current clustering results and clustering optimization goals, and compare the two adjacent evaluation scores. When the evaluation score no longer decreases, the final clustering result is obtained.

5. The method according to claim 4, characterized in that The expression of the evaluation score is: ; in, is the standard deviation of the area of ​​all clusters in the current partition result, Q is the modularity of the current partition result, k is the number of clusters, represents the area of ​​the ith cluster, represents the mean value of cluster area; in, represents the actual edge between nodes v and w, and are the degrees of the nodes, m is the total number of edges in the graph, is an indicator of whether v and w are in the same community.

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