Logic comprehensive parameter optimization method and device of circuit, equipment and medium

Abstract

The embodiment of the invention provides a logic comprehensive parameter optimization method and device of a circuit, equipment and a medium. The method comprises the following steps: acquiring an initial clock uncertainty parameter and an initial clock conversion time parameter; determining an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model; determining a time sequence score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter; determining a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter under the condition that the time sequence score and the area score meet a preset scoring condition; in this way, the optimized clock uncertainty parameter and the optimized clock conversion time parameter can be accurately calculated. The problem that parameter setting depends on experience and lacks scientificity is solved, and the accuracy and reliability of clock tree design are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit logic synthesis parameter optimization, and in particular to a circuit logic synthesis parameter optimization method, device, equipment and medium. Background Art

[0002] The design of integrated circuits is divided into two stages: front-end and back-end. Front-end design focuses on the realization of logical functions. Through RTL (Register Transfer Level) code writing and logic synthesis, the design ideas are converted into circuit netlists. Back-end design, also known as physical design, is responsible for further converting this circuit netlist into a specific physical layout, including component placement, wiring planning, and clock tree construction. In the physical design stage, the layout and wiring of the clock tree become key factors affecting chip performance. The clock signal must reach each sequential element accurately and quickly to ensure the correct transmission and processing of data. However, with the increase in chip scale and clock frequency, the optimization of the clock tree faces increasing challenges. Clock uncertainty and clock transition time are two critical parameters in clock tree optimization. Clock uncertainty describes the time difference of the clock signal reaching each sequential element due to factors such as process changes and wiring length differences. The clock transition time reflects the conversion speed of the clock signal when it propagates in the clock tree. In the traditional design process, the setting of these two parameters often depends on the experience and intuition of engineers. In the synthesis stage, in order to leave enough timing margin for subsequent layout and routing, engineers usually set these parameters relatively large. However, this empirical setting method may lead to unnecessary area waste or degradation of timing performance. In addition, when generating circuit structures, logic synthesis tools will optimize timing and area based on given constraint files (such as SDC files). However, there is often a conflict between timing and area optimization: pursuing better timing performance may increase circuit area, while over-emphasizing area optimization may sacrifice timing performance. Therefore, how to reasonably set these parameters in the constraint file to achieve joint optimization of timing and area has become an important issue in integrated circuit design. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a method, apparatus, device and medium for optimizing logic synthesis parameters of a circuit that overcomes the above problems or at least partially solves the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a method for optimizing logic synthesis parameters of a circuit, the method comprising:

[0005] Obtaining an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0006] Determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model;

[0007] Determine a timing score and an area score based on the optimized clock uncertainty parameter and the optimized clock transition time parameter

[0008] In a case where the timing score and the area score meet a preset score condition, a target clock uncertainty parameter and a target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter.

[0009] Optionally, the method further comprises:

[0010] Determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group includes a clock uncertainty parameter and a clock conversion time parameter;

[0011] The step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model comprises:

[0012] According to the at least one initial parameter group and the preset optimization model, determining an optimization parameter group corresponding to the at least one initial parameter group one by one;

[0013] The step of determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter comprises:

[0014] Determining a corresponding timing score and an area score for each of the optimization parameter groups;

[0015] The step of determining a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter when the timing score and the area score meet a preset scoring condition includes:

[0016] When the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determining a target parameter group according to the optimization parameter group;

[0017] The target clock uncertainty parameter and the target clock conversion time parameter are determined according to the target parameter group.

[0018] Optionally, the method further comprises:

[0019] When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, return to the step of determining the optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model.

[0020] Optionally, when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, returning to the step of determining an optimization parameter group corresponding one-to-one to the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model comprises:

[0021] When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, determining a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding to one of them;

[0022] Determining a second candidate parameter group according to the at least one optimization parameter group;

[0023] Return to the step of determining an optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model.

[0024] Optionally, determining, according to the at least one initial parameter group and a preset optimization model, an optimization parameter group corresponding one-to-one to the at least one initial parameter group includes:

[0025] Determine an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and a preset optimization model;

[0026] The step of returning the step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model comprises:

[0027] Return to the step of determining an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0028] Optionally, when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determining a target parameter group according to the optimization parameter group includes:

[0029] When the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group and the second candidate parameter group.

[0030] Optionally, the method further comprises:

[0031] When the timing score and the area score do not meet the preset score conditions, return to the step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model.

[0032] On the other hand, an embodiment of the present invention further discloses a circuit logic synthesis parameter optimization device, the device comprising:

[0033] An initial parameter acquisition module, used to acquire an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0034] An optimization parameter determination module, used to determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model;

[0035] A comprehensive score determination module, used to determine the timing score and the area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter

[0036] The target parameter determination module is used to determine a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter when the timing score and the area score meet a preset scoring condition.

[0037] Optionally, the device further comprises:

[0038] An initial parameter group acquisition submodule, used to determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group includes a clock uncertainty parameter and a clock conversion time parameter;

[0039] The module is determined according to the initial clock uncertainty parameter and the optimization parameter, comprising:

[0040] An optimization parameter group determination submodule, configured to determine an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and a preset optimization model;

[0041] The comprehensive score determination module comprises:

[0042] A comprehensive score group determination submodule, used to determine the corresponding timing score and area score for each of the optimization parameter groups;

[0043] The target parameter determination module comprises:

[0044] A target parameter group determination submodule, configured to determine a target parameter group according to the optimization parameter group when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold;

[0045] Finally, the target parameter determination submodule is used to determine the target clock uncertainty parameter and the target clock conversion time parameter according to the target parameter group.

[0046] Optionally, the device further comprises:

[0047] The repeated iteration submodule is used to return to the step of determining the optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold.

[0048] Optionally, the repeated iteration submodule includes:

[0049] A first candidate determination unit is configured to determine a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding to each of the optimization parameter groups when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold;

[0050] A second candidate determination unit, configured to determine a second candidate parameter group according to the at least one optimization parameter group;

[0051] The first optimization iteration unit is used to return to the step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model.

[0052] Optionally, the optimization parameter group determination submodule includes:

[0053] A first optimization unit, configured to determine, according to the at least one first candidate parameter group, the second candidate group and a preset optimization model, an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group;

[0054] The first optimization iteration unit comprises:

[0055] The second optimization iteration subunit is used to return to the step of determining an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group based on the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0056] Optionally, the target parameter group determination submodule includes:

[0057] The final target parameter group determination unit is used to determine the target parameter group according to the optimization parameter group and the second candidate parameter group when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold.

[0058] Optionally, the method further includes:

[0059] When the timing score and the area score do not meet the preset scoring conditions, the iteration submodule returns to the step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter based on the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model.

[0060] Accordingly, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the various steps of the embodiment of the logic synthesis parameter optimization method of the above-mentioned circuit.

[0061] Accordingly, an embodiment of the present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various steps of the embodiment of the logic synthesis parameter optimization method of the above circuit are implemented.

[0062] The embodiment of the present invention includes the following advantages: based on obtaining the initial clock uncertainty parameter and the initial clock conversion time parameter, by combining with the preset optimization model, the embodiment of the present invention can accurately calculate the optimized clock uncertainty parameter and the clock conversion time parameter. The problem that the parameter setting depends on experience and lacks scientificity is solved, and the accuracy and reliability of the clock tree design are improved. Based on the optimized clock uncertainty parameter and the clock conversion time parameter, the timing score and the area score are further determined. The two scores reflect the performance of the clock tree in terms of timing performance and area efficiency, respectively. By comprehensively considering the timing and area, the area waste can be minimized while ensuring the timing performance, and the dual optimization of timing and area is achieved. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for the subsequent clock tree layout and routing, ensuring the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, providing strong support for the manufacture of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 It is a flow chart of steps of an embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention;

[0064] Figure 2 is a flow chart of steps of another embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention;

[0065] Figure 3 It is a flow chart of an embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention;

[0066] Figure 4 It is a structural block diagram of an embodiment of a circuit logic synthesis parameter optimization method device of the present invention. DETAILED DESCRIPTION

[0067] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] In integrated circuit design, the design of the clock tree is a crucial link. Among them, the clock uncertainty parameter and the clock conversion time parameter are two key concepts that have a direct impact on the performance of the clock tree.

[0069] The clock uncertainty parameter is used to describe the impact of the layout and routing of the clock tree on the arrival time of the clock signal. In the clock tree, due to differences in layout and routing, the time when the clock signal arrives at each register or trigger may be different. This time difference is called clock uncertainty. The clock uncertainty parameter is an important indicator to measure this time difference, which is crucial for the timing analysis and optimization of the clock tree.

[0070] The Clock Transition Time Parameter is used to describe the conversion speed of the clock signal in the clock tree. When the clock signal jumps from a low level to a high level or from a high level to a low level, it takes a certain amount of time to complete the conversion process. This time is called the clock transition time. The clock transition time parameter is an important indicator to measure the conversion speed of the clock signal, which has a direct impact on the performance of the clock tree. A faster clock transition time can increase the operating frequency of the clock tree, but it may also bring greater power consumption and noise.

[0071] One of the core concepts of the embodiments of the present invention is to obtain and optimize clock uncertainty parameters and clock conversion time parameters by combining scientific methods with preset optimization models, and to quantify the timing and area of ​​the clock tree into evaluable indicators by introducing timing scores and area scores, thereby providing a clear direction for subsequent optimization.

[0072] Reference Figure 1 , shows a flow chart of steps of an embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention, which may specifically include the following steps:

[0073] Step 101, obtaining an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0074] The method for obtaining the initial clock uncertainty parameters and the initial clock conversion time parameters can be calculated based on the physical parameters of the circuit design, or generated using EDA (Electronic Design Automation) tools and estimated based on experience, etc., and the embodiments of the present invention are not limited to this.

[0075] Step 102, determining an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model;

[0076] After the initial parameters are obtained, the preset optimization model is used to calculate the optimized parameter values ​​in combination with the initial clock uncertainty parameters and the clock conversion time parameters.

[0077] Step 103: Determine a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter.

[0078] The timing score indicates whether the circuit can work stably within the specified clock cycle based on the optimized clock parameters, that is, whether it meets the timing requirements. A high timing score means that the circuit has good timing performance. The area score indicates the circuit area or resource consumption required to achieve these clock parameters.

[0079] Step 104, when the timing score and the area score meet the preset score conditions, determine the target clock uncertainty parameter and the target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter.

[0080] If both the timing score and the area score meet the preset score conditions, the current optimized clock uncertainty parameter and the optimized clock conversion time parameter are determined as the final target parameters.

[0081] In one embodiment, the method further comprises:

[0082] When the timing score and the area score do not meet the preset score conditions, return to the step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model.

[0083] If the scoring condition is not met, it means that the current parameter combination is not optimal, and it is necessary to return to step 102 and perform the optimization process again until a parameter combination that meets the condition is found.

[0084] In one embodiment, a termination condition can be set for the iteration of the method to prevent endless iteration of the algorithm due to abnormal reasons; the condition for terminating the iteration can be that the number of iterations reaches a threshold; for example, the iteration number threshold can be set to 8 times, that is, when the number of iterations is the 8th time, the iteration is terminated.

[0085] Based on obtaining the initial clock uncertainty parameter and the initial clock conversion time parameter, by combining with the preset optimization model, the embodiment of the present invention can accurately calculate the optimized clock uncertainty parameter and clock conversion time parameter. This step directly solves the problem that the parameter setting in the background technology relies on experience and lacks scientificity, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and clock conversion time parameter, the timing score and area score are further determined. These two scores reflect the performance of the clock tree in terms of timing performance and area efficiency, respectively. By comprehensively considering the timing and area, it is possible to minimize area waste while ensuring the timing performance, and achieve dual optimization of timing and area. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for the subsequent clock tree layout and routing, ensuring the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, providing strong support for the manufacture of integrated circuits.

[0086] Reference Figure 2 , shows a flowchart of another embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention, which may specifically include the following steps:

[0087] In an embodiment of the present invention, the preset optimization model may be a particle swarm optimization model. The following are corresponding steps and explanations of an embodiment of a method for optimizing logic synthesis parameters of a circuit in combination with a particle swarm optimization algorithm.

[0088] Particle Swarm Optimization (PSO) is an optimization algorithm based on swarm intelligence, which solves optimization problems by simulating the behavior of biological groups such as bird flocks or fish schools.

[0089] The PSO algorithm simulates the behavior of flocks of birds or schools of fish foraging in nature. In this model, each solution is considered a "particle" in the search space, representing a potential solution to the problem. Each particle has two key properties: position and velocity. The position represents the current coordinates of the particle in the solution space, while the velocity determines the direction and speed of the particle's movement.

[0090] Step 201, obtaining an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0091] The method for obtaining the initial clock uncertainty parameters and the initial clock conversion time parameters can be calculated based on the physical parameters of the circuit design, or generated using EDA (Electronic Design Automation) tools and estimated based on experience, etc., and the embodiments of the present invention are not limited to this.

[0092] Combined with the particle swarm optimization algorithm, the initial parameters are generated. For example, the clock transition time parameter (transition) can be initialized to x i1 , the range is (0.8, 1.2); initialize the clock uncertainty parameter (uncertainty) to x i2 , the range is (0.3, 1.7).

[0093] Step 202, determining at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group includes a clock uncertainty parameter and a clock conversion time parameter;

[0094] Exemplarily, a group of particles are randomly generated, each particle representing a combination of a set of initial clock uncertainty parameters and the initial clock conversion time parameters. Here, the number of particles is tentatively set to 5. For each particle i, its position is randomly initialized. i =(x i1 ,x i2 )

[0095] In one example, the velocity V of each particle can also be initialized i =(v i1 ,v i2 ) to control the moving speed of particles in the search space. Correspondingly, x i1 Smaller range, v i1 The range of is set to (-0.1, 0.1); x i2 Smaller range, v i2 The range of is set to (-0.2, 0.2).

[0096] Step 203, determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and a preset optimization model;

[0097] Optimize the initial parameter group based on the initial position and velocity of the particles;

[0098] Step 204, determining a corresponding timing score and area score for each of the optimization parameter groups;

[0099] For each optimization parameter group, their timing score and area score need to be determined in order to better evaluate the performance of the generated parameters; the method of generating the timing score and area score can be generated with the help of the DC (Design Compiler, logic synthesis tool) tool; DC (Design Compiler) is an advanced digital integrated circuit logic synthesis tool developed by Synopsys, which can convert high-level hardware description language (HDL) code (such as Verilog, VHDL, etc.) into an optimized gate-level netlist.

[0100] Step 205, when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determine a target parameter group according to the optimization parameter group;

[0101] For example, the importance of the timing score and the area score can be set according to business needs. For this embodiment, it is most important that the timing score meets the threshold. If the timing meets the requirements, the logic synthesis area is A. Here, A=450000, and the fitness is defined as If the timing does not meet the requirements, the fitness is set to the minimum value, f = 0.01. The smaller the area, the greater the fitness and the better the logic synthesis result.

[0102] In one embodiment, the method further comprises:

[0103] When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, return to the step of determining the optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model.

[0104] When the score does not meet the threshold, it means that the optimization of the model has not achieved the predetermined goal, and it needs to be iterated again. This process ensures the quality of the design and enhances the design flexibility.

[0105] In one embodiment, the step of "when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, returning to the step of determining an optimization parameter group corresponding one-to-one to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model" may include the following sub-steps:

[0106] Sub-step S11, when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, determining a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding to one of them;

[0107] In the particle swarm algorithm, the selection of the individual optimal and group optimal particles is the key point of the algorithm;

[0108] In one example, when determining the individual best, it is necessary to compare the scoring results of the parameters generated this time with the scoring results of the parameters generated last time, and select the best one as the new particle individual best to be brought into the next iteration; illustratively, for each particle i, its current fitness is compared with the individual historical best fitness. If the current fitness is better, the individual best position Pbest is updated i =X i The optimal position of an individual for the initial solution is itself.

[0109] Sub-step S12, determining a second candidate parameter group according to the at least one optimization parameter group;

[0110] After determining the optimal position of the individual, it is necessary to further determine the optimal position of the group;

[0111] In one example, after each individual position is selected as optimal, it is compared with the current group optimal position. If the current individual position is better than the current group optimal position, the current individual position replaces the group optimal position to generate a new group optimal position.

[0112] Sub-step S13, returning to the step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model.

[0113] When the score does not meet the threshold, it means that the optimization of the model has not achieved the predetermined goal, and re-iteration is required. This process ensures the quality of the design and enhances the design flexibility.

[0114] In one embodiment, step 203 includes the following sub-steps:

[0115] Sub-step S21, determining an optimization parameter group corresponding to the at least one first candidate parameter group in a one-to-one manner according to the at least one first candidate parameter group, the second candidate group and a preset optimization model;

[0116] For example, the velocity of the particle may be updated according to the following formula:

[0117] v ij =w t *v ij (t)+c1*r1*(Pbest ij -x ij (t))+c2*r2*(Gbest j -x ij (t))

[0118] The particle position can be updated according to the following formula combined with the updated velocity:

[0119] x ij (t+1)=x ij (t)+v ij (t+1)

[0120] The learning factor is: c1 = c2 = 2. Specifically, the learning factor is in the range of [0, 4]. The values ​​of c1 and c2 can be adjusted appropriately according to business needs. The inertia weight is set to: w = 0.9. max =0.9w min =0.3. r1 and r2 are random numbers in [0, 1]. It should be noted that the values ​​of the learning factor, r1, r2, and inertia weight can be freely set in other ways and scenarios, and the embodiment of the present invention does not limit this.

[0121] For the updated position x i1 (t+1), if it is less than 0.8, it is set to 0.81, if it is greater than 1.2, it is set to 1.2. For the updated position x i2 (t+1), if it is less than 0.4, set it to 0.41, if it is greater than 1.7, set it to 1.7. If the position exceeds the range because the speed is too high, the speed can be reversed and its absolute value can be reduced according to the direction of the excess. For example, with x i1 For example: If x i1 (t+1)>1.2, then v i1 (t+1)=-|v i1 (t+1)|*α, where α is a coefficient less than 1 and can be adjusted according to business needs; if x i1 (t+1)<0.8, then v i1 (t+1)=-|v i1 (t+1)|*α;

[0122] The sub-step S13 includes the following sub-steps:

[0123] Sub-step S131, returning to the step of determining an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0124] In one embodiment, step 205 includes the following sub-steps:

[0125] Sub-step S31, when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determine a target parameter group according to the optimization parameter group and the second candidate parameter group.

[0126] Exemplarily, when the fitness score meets the threshold, the fitness scores of the current optimization parameter group and the second candidate parameter group are compared, and the one with the highest fitness score is taken as the target parameter group;

[0127] Step 206: Determine the target clock uncertainty parameter and the target clock conversion time parameter according to the target parameter group.

[0128] In one embodiment, a termination condition can be set for the iteration of the method to prevent endless iteration of the algorithm due to abnormal reasons; the condition for terminating the iteration can be that the number of iterations reaches a threshold or the fitness score reaches a threshold; for example, the iteration number threshold can be set to 8 times and the score threshold can be set to 0.001, that is, when the number of iterations is the 8th time or when the fitness score is less than 0.001, the iteration is terminated.

[0129] Reference Figure 3 , showing a schematic flow chart of an embodiment of a method for optimizing logic synthesis parameters of a circuit of the present invention;

[0130] First, the parameter particles are initialized, and then the DC tool is used to perform parallel logic synthesis to obtain the timing score and area score. Then, the fitness of the group of parameters is evaluated based on the obtained timing score and area score, and the position, speed and number of iterations of the corresponding parameter particles are updated according to the evaluation results; then check whether the conditions for terminating the iteration are met. If so, stop the iteration and output the optimal solution. If not, continue the iteration.

[0131] Based on obtaining the initial clock uncertainty parameter and the initial clock conversion time parameter, by combining with the preset optimization model, the embodiment of the present invention can accurately calculate the optimized clock uncertainty parameter and clock conversion time parameter. This step directly solves the problem that the parameter setting in the background technology relies on experience and lacks scientificity, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and clock conversion time parameter, the timing score and area score are further determined. These two scores reflect the performance of the clock tree in terms of timing performance and area efficiency, respectively. By comprehensively considering the timing and area, it is possible to minimize area waste while ensuring the timing performance, and achieve dual optimization of timing and area. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for the subsequent clock tree layout and routing, ensuring the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, providing strong support for the manufacture of integrated circuits.

[0132] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0133] Reference Figure 3 , shows a structural block diagram of an embodiment of a circuit logic synthesis parameter optimization device of the present invention, which may specifically include the following modules:

[0134] An initial parameter acquisition module 301 is used to acquire an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0135] An optimization parameter determination module 302, configured to determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model;

[0136] A comprehensive score determination module 303 is used to determine a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter.

[0137] The target parameter determination module 304 is used to determine a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter when the timing score and the area score meet a preset scoring condition.

[0138] In one embodiment, the device further comprises:

[0139] An initial parameter group acquisition submodule, used to determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group includes a clock uncertainty parameter and a clock conversion time parameter;

[0140] The module is determined according to the initial clock uncertainty parameter and the optimization parameter, comprising:

[0141] An optimization parameter group determination submodule, configured to determine an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and a preset optimization model;

[0142] The comprehensive score determination module comprises:

[0143] A comprehensive score group determination submodule, used to determine the corresponding timing score and area score for each of the optimization parameter groups;

[0144] The target parameter determination module comprises:

[0145] A target parameter group determination submodule, configured to determine a target parameter group according to the optimization parameter group when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold;

[0146] Finally, the target parameter determination submodule is used to determine the target clock uncertainty parameter and the target clock conversion time parameter according to the target parameter group.

[0147] In one embodiment, the device further comprises:

[0148] The repeated iteration submodule is used to return to the step of determining the optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold.

[0149] In one embodiment, the repeating iterative submodule includes:

[0150] A first candidate determination unit is configured to determine a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding to each of the optimization parameter groups when the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold;

[0151] A second candidate determination unit, configured to determine a second candidate parameter group according to the at least one optimization parameter group;

[0152] The first optimization iteration unit is used to return to the step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model.

[0153] In one embodiment, the optimization parameter group determination submodule includes:

[0154] A first optimization unit, configured to determine, according to the at least one first candidate parameter group, the second candidate group and a preset optimization model, an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group;

[0155] The first optimization iteration unit comprises:

[0156] The second optimization iteration subunit is used to return to the step of determining an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group based on the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0157] In one embodiment, the target parameter group determination submodule includes:

[0158] The final target parameter group determination unit is used to determine the target parameter group according to the optimization parameter group and the second candidate parameter group when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold.

[0159] In one embodiment, the method further comprises:

[0160] When the timing score and the area score do not meet the preset scoring conditions, the iteration submodule returns to the step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter based on the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model.

[0161] Based on obtaining the initial clock uncertainty parameter and the initial clock conversion time parameter, by combining with the preset optimization model, the embodiment of the present invention can accurately calculate the optimized clock uncertainty parameter and clock conversion time parameter. This step directly solves the problem that the parameter setting in the background technology relies on experience and lacks scientificity, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and clock conversion time parameter, the timing score and area score are further determined. These two scores reflect the performance of the clock tree in terms of timing performance and area efficiency, respectively. By comprehensively considering the timing and area, it is possible to minimize area waste while ensuring the timing performance, and achieve dual optimization of timing and area. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for the subsequent clock tree layout and routing, ensuring the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, providing strong support for the manufacture of integrated circuits.

[0162] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0163] An embodiment of the present invention further provides an electronic device, including:

[0164] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the embodiment of the logic synthesis parameter optimization method of the above-mentioned circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0165] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the embodiment of the logic synthesis parameter optimization method of the above-mentioned circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0166] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0167] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0168] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0169] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0171] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0172] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0173] The above is a detailed introduction to the logic synthesis parameter optimization method, device, equipment and medium of a circuit provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for optimizing logic synthesis parameters of a circuit, characterized in that: The method comprises: Obtaining an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree; Determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model; Determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock transition time parameter; In a case where the timing score and the area score meet a preset score condition, a target clock uncertainty parameter and a target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter.

2. The method according to claim 1, characterized in that The method further comprises: Determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group includes a clock uncertainty parameter and a clock conversion time parameter; The step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model comprises: According to the at least one initial parameter group and the preset optimization model, determining an optimization parameter group corresponding to the at least one initial parameter group one by one; The step of determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter comprises: Determining a corresponding timing score and an area score for each of the optimization parameter groups; The step of determining a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter when the timing score and the area score meet a preset scoring condition includes: When the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determining a target parameter group according to the optimization parameter group; The target clock uncertainty parameter and the target clock conversion time parameter are determined according to the target parameter group.

3. The method according to claim 2, characterized in that The method further comprises: When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, return to the step of determining the optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model.

4. The method according to claim 3, characterized in that When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, returning to the step of determining an optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model, comprises: When the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the corresponding area score is less than a preset area threshold, determining a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding to one of them; Determining a second candidate parameter group according to the at least one optimization parameter group; Return to the step of determining an optimization parameter group corresponding one-to-one to the at least one initial parameter group based on the at least one initial parameter group and the preset optimization model.

5. The method according to claim 4, characterized in that The step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model includes: Determine an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and a preset optimization model; The step of returning the step of determining an optimization parameter group corresponding to the at least one initial parameter group in a one-to-one manner according to the at least one initial parameter group and the preset optimization model comprises: Return to the step of determining an optimization parameter group corresponding one-to-one to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

6. The method according to claim 5, characterized in that When the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, determining a target parameter group according to the optimization parameter group includes: When the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the corresponding area score is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group and the second candidate parameter group.

7. The method according to claim 1, characterized in that The method further comprises: When the timing score and the area score do not meet the preset score conditions, return to the step of determining the optimized clock uncertainty parameter and the optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model.

8. A circuit logic synthesis parameter optimization device, characterized in that: The device comprises: An initial parameter acquisition module, used to acquire an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree; An optimization parameter determination module, used to determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model; A comprehensive score determination module, used to determine the timing score and the area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter The target parameter determination module is used to determine a target clock uncertainty parameter and a target clock conversion time parameter according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter when the timing score and the area score meet a preset scoring condition.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the method for optimizing the logic synthesis parameters of the circuit according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for optimizing logic synthesis parameters of a circuit as claimed in any one of claims 1 to 7 are implemented.

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