MOS (Metal Oxide Semiconductor) and MOM (Metal Oxide Semiconductor) capacitor visual Pcell layout generation method

Abstract

The invention discloses an MOS and MOM capacitor visual Pcell layout generation method, and relates to the technical field of integrated circuits. According to the method, a simulation circuit is constructed to carry out simulation for multiple times, capacitance value changes of the MOS tube under different voltages are recorded, a detailed capacitance value data table is generated, Pcell parameters associated with geometric parameters are formed and integrated into a layout design tool, rapid calculation and visualization in a layout are achieved, then the calculation range of POLY density is defined, calculation is carried out in real time, and the calculation efficiency is improved. It is ensured that the MOM capacitor meets the technological requirements, and the design of the MOM capacitor is optimized by selecting the optimal metal layer combination and adjusting the metal area; and integrating calculation results of the MOS tube capacitor and the MOM capacitor into the Pcell, calling parameters of the Pcell, generating a corresponding capacitor layout, and performing design rule check and circuit layout comparison verification to ensure that the layout meets process requirements.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a method for generating a visualized Pcell layout of MOS and MOM capacitors. Background Art

[0002] In the field of chip design, MOS tubes are often used as filter capacitors, but this design has obvious defects. When the source and drain of the MOS tube are connected, its capacitance changes with Vgs. This change cannot be directly reflected in the layout RC extraction, resulting in only the parasitic capacitance of poly, diffusion and metal layers being extracted, and most of the capacitance needs to be calculated within the frequency bandwidth through circuit design. This makes it difficult to intuitively evaluate the capacitance of the MOS tube in the pre-simulation stage, which is not conducive to the layout area evaluation. As the frequency of IP design increases, the filter capacitor needs a larger capacitance, resulting in an increase in the layout area. In order to save area, MOM capacitors are often superimposed on the MOS tube capacitors, but the change in the pressure difference of the MOM capacitor will change the metal trace spacing, affecting PV verification, and it is easy to cause connection short circuits or DRC errors due to changes in the position of the positive and negative plates when calling, and the layout needs to be redrawn. In addition, the production of MOM capacitors may increase the voltage recognition layer, which will increase the voltage when connecting other nets, causing subtle DRC errors. And with the continuous reduction of process nodes, the flatness of the layout is becoming more and more important to the yield of the chip, which requires strict control of the density of each layer during layout design. When filter capacitors are used on a large scale, the density of POLY can easily exceed the required range. This requires that this issue be considered during layout design to avoid insufficient layout area in the later stage, resulting in redrawing of the layout and increased workload. Summary of the invention

[0003] The object of the present invention is to provide a method for generating a visualized Pcell layout of MOS and MOM capacitors, efficiently generate a visible capacitance Pcell layout of MOS tube capacitors and MOM capacitors based on a FinFET process, and improve the efficiency and accuracy of layout design.

[0004] The purpose of the present invention can be achieved through the following technical solutions: The present application provides a method for generating a visualized Pcell layout of MOS and MOM capacitors, comprising the following steps: The capacitance change of 1.8V MOS tube under different Vgs voltages is recorded through simulation circuit, and a curve is drawn to analyze the linear relationship between finger, length and capacitance. According to the simulation results, the capacitance change slope of the MOS tube under different voltages is calculated to generate the reference capacitance C1, the capacitance C2 and C under different lengths and fingers are calculated, and the capacitance data table of the MOS tube is generated; According to the capacitance data table of MOS tube, it is associated with geometric parameters to form Pcell parameters, and then quickly calculate and visualize them in the layout; According to the simulation result data, select Metal4 and above metal levels, calculate the MOM capacitor capacitance per unit area based on the process conditions, and calculate the overall metal capacitance based on the designed metal area. According to the MOS tube capacitance and the overall metal capacitance, the POLY density calculation range is defined, the POLYdensity is calculated in real time, and the POLY density ratio is reduced by adjusting the layout parameters to determine whether the layout meets the CMP requirements.

[0005] Furthermore, the capacitance change of the 1.8V MOS tube at different Vgs voltages is recorded through the simulation circuit, and a curve graph is drawn to analyze the linear relationship between finger, length and capacitance, including: According to the parameters of the 1.8V MOS tube, a MOS tube circuit model is constructed in the simulation circuit design software, and different Vgs voltage values ​​are set. Multiple simulations are performed through the circuit simulation software to obtain the capacitance value data of the MOS tube under different Vgs voltages; The acquired capacitance value data is sorted out, and a curve graph of capacitance value and Vgs voltage is drawn through data analysis software. According to the drawn curve graph, the linear relationship between the finger and Length parameters of the MOS tube and the capacitance value is analyzed to obtain the influence of finger and Length on the capacitance value. For the capacitance value data under different Vgs voltages, the trend of capacitance value changing with Vgs voltage is judged by curve fitting algorithm, and the mathematical model between capacitance value and Vgs voltage is obtained. Then, the mapping relationship model between capacitance value and Vgs voltage, finger, and Length parameters is trained by machine learning algorithm to predict the capacitance value of MOS tube under any parameter combination. According to the established mathematical model and machine learning model, the finger and length parameter design of the MOS tube are optimized to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

[0006] Furthermore, a capacitance data table of the MOS tube is generated, specifically including: According to the simulation result data, extract the voltage parameters, tube parameters, tube type and other information, establish a multi-dimensional array to store the simulation capacitance data under different conditions, traverse the voltage and tube parameters of different tube types, call the capacitance calculation formula, obtain the capacitance under the corresponding conditions, and update it to the corresponding multi-dimensional array; From the multidimensional array, select the MOS tube data of the same size, perform linear fitting on the capacitance data under different voltages, and obtain the slope of the capacitance change with voltage under the corresponding size. Then select the reference Length and finger as the initial value, and according to the capacitance change slope under the size, extrapolate and calculate the capacitance under zero voltage as the reference capacitance C1; Among them, starting from the reference Length, applying the Length slope formula, traversing different Lengths, calculating the capacitance C2 under the corresponding conditions, and updating the Length-capacitance mapping table; starting from the reference finger, traversing different values ​​of finger, calling the mapping formula of index and capacitance, calculating the capacitance C under different finger values, and continuously updating the finger-capacitance mapping table; The length-capacitance mapping table and the finger-capacitance mapping table are combined to generate a capacitance data table covering different lengths, fingers, and voltage conditions.

[0007] Furthermore, according to the capacitance data table of the MOS tube, the Pcell parameters are associated with the geometric parameters, including: Obtain the capacitance data table of the MOS tube, extract the corresponding relationship data between the capacitance and the geometric parameters, establish the Pcell parameterized model of the MOS tube capacitor according to the extracted corresponding relationship data between the capacitance and the geometric parameters, and associate and map the capacitance and the geometric parameters; in the Pcell parameterized model, set the geometric parameters as input variables and the capacitance as output variables, establish a parameterized calculation formula, integrate the Pcell parameterized model into the layout design tool, perform real-time association calculation between the geometric parameters and the capacitance change slope, and perform visual adjustment of the geometric parameters according to the Pcell parameterized model. In the layout design process, the MOS tube capacitance is calculated by calling the Pcell parameterized model. When the layout design needs to adjust the MOS tube capacitance, the capacitance of the adjusted MOS tube capacitance is calculated according to the geometric parameters of the adjusted MOS tube capacitance, and the visualization of the MOS tube capacitance is updated in real time in the layout.

[0008] Furthermore, after associating with geometric parameters to form Pcell parameters, it also includes: obtaining the capacitance of MOM capacitors at different metal levels, analyzing the relationship between the capacitance of the MOM capacitor and the metal level and area, establishing a Pcell model of the MOM capacitor, the Pcell model includes a mapping relationship between the metal level, area and capacitance, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor to calculate the capacitance of the corresponding MOM capacitor.

[0009] Furthermore, the overall metal capacitance is calculated according to the designed metal area, specifically including: obtaining Metal4 and above metal levels, extracting the corresponding metal capacitance, obtaining the capacitance data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance, calculating the capacitance per unit area, and obtaining the corresponding capacitance per unit area according to the metal area designed in the Pcell model by table lookup or interpolation, multiplying the metal area by the capacitance per unit area to obtain the overall metal capacitance, and then using the overall metal capacitance as a parameter of the MOM capacitor to calculate the overall capacitance to obtain a calculation result.

[0010] Furthermore, according to the calculation results, it also includes: analyzing the capacitance characteristics of different metal levels and selecting the optimal metal level combination; adjusting the metal area according to the design requirements, using the calculation method of the MOS tube to obtain the corresponding capacitance value, obtaining the optimized metal level, area and corresponding capacitance value, and using the optimized value as the input parameter of the Pcell model of the MOM capacitor to calculate the metal capacitance and intuitively display it in the layout.

[0011] Further, a POLY density calculation range is defined, POLY density is calculated in real time, and the POLY density ratio is reduced by adjusting layout parameters to determine whether the layout CMP requirements are met, specifically including: obtaining the MOS tube capacitance and metal capacitance, determining the POLY density calculation range to be a BOX range with the lower left corner of the POLY as the starting point and the upper right corner as the end point, calculating the area of ​​the POLY layer within the defined BOX range, and at the same time, calculating the total area of ​​the BOX range; calculating the POLY density ratio in real time according to the ratio of the POLY area within the calculation range to the total BOX area; then obtaining the POLY Dn requirement threshold of the process to determine whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, the MOS tube layout parameters are adjusted to reduce the POLY density while keeping the MOS capacitance unchanged; repeatedly calculating the POLY density ratio and determining whether the POLY Dn meets the requirement threshold until the POLY density meets the CMP requirement threshold; then determining whether the layout area is sufficient according to the adjusted layout parameters; when the layout area is insufficient, continuing to adjust the layout parameters until the layout area meets the requirements, and outputting the final layout parameters and layout area.

[0012] The calculation results of MOS tube capacitance and MOM capacitance are integrated into a Pcell to form a complete capacitance module. In the layout design, by calling the Pcell parameters, the corresponding capacitance layout is quickly generated according to the design requirements, and the capacitance module is automatically laid out and wired. The generated Pcell layout is checked for design rules and compared with the circuit layout to ensure that the layout meets the process requirements.

[0013] Furthermore, the calculation results of the MOS tube capacitor and the MOM capacitor are used to form a complete capacitor module. According to the design requirements, the parameter specifications of the capacitor module are determined and used as the input parameters of the Pcell. By calling the corresponding capacitor Pcell, the design parameters are passed in. The Pcell automatically generates a capacitor layout that meets the requirements according to the preset layout and routing algorithm and design rules. Perform a design rule check on the generated capacitor layout to check whether the layout meets the design specifications of the process. If the check fails, adjust the Pcell parameters to regenerate the layout until the DRC check passes. Then compare the generated capacitor layout with the schematic diagram for LVS circuit layout verification to check whether the electrical connections of the layout and the schematic diagram are consistent. If the layout comparison verification fails, return to modify the Pcell parameters and regenerate the layout until the layout comparison verification passes.

[0014] The beneficial effects of the present invention are: By building a simulation circuit and performing multiple simulations, the capacitance changes of MOS tubes under different voltages are recorded, a detailed capacitance data table is generated, and Pcell parameters associated with geometric parameters are formed. These Pcell parameters are then integrated into the layout design tool to achieve fast calculation and visualization in the layout, which not only improves the efficiency of layout design, but also ensures the accuracy of the design, so that the capacitance of MOS tubes can be intuitively evaluated in the pre-simulation stage, avoiding the problem of inaccurate layout area evaluation caused by capacitance changes; in addition, by optimizing the finger and Length parameter design of MOS tubes, the linear characteristics of capacitance are further improved to meet the circuit performance requirements; By defining the calculation range of POLY density and calculating POLY density in real time, it is ensured that it meets the process requirements. When POLY density exceeds the threshold, by adjusting the layout parameters of the MOS tube (such as nfinSpace), the POLY density ratio is reduced without changing the MOS capacitance, and whether it meets the layout CMP requirements is quickly determined. This effectively avoids the problem of redrawing due to insufficient layout area caused by excessive POLY density, reducing the workload. At the same time, by selecting the optimal metal layer combination and adjusting the metal area, the design of the MOM capacitor is optimized to ensure the flatness of the layout and the yield of the chip. The calculation results of the MOS tube capacitance and the MOM capacitance are then integrated into a Pcell to form a complete capacitor module. By calling the Pcell parameters, the corresponding capacitor layout is quickly generated, and the design rule check and circuit layout comparison verification are performed to ensure that the layout meets the process requirements and improve the reliability and performance of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A schematic diagram of a process for generating a visual Pcell layout of MOS and MOM capacitors provided in this application; Figure 2 A MOS and MOM capacitor visualization Pcell layout generation method provided in this application constructs a simulation circuit and sets different Vgs voltage values ​​for circuit simulation. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0018] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0019] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0020] See also Figure 1-Figure 2 This embodiment provides a method for generating a visualized Pcell layout of MOS and MOM capacitors, comprising the following steps: Among them, FinFET process is an advanced semiconductor manufacturing technology that significantly improves the performance and energy efficiency of transistors by adopting a three-dimensional fin structure and dual-gate design. This process not only enhances the control capability of the channel and reduces leakage current, but also improves the drive current and integration density, making the chip perform well in high-performance computing and low-power applications, while also having good scalability to meet the needs of future technological development; S1. Record the capacitance change of 1.8V MOS tube under different Vgs voltages through simulation circuit, draw a curve chart, and analyze the linear relationship between finger, length and capacitance; Specifically, the simulation circuit is constructed and different Vgs voltage values ​​are set to perform circuit simulation, the capacitance value change of the 1.8V MOS tube under different voltages is recorded, the simulation results are sorted out and a curve is drawn, and the linear relationship between the finger and length of the MOS tube and the capacitance value, as well as the capacitance change trend with voltage under different voltages are analyzed; Among them, Finger refers to the multiple parallel, elongated active regions between the source (Source) and the drain (Drain) in the FinFET, and Length refers to the channel length between the source (Source) and the drain (Drain) in the FinFET.

[0021] Furthermore, the capacitance change of the 1.8V MOS tube at different Vgs voltages is recorded through the simulation circuit, and a curve graph is drawn to analyze the linear relationship between finger, length and capacitance, including: S11. According to the parameters of the 1.8V MOS tube, a MOS tube circuit model is constructed in the simulation circuit design software, and different Vgs voltage values ​​are set. Multiple simulations are performed through the circuit simulation software to obtain the capacitance value data of the MOS tube under different Vgs voltages. S12, sorting the acquired capacitance value data, drawing a curve graph of capacitance value and Vgs voltage through data analysis software, analyzing the linear relationship between the finger and Length parameters of the MOS tube and the capacitance value according to the drawn curve graph, and obtaining the influence of finger and Length on the capacitance value; S13. For the capacitance value data under different Vgs voltages, the trend of the capacitance value changing with the Vgs voltage is determined by a curve fitting algorithm, and a mathematical model between the capacitance value and the Vgs voltage is obtained. Then, a machine learning algorithm, such as a support vector machine or a neural network, is used to train a mapping relationship model between the capacitance value and parameters such as the Vgs voltage, finger, and Length, so as to predict the capacitance value of the MOS tube under any parameter combination. S14. According to the established mathematical model and machine learning model, the finger and length parameter design of the MOS tube is optimized to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

[0022] Specifically, by constructing a simulation circuit and setting different Vgs voltage values ​​for multiple simulations, the capacitance value changes of the 1.8V MOS tube at different voltages are recorded, a detailed capacitance data table is generated, and Pcell parameters associated with geometric parameters are formed. These Pcell parameters are integrated into the layout design tool to achieve fast calculation and visualization in the layout, improving design efficiency and accuracy. At the same time, by analyzing the linear relationship between finger and length and capacitance value, as well as the trend of capacitance change with voltage, the finger and length parameter design of the MOS tube is optimized to ensure that the optimal capacitance value and linear characteristics are obtained while meeting the circuit performance requirements.

[0023] S2. According to the simulation results, the capacitance change slope of the MOS tube under different voltages is calculated to generate the reference capacitance C1, the capacitance C2 and C under different lengths and fingers are calculated, and the capacitance data table of the MOS tube is generated; Specifically, according to the simulation result data, the formula Scan the capacitance values ​​of different voltages, different tube parameters, and different tube types. According to the scan result data, calculate the capacitance change slope of the same size MOS tube under different voltages, convert it into a linear result to obtain the reference capacitance C1, and select the reference Length and finger. According to the slope of Length, calculate the capacitance C2 under different Lengths, and then calculate the capacitance C under different fingers to generate the capacitance data table of the MOS tube; Furthermore, a capacitance data table of the MOS tube is generated, specifically including: According to the simulation result data, extract the voltage parameters, tube parameters, tube type and other information, establish a multi-dimensional array to store the simulation capacitance data under different conditions, traverse the voltage and tube parameters of different tube types, call the capacitance calculation formula, obtain the capacitance under the corresponding conditions, and update it to the corresponding multi-dimensional array; From the multidimensional array, select the MOS tube data of the same size, perform linear fitting on the capacitance data under different voltages, and obtain the slope of the capacitance change with voltage under the corresponding size. Then select the reference Length and finger as the initial value, and according to the capacitance change slope under the size, extrapolate and calculate the capacitance under zero voltage as the reference capacitance C1; Among them, starting from the reference Length, applying the Length slope formula, traversing different Lengths, calculating the capacitance C2 under the corresponding conditions, and updating the Length-capacitance mapping table; starting from the reference finger, traversing different values ​​of finger, calling the mapping formula of index and capacitance, calculating the capacitance C under different finger values, and continuously updating the finger-capacitance mapping table; The length-capacitance mapping table and the finger-capacitance mapping table are combined to generate a capacitance data table covering different lengths, fingers, and voltage conditions.

[0024] For example, for a voltage range of 1V to 1.1V, the calculated capacitance slope is 20, and the capacitance at 1V is 275.2 fF. Therefore, the reference capacitance C1 can be expressed as: ; Assuming that the designed MOS tube length L is not equal to 0.15u, the capacitance C2 under different lengths can be calculated according to the change of the slope between 1644.7 and 1657.6; the formula is: , where VB is the capacitance difference of the MOS tube; calculate the capacitance C under different fingers, the formula is: ;in, 3.8378 and 3.8639 are the slopes obtained from the simulation results, and 72 is the benchmark finger of the simulation.

[0025] Among them, MOS tube capacitance is a capacitance formed by the gate, source and drain of MOS transistors. When the source and drain are connected together, a capacitance is formed between the gate and the source and drain; MOM capacitance is a capacitance formed by the metal layer and the dielectric layer between the metal layers, and is composed of multiple metal layers and dielectric layers between the metal layers; the size of the capacitance mainly depends on the area of ​​the metal layer, the number of layers and the dielectric constant of the dielectric layer.

[0026] Specifically, through detailed data analysis and mathematical modeling, a capacitance data table of MOS tubes was generated, which covers the capacitance changes under different voltages, different tube parameters and different tube types. This data table not only provides the benchmark capacitance C1, but also obtains the capacitance C2 and C under different Length and finger values ​​through slope calculation, thus providing an accurate reference for the design and optimization of MOS tube capacitors. In addition, through comparison and integration with MOM capacitors, the design of the capacitor module is further optimized, the efficiency and accuracy of the layout design are improved, and it is ensured that the capacitance value can be quickly and accurately evaluated and adjusted under different design conditions to meet the circuit performance requirements.

[0027] S3. According to the capacitance data table of the MOS tube, the Pcell parameters are associated with the geometric parameters to perform rapid calculation and visualization in the layout; Among them, Pcell (Parametric Cell) is a parameterized unit in semiconductor design, which is used to generate circuit elements with specific electrical characteristics and geometric shapes. Pcell technology allows designers to generate circuit elements of different sizes and characteristics by adjusting parameters, thereby improving design efficiency and flexibility.

[0028] Furthermore, according to the capacitance data table of the MOS tube, the Pcell parameters are associated with the geometric parameters, including: Obtain the capacitance data table of the MOS tube, extract the corresponding relationship data between the capacitance and the geometric parameters, establish the Pcell parameterized model of the MOS tube capacitor according to the extracted corresponding relationship data between the capacitance and the geometric parameters, and associate and map the capacitance with the geometric parameters; in the Pcell parameterized model, set the geometric parameters as input variables and the capacitance as output variables, establish a parameterized calculation formula, integrate the Pcell parameterized model into the layout design tool, realize the real-time association calculation of the geometric parameters and the capacitance change slope, and realize the visual adjustment of the geometric parameters according to the Pcell parameterized model. In the layout design process, the Pcell parameterized model is called to realize the rapid calculation of the MOS tube capacitance. When the layout design needs to adjust the MOS tube capacitance, the capacitance of the adjusted MOS tube capacitance is quickly calculated according to the geometric parameters of the adjusted MOS tube capacitance, and the visualization of the MOS tube capacitance is updated in real time in the layout.

[0029] Specifically, by forming Pcell parameters associated with geometric parameters, the rapid calculation and visualization of MOS tube capacitance in layout design is achieved. Specifically, using the capacitance data table of MOS tubes, a Pcell parameterized model is established to associate and map capacitance with geometric parameters (such as Length and finger). This model is integrated into the layout design tool, allowing designers to adjust geometric parameters in real time during the design process and immediately see the corresponding capacitance changes, thereby quickly optimizing the design and improving design efficiency and accuracy. This real-time calculation and visualization function greatly simplifies the layout design process and ensures the flexibility and reliability of the design.

[0030] S4. According to the simulation result data, select Metal4 and above metal levels, calculate the MOM capacitor value per unit area in combination with the process conditions, and calculate the overall metal capacitance according to the designed metal area; Specifically, according to the simulation result data, Metal4 and above metal levels are selected, and the capacitance per unit area is calculated by extracting the metal capacitance and combining it with the capacitance of the process MOM capacitor under the same conditions. In the Pcell model of the MOM capacitor, the overall metal capacitance is calculated according to the designed metal area, and the metal capacitance is quickly calculated. Among them, the same conditions of MOM capacitors refer to the capacitance calculated by the Pcell model of MOM capacitors under the same process conditions such as the same metal layer, dielectric material between metal layers, thickness of metal layers, spacing between metal layers, etc.

[0031] Furthermore, after associating with geometric parameters to form Pcell parameters, it also includes: obtaining the capacitance of MOM capacitors at different metal levels, analyzing the relationship between the capacitance of the MOM capacitor and the metal level and area, establishing a Pcell model of the MOM capacitor, the Pcell model includes a mapping relationship between the metal level, area and capacitance, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor to quickly calculate the capacitance of the corresponding MOM capacitor.

[0032] The rapid calculation and visualization of MOS tube capacitance and MOM capacitance realized by the above Pcell model greatly improves the efficiency of layout design and shortens the design cycle.

[0033] Furthermore, the overall metal capacitance is calculated according to the designed metal area, specifically including: obtaining Metal4 and above metal levels, extracting the corresponding metal capacitance, obtaining the capacitance data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance, calculating the capacitance per unit area, and obtaining the corresponding capacitance per unit area according to the metal area designed in the Pcell model by table lookup or interpolation. The metal area is multiplied by the capacitance per unit area to obtain the overall metal capacitance, and then the overall metal capacitance is used as a parameter of the MOM capacitor to quickly calculate the overall capacitance to obtain the calculation result.

[0034] Furthermore, according to the calculation results, it also includes: analyzing the capacitance characteristics of different metal levels (such as Metal4 and above) and selecting the optimal metal level combination; according to the design requirements, accurately adjusting the metal area, using the calculation method of the MOS tube to quickly obtain the corresponding capacitance, and obtaining the optimized metal level, area and corresponding capacitance value, and using the optimized value as the input parameter of the Pcell model of the MOM capacitor to quickly and accurately calculate the metal capacitance, and intuitively display it in the layout, ensuring that the capacitance calculation of the MOM capacitor is more accurate and the layout display is clearer, thereby further improving the visualization effect and design efficiency of the MOM capacitor.

[0035] Specifically, by selecting metal levels of Metal 4 and above, combined with the capacitance data under process conditions, the MOM capacitor capacitance per unit area is calculated, and the overall metal capacitance is quickly calculated in the Pcell model based on the designed metal area. This process not only achieves rapid calculation and visualization of MOM capacitors, but also optimizes the selection of metal levels and areas by analyzing the capacitance characteristics of different metal levels, ensuring more accurate calculation of MOM capacitor capacitance. Finally, the optimized parameters are used as input to the Pcell model, further improving the visualization effect and design efficiency of MOM capacitors and significantly shortening the layout design cycle.

[0036] S5. Define the POLY density calculation range according to the MOS tube capacitance and the overall metal capacitance, calculate the POLY density in real time, adjust the layout parameters to reduce the POLY density ratio, and determine whether it meets the layout CMP requirements; Specifically, the calculation range of POLY density is defined according to the capacitance of the MOS tube and the overall metal capacitance. The proportion of POLY is calculated within the BOX range with the lower left corner of POLY as the starting point and the upper right corner of POLY as the end point. The POLYDn requirements of the process are used to calculate the POLY density in real time during the layout design to ensure that it meets the process requirements. By adjusting the layout parameters of the MOS tube (such as nfinSpace), the POLY density ratio is reduced without changing the MOS capacitance, and it is quickly determined whether it meets the layout CMP requirements to avoid redrawing the layout due to insufficient layout area due to excessive POLY density and reduce workload. The POLY Dn requirement is <45%.

[0037] Among them, POLY density refers to the area ratio of the polysilicon (POLY) layer in a specific area, expressed as a percentage, and the calculation formula is: ; In semiconductor manufacturing, POLY density is an important process parameter because it directly affects the performance, reliability and manufacturing yield of the chip. POLY Dn is expressed as a percentage, which specifies the maximum allowable area of ​​the polysilicon layer in a specific area, where POLY Dn < 45% means that the area of ​​the polysilicon layer cannot exceed 45%; nfinSpace is a parameter used to control the spacing between polysilicon (POLY) layers in the FinFET process, which refers to the minimum spacing between the polysilicon layers of adjacent FinFET transistors.

[0038] Further, the MOS tube capacitance and metal capacitance are obtained, and the calculation range of POLY density is determined to be the BOX range with the lower left corner of POLY as the starting point and the upper right corner as the end point; within the defined BOX range, the area of ​​the POLY layer is calculated, and at the same time, the total area of ​​the BOX range is calculated. This area is the total area of ​​the area where the POLY layer is located, including the area of ​​the POLY layer and other layers; according to the ratio of the POLY area within the calculation range to the total area of ​​BOX, the POLY density ratio is calculated in real time; then the POLY Dn requirement threshold of the process is obtained to determine whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, the MOS tube layout parameters such as nfinSpace are adjusted to reduce the POLYdensity while keeping the MOS capacitance unchanged; the POLY density ratio is calculated repeatedly and the POLY Dn requirement threshold is determined until the POLYdensity meets the CMP requirement threshold; then, according to the adjusted layout parameters, whether the layout area is sufficient is determined; when the layout area is insufficient, the layout parameters are adjusted continuously until the layout area meets the requirements, and the final layout parameters and layout area are output.

[0039] Specifically, by defining the calculation range of POLY density and calculating POLYdensity in real time during layout design, ensure that it meets the process requirements (POLY Dn requirement <45%). When POLY density exceeds the threshold, by adjusting the layout parameters of the MOS tube (such as nfinSpace), the POLY density ratio is reduced without changing the MOS capacitance, and it is quickly determined whether it meets the layout CMP requirements. This process effectively avoids the problem of redrawing due to insufficient layout area due to excessive POLY density, reduces workload, and improves the efficiency and reliability of layout design.

[0040] S6. Integrate the calculation results of MOS tube capacitance and MOM capacitance into a Pcell to form a complete capacitance module. In the layout design, by calling the Pcell parameters, quickly generate the corresponding capacitance layout according to the design requirements, perform automatic layout and routing of the capacitance module, and perform DRC (design rule check) and LVS (circuit layout comparison) verification on the generated Pcell layout to ensure that the layout meets the process requirements and has no design errors. By comparing with the test results, verify the accuracy and reliability of the Pcell layout to ensure that its performance in actual applications meets the design expectations.

[0041] Furthermore, the calculation results of the MOS tube capacitance and the MOM capacitance are used to form a complete capacitance module. According to the design requirements, the parameter specifications of the capacitance module, including capacitance value, area, shape, etc., are determined as input parameters of the Pcell. By calling the corresponding capacitance Pcell, the design parameters are passed in. The Pcell automatically generates a capacitance layout that meets the requirements according to the preset layout and routing algorithm and design rules. Perform a design rule check (DRC) on the generated capacitor layout to check whether the layout meets the design specifications of the process. If the check fails, adjust the Pcell parameters to regenerate the layout until the DRC check passes. Then compare the generated capacitor layout with the schematic diagram for LVS circuit layout verification to check whether the electrical connections of the layout and the schematic diagram are consistent. If the LVS verification fails, return to modify the Pcell parameters and regenerate the layout until the LVS verification passes.

[0042] Specifically, in layout design, by calling Pcell to quickly generate capacitor layout, the design efficiency can be greatly improved and the workload of manual layout and routing can be reduced. At the same time, the built-in layout and routing algorithm of Pcell can ensure the quality and consistency of the layout. The generated Pcell layout is checked by DRC design rules and compared with LVS circuit layout to verify the problems in the layout design in time, improve the correctness and reliability of the design, and avoid errors in later plate making and production. Through Pcell parametric design, rapid iteration and optimization of capacitor modules can be achieved. By adjusting Pcell parameters, capacitor layouts of different specifications and performances can be easily generated to meet different design requirements.

[0043] In the simulation circuit construction and data acquisition of this embodiment, by constructing a simulation circuit and setting different Vgs voltage values ​​for simulation, the capacitance value change of the 1.8V MOS tube at different voltages is recorded, a curve graph is drawn and the linear relationship between finger and length and the capacitance value and the capacitance change trend with voltage at different voltages are analyzed; a capacitance data table is generated, and according to the simulation result data, the capacitance values ​​of different voltages, different tube parameters and different tube types are scanned out by formula, the capacitance change slope of the MOS tube of the same size at different voltages is calculated, and converted into a linear result to obtain the reference capacitance value C1, and the capacitance value C2 at different lengths and the capacitance value C at different fingers are calculated, so that the capacitance value of the MOS tube can be intuitively evaluated in the pre-simulation stage, which is conducive to the evaluation of the layout area and solves the problem of difficult evaluation in the pre-simulation stage caused by the change of the capacitance value of the MOS tube.

[0044] Then, the calculation result of the MOS tube capacitance is used to deduce the capacitance change slope through simulation data to form the Pcell parameters associated with the geometric parameters, so as to realize fast calculation and visualization in the layout; at the same time, the calculation of the MOM capacitance is realized by extracting the capacitance of the metal layer and combining the process conditions to form the Pcell parameters associated with the metal layer and area, so as to realize fast calculation and visualization in the layout; for fast calculation of metal capacitance, according to the simulation result data, the metal layer of Metal4 and above is selected, and the capacitance per unit area is calculated by extracting the capacitance of metal C and combining the capacitance of the MOM capacitor under the same process conditions. In the Pcell, the overall metal capacitance is calculated according to the designed metal area. The metal capacitor is quickly calculated; the calculated metal capacitance is associated with the selection of metal level, metal area and other parameters to form Pcell parameters, and in the layout design, by selecting different metal levels and adjusting the metal area, the corresponding capacitance is quickly obtained using the calculation method of the MOS tube, and it is intuitively displayed in the layout to realize the visualization of the MOM capacitor; this not only avoids the problem that the metal routing spacing caused by the change of the MOM capacitor pressure difference affects the PV verification, but also reduces the situation of connection short circuit or DRC error caused by the change of the position of the positive and negative plates, and at the same time avoids the DRC error caused by the possible addition of the voltage recognition layer in the production of the MOM capacitor, solving a series of problems in the design of the MOM capacitor.

[0045] In addition, including POLY density optimization, according to the formed Pcell parameters, define the calculation range of POLY density, calculate POLY density in real time during layout design and layout to ensure that it meets the process requirements, and by adjusting the layout parameters of the MOS tube, reduce the POLY density ratio without changing the MOS capacitance, quickly determine whether it meets the layout CMP requirements, avoid redrawing the layout due to insufficient layout area caused by excessive POLY density, and reduce workload; this effectively solves the problem that POLY density is likely to exceed the required range when filter capacitors are used on a large scale, ensures the rationality of layout design and layout, and avoids redrawing the layout due to insufficient layout area in the later stage, which increases workload.

[0046] Capacitor module integration and verification, integrating the calculation results of MOS tube capacitance and MOM capacitance into a Pcell to form a complete capacitor module. In layout design, by calling the Pcell parameters, the corresponding capacitor layout is quickly generated according to the design requirements, and the automatic layout and routing of the capacitor module is performed. The generated Pcell layout is verified by DRC and LVS to ensure that the layout meets the process requirements and there are no design errors. By comparing with the test results, the accuracy and reliability of the Pcell layout are verified to ensure that its performance in practical applications meets the design expectations; this ensures the correctness and reliability of the layout design and avoids subsequent problems caused by layout design errors. The entire process, from simulation data acquisition to layout design and verification, is closely linked and progressive, and ultimately achieves efficient and accurate capacitor layout design, effectively solving many of the problems mentioned in the background technology.

[0047] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for generating a visualized Pcell layout of MOS and MOM capacitors, characterized in that: The steps include: The capacitance change of 1.8V MOS tube under different Vgs voltages is recorded through simulation circuit, and a curve is drawn to analyze the linear relationship between finger, length and capacitance. According to the simulation results, the capacitance change slope of the MOS tube under different voltages is calculated to generate the reference capacitance C1, the capacitance C2 and C under different lengths and fingers are calculated, and the capacitance data table of the MOS tube is generated; According to the capacitance data table of MOS tube, it is associated with geometric parameters to form Pcell parameters, and then quickly calculate and visualize them in the layout; According to the simulation result data, select Metal4 and above metal levels, calculate the MOM capacitor capacitance per unit area based on the process conditions, and calculate the overall metal capacitance based on the designed metal area; According to the MOS tube capacitance and the overall metal capacitance, the POLY density calculation range is defined, the POLYdensity is calculated in real time, and the POLY density ratio is reduced by adjusting the layout parameters to determine whether the layout meets the CMP requirements.

2. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: The capacitance change of 1.8V MOS tube under different Vgs voltages is recorded through simulation circuit, and a curve is drawn to analyze the linear relationship between finger, length and capacitance, including: According to the parameters of the 1.8V MOS tube, a MOS tube circuit model is constructed in the simulation circuit design software, and different Vgs voltage values ​​are set. Multiple simulations are performed through the circuit simulation software to obtain the capacitance value data of the MOS tube under different Vgs voltages; The acquired capacitance value data is sorted out, and a curve graph of capacitance value and Vgs voltage is drawn through data analysis software. According to the drawn curve graph, the linear relationship between the finger and Length parameters of the MOS tube and the capacitance value is analyzed to obtain the influence of finger and Length on the capacitance value. For the capacitance value data under different Vgs voltages, the trend of capacitance value changing with Vgs voltage is judged by curve fitting algorithm, and the mathematical model between capacitance value and Vgs voltage is obtained. Then, the mapping relationship model between capacitance value and Vgs voltage, finger, and Length parameters is trained by machine learning algorithm to predict the capacitance value of MOS tube under any parameter combination. According to the established mathematical model and machine learning model, the finger and length parameter design of the MOS tube are optimized to obtain the optimal capacitance value and linear characteristics while meeting the circuit performance requirements.

3. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: Generate the capacitance data table of MOS tube, including: According to the simulation result data, the voltage parameters, tube parameters and tube type information are extracted, and a multidimensional array is established to store the simulated capacitance data under different conditions. The voltages and tube parameters of different tube types are traversed, and the capacitance calculation formula is called to obtain the capacitance under the corresponding conditions, and the capacitance is updated to the corresponding multidimensional array. From the multidimensional array, select the MOS tube data of the same size, perform linear fitting on the capacitance data under different voltages, and obtain the slope of the capacitance change with voltage under the corresponding size. Then select the reference Length and finger as the initial value, and according to the capacitance change slope under the size, extrapolate and calculate the capacitance under zero voltage as the reference capacitance C1; Among them, starting from the reference Length, applying the Length slope formula, traversing different Lengths, calculating the capacitance C2 under the corresponding conditions, and updating the Length-capacitance mapping table; starting from the reference finger, traversing different values ​​of finger, calling the mapping formula of index and capacitance, calculating the capacitance C under different finger values, and continuously updating the finger-capacitance mapping table; The length-capacitance mapping table and the finger-capacitance mapping table are combined to generate a capacitance data table covering different lengths, fingers, and voltage conditions.

4. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: According to the capacitance data table of MOS tube, Pcell parameters are formed by associating with geometric parameters, including: Obtain the capacitance data table of the MOS tube, extract the corresponding relationship data between the capacitance and the geometric parameters, establish the Pcell parameterized model of the MOS tube capacitor according to the extracted corresponding relationship data between the capacitance and the geometric parameters, and associate and map the capacitance and the geometric parameters; in the Pcell parameterized model, set the geometric parameters as input variables and the capacitance as output variables, establish a parameterized calculation formula, integrate the Pcell parameterized model into the layout design tool, perform real-time association calculation between the geometric parameters and the capacitance change slope, and perform visual adjustment of the geometric parameters according to the Pcell parameterized model. In the layout design process, the MOS tube capacitance is calculated by calling the Pcell parameterized model. When the layout design needs to adjust the MOS tube capacitance, the capacitance of the adjusted MOS tube capacitance is calculated according to the geometric parameters of the adjusted MOS tube capacitance, and the visualization of the MOS tube capacitance is updated in real time in the layout.

5. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 4, it is characterized in that: After associating with geometric parameters to form Pcell parameters, it also includes: obtaining the capacitance of MOM capacitors at different metal levels, analyzing the relationship between the capacitance of the MOM capacitor and the metal level and area, establishing a Pcell model of the MOM capacitor, the Pcell model includes a mapping relationship between the metal level, area and capacitance, and during layout design, according to the metal level and area parameters of the MOM capacitor, using the Pcell model of the MOM capacitor to calculate the capacitance of the corresponding MOM capacitor.

6. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 5, it is characterized in that: The overall metal capacitance is calculated according to the designed metal area, specifically including: obtaining Metal4 and above metal levels, extracting the corresponding metal capacitance, obtaining the capacitance data under the same process conditions as the MOM capacitor, combining the extracted metal capacitance, calculating the capacitance per unit area, and obtaining the corresponding capacitance per unit area according to the metal area designed in the Pcell model by table lookup or interpolation. The metal area is multiplied by the capacitance per unit area to obtain the overall metal capacitance, and then the overall metal capacitance is used as a parameter of the MOM capacitor to calculate the overall capacitance to obtain the calculation result.

7. A MOS and MOM capacitor visualization Pcell layout generation method according to claim 6, characterized in that: According to the calculation results, it also includes: analyzing the capacitance characteristics of different metal levels and selecting the optimal metal level combination; adjusting the metal area according to design requirements, using the MOS tube calculation method to obtain the corresponding capacitance value, and obtaining the optimized metal level, area and corresponding capacitance value, and using the optimized value as the input parameter of the Pcell model of the MOM capacitor to calculate the metal capacitance and display it intuitively in the layout.

8. A kind of MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, it is characterized in that: Define the POLY density calculation range, calculate the POLY density in real time, adjust the layout parameters to reduce the POLYdensity ratio, and judge whether it meets the layout CMP requirements, including: obtain the MOS tube capacitance and metal capacitance, determine the POLYdensity calculation range as the BOX range with the lower left corner of the POLY as the starting point and the upper right corner as the end point, calculate the area of ​​the POLY layer within the defined BOX range, and at the same time, calculate the total area of ​​the BOX range; calculate the POLY density ratio in real time according to the ratio of the POLY area within the calculation range to the total BOX area; then obtain the POLY Dn requirement threshold of the process to judge whether the calculated POLY density meets the requirements; when the POLY density exceeds the threshold, adjust the MOS tube layout parameters to reduce the POLY density while keeping the MOS capacitance unchanged; repeatedly calculate the POLY density ratio and judge whether the POLY Dn meets the requirement threshold until the POLY density meets the CMP requirement threshold; then determine whether the layout area is sufficient according to the adjusted layout parameters; when the layout area is insufficient, continue to adjust the layout parameters until the layout area meets the requirements, and output the final layout parameters and layout area.

9. A MOS and MOM capacitor visualization Pcell layout generation method according to claim 1, characterized in that: Also includes: The calculation results of MOS tube capacitance and MOM capacitance are integrated into a Pcell to form a complete capacitance module. In the layout design, by calling the Pcell parameters, the corresponding capacitance layout is quickly generated according to the design requirements, and the capacitance module is automatically laid out and wired. The generated Pcell layout is checked for design rules and compared with the circuit layout to ensure that the layout meets the process requirements.

10. A method for generating a MOS and MOM capacitor visualization Pcell layout according to claim 9, characterized in that: The calculation results of MOS tube capacitance and MOM capacitance are used to form a complete capacitance module. According to the design requirements, the parameter specifications of the capacitance module are determined and used as the input parameters of Pcell. By calling the corresponding capacitance Pcell, the design parameters are passed in. The Pcell automatically generates a capacitance layout that meets the requirements according to the preset layout and routing algorithm and design rules. Perform a design rule check on the generated capacitor layout to check whether the layout meets the design specifications of the process. If the check fails, adjust the Pcell parameters to regenerate the layout until the DRC check passes. Then compare the generated capacitor layout with the schematic diagram for LVS circuit layout verification to check whether the electrical connections of the layout and the schematic diagram are consistent. If the layout comparison verification fails, return to modify the Pcell parameters and regenerate the layout until the layout comparison verification passes.

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