Transposition circuit, transposition method and related device

Abstract

The invention relates to a transposition circuit, a transposition method and a related device. A transpose circuit includes: an input module configured to receive first data of N rows * M columns; the storage module is connected to the input module and comprises a plurality of first storage units in N rows and M columns, and the storage module is configured to write each column of data of the first data into a corresponding column of storage units in the plurality of first storage units in a corresponding period of a first cycle; the selection module is connected to the storage module and is configured to output data read from each row of storage units in the plurality of first storage units in a corresponding period of a second cycle after the first cycle; and an output module connected to the selection module and configured to output the data received from the selection module as transposed first data, where N and M are positive integers and at least one of N and M is greater than 1.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of electronic circuits, and more specifically, to a transposition circuit and a transposition method, and also to a two-dimensional (2D) discrete cosine transform (DCT) device, a processor, and a computing device including such a transposition circuit. Background Art

[0002] 2D DCT is widely used in the field of image and video processing, mainly for signal compression and feature extraction. In 2D DCT, the intermediate results of the transformation need to be transposed. Specifically, the transposition operation refers to converting the data input in rows to output in columns, or converting the data input in columns to output in rows. In the hardware implementation of 2D DCT, the transposition circuit is a key part. For example, 2D DCT is usually divided into two one-dimensional (1D) DCT steps, that is, the row transformation is first transformed and then the column transformation, but the data access mode of the row transformation and the column transformation is different. In this regard, the transposition circuit can rearrange the data between the row transformation and the column transformation to ensure that the data is input in the correct order. Summary of the invention

[0003] According to a first aspect of the present disclosure, a transposition circuit is provided, comprising: an input module, configured to receive N rows×M columns of first data; a storage module, connected to the input module and comprising a first plurality of storage cells of N rows×M columns, the storage module being configured to write each column of the first data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of a first cycle; a selection module, connected to the storage module and configured to output data read out from each row of storage cells in the first plurality of storage cells in a corresponding cycle of a second cycle after the first cycle; and an output module, connected to the selection module and configured to output the data received from the selection module as the transposed first data, wherein N and M are positive integers and at least one of N and M is greater than 1.

[0004] In some embodiments, the selection module includes a multiplexer combination having N input terminals and 1 output terminal, each of the N input terminals is connected to a corresponding row of storage cells in the first plurality of storage cells, and the 1 output terminal is connected to the output module.

[0005] In some embodiments, the input module is also configured to receive N rows×M columns of second data, and the storage module also includes N rows×M columns of a second plurality of storage cells and is configured to write each column of the second data into a corresponding column of storage cells in the second plurality of storage cells in a corresponding cycle of the second cycle, wherein the selection module is also configured to output the data read from each row of storage cells in the second plurality of storage cells in a corresponding cycle of a third cycle after the second cycle, wherein the output module is also configured to output the data received from the selection module as the transposed second data.

[0006] In some embodiments, the input module is further configured to receive N rows × M columns of third data, the storage module is further configured to write each column of the third data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of the third cycle, the selection module is further configured to output the data read from each row of storage cells in the first plurality of storage cells in a corresponding cycle of a fourth cycle after the third cycle, and the output module is further configured to output the data received from the selection module as the transposed third data.

[0007] In some embodiments, the selection module includes a multiplexer combination having 2N input terminals and 1 output terminal, each of the 2N input terminals is connected to a corresponding row of storage cells in the N rows of storage cells of the first plurality of storage cells and the N rows of storage cells of the second plurality of storage cells, and the 1 output terminal is connected to the output module.

[0008] In some embodiments, the selection module includes: a first selection submodule, including a first multiplexer combination having N input terminals and y output terminals, each of the N input terminals of the first multiplexer combination being connected to a corresponding row of storage cells in the x rows of the first plurality of storage cells and the Nx rows of storage cells in the second plurality of storage cells; a second selection submodule, including a second multiplexer combination having N input terminals and z output terminals, each of the N input terminals of the second multiplexer combination being connected to the remaining Nx rows of storage cells in the first plurality of storage cells. storage unit and a corresponding row of storage units among the remaining x rows of storage units of the second plurality of storage units; a third selection submodule, comprising a third multiplexer combination having y+z input terminals and 1 output terminal, the y output terminals of the first multiplexer combination and the z output terminals of the second multiplexer combination are respectively connected to corresponding input terminals among the y+z input terminals of the third multiplexer combination, and the 1 output terminal of the third multiplexer combination is connected to the output module, wherein x is an integer and 0≤x≤N, y is an integer and 0<y<N, and z is an integer and 0<z<N.

[0009] In some embodiments, x=0 or N, y=z=1.

[0010] In some embodiments, x=y=z=N / 2, wherein the first multiplexer combination includes N / 2 2-to-1 multiplexers, a first input of each 2-to-1 multiplexer is connected to a corresponding row of storage cells among the x rows of storage cells of the first plurality of storage cells and a second input is connected to a corresponding row of storage cells among the Nx rows of storage cells of the second plurality of storage cells, and the second multiplexer combination includes N / 2 2-to-1 multiplexers, a first input of each 2-to-1 multiplexer is connected to a corresponding row of storage cells among the remaining Nx rows of storage cells of the first plurality of storage cells and a second input is connected to a corresponding row of storage cells among the remaining x rows of storage cells of the second plurality of storage cells.

[0011] In some embodiments, the input module includes a first trigger configured to output each column of received data to a corresponding column of storage cells based on a received clock signal. In some embodiments, the output module includes a second trigger configured to output the received data read out from each row of storage cells based on a received clock signal.

[0012] In some embodiments, the memory cell includes: a latch cell; or a dynamic random access memory DRAM cell; or a static random access memory SRAM cell.

[0013] In some embodiments, N is equal to M.

[0014] In some embodiments, the data is image data.

[0015] According to a second aspect of the present disclosure, a two-dimensional discrete cosine transform device is provided, comprising the transposition circuit according to the first aspect of the present disclosure, wherein N is equal to M.

[0016] According to a third aspect of the present disclosure, a processor is provided, comprising the transposition circuit according to the first aspect of the present disclosure or the two-dimensional discrete cosine transform device according to the second aspect of the present disclosure.

[0017] According to a fourth aspect of the present disclosure, a computing device is provided, comprising the transposition circuit according to the first aspect of the present disclosure or the two-dimensional discrete cosine transform device according to the second aspect of the present disclosure or the processor according to the third aspect of the present disclosure.

[0018] According to a fifth aspect of the present disclosure, a transposition method is provided, comprising: receiving N rows×M columns of first data and writing each column of the first data into a corresponding column of storage cells in a first plurality of storage cells of N rows×M columns in a corresponding cycle of a first cycle; outputting data read out from each row of storage cells in the first plurality of storage cells in a corresponding cycle of a second cycle after the first cycle, and receiving N rows×M columns of second data and writing each column of the second data into a corresponding column of storage cells in a second plurality of storage cells of N rows×M columns in a corresponding cycle of the second cycle; outputting data read out from each row of storage cells in the second plurality of storage cells in a corresponding cycle of a third cycle after the second cycle, wherein N and M are positive integers and at least one of N and M is greater than 1.

[0019] In some embodiments, the transposition method also includes: receiving N rows × M columns of third data and writing each column of the third data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of the third cycle; and outputting the data read out from each row of storage cells in the first plurality of storage cells in a corresponding cycle of a fourth cycle after the third cycle.

[0020] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which constitute a part of the specification, describe embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure. With reference to the accompanying drawings, the present disclosure can be more clearly understood according to the following detailed description, in which: Figure 1 A transposition circuit according to a comparative example of the present disclosure is shown; Figure 2 A transposition circuit according to some embodiments of the present disclosure is shown; Figure 3 A transposition circuit according to some other embodiments of the present disclosure is shown; Figure 4 Shows Figure 3 An exemplary implementation of the selection module of the transposition circuit shown; Figure 5 Shows Figure 3 Another exemplary implementation of the selection module of the transposition circuit shown; Figure 6 An example implementation of a data writing portion of a transposition circuit according to some embodiments of the present disclosure is shown; Figure 7 An example implementation of a data readout portion of a transposition circuit according to some embodiments of the present disclosure is shown; Figure 8 Another example implementation of a data readout portion of a transposition circuit according to some embodiments of the present disclosure is shown; Fig. 9 is a flow chart illustrating a transposition method according to some embodiments of the present disclosure; Fig.10 An example implementation of a storage unit of a transposition circuit according to some embodiments of the present disclosure is shown.

[0022] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in other drawings unless otherwise specified.

[0023] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0025] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0026] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0028] Figure 1 FIG. 1 shows a transposition circuit 10 according to a comparative example of the present disclosure, which can be used to perform a transposition operation on 4×4 two-dimensional data (eg, an image). Figure 1 As shown, the transposition circuit 10 includes a column input module 11, a column output module 12, a row input module 13, a row output module 14 and a storage module 15. Specifically, the storage module 15 is composed of 16 register groups arranged in 4 rows and 4 columns, and each register group can store one data in the two-dimensional data (for example, one pixel in the image). The number of registers included in each register group can be determined by the bit width of the data to be stored in the register group. The column input module 11 is connected to the input end of the first column register group p00 to p30, the output end of the first column register group p00 to p30 is respectively connected to the input end of the second column register group p01 to p31, the output end of the second column register group p01 to p31 is respectively connected to the input end of the third column register group p02 to p32, the output end of the third column register group p02 to p32 is respectively connected to the input end of the fourth column register group p03 to p33, and the output end of the fourth column register group p03 to p33 is connected to the column output module 12. The row input module 13 is connected to the input ends of the first row register group p00 to p03, the output ends of the first row register group p00 to p03 are respectively connected to the input ends of the second row register group p10 to p13, the output ends of the second row register group p10 to p13 are respectively connected to the input ends of the third row register group p20 to p23, the output ends of the third row register group p20 to p23 are respectively connected to the input ends of the fourth row register group p30 to p33, and the output ends of the fourth row register group p30 to p33 are connected to the row output module 14.

[0029] For example, in the first loop, the two-dimensional data A= The first column data a_0 of the two-dimensional data A is input to the storage module 15 by column through the column input module 11. Specifically, in the first cycle of the first cycle, the first column data a_0 of the two-dimensional data A= Stored in the first column register group p00 to p30; in the second cycle of the first loop, the first column data a_0 of the two-dimensional data A is shifted right as a whole to be stored in the second column register group p01 to p31, and the second column data a_1 of the two-dimensional data A= stored in the first column register group p00 to p30; in the third cycle of the first loop, the first column data a_0 and the second column data a_1 of the two-dimensional data A are shifted right as a whole to be stored in the third column register group p02 to p32 and the second column register group p01 to p31 respectively, and the third column data a_2 of the two-dimensional data A= stored in the first column register group p00 to p30; in the fourth cycle of the first loop, the first column data a_0, the second column data a_1 and the third column data a_2 of the two-dimensional data A are shifted right as a whole to be stored in the fourth column register group p03 to p33, the third column register group p02 to p32 and the second column register group p01 to p31 respectively, and the fourth column data a_3 of the two-dimensional data A= Stored in the first column register group p00 to p30. So far, after 4 cycles, the storage module 15 is fully stored with the two-dimensional data A.

[0030] Next, in the second cycle, the two-dimensional data A is output row by row from the storage module 15 via the row output module 14, and the two-dimensional data B= The row input module 13 is input to the storage module 15 row by row. Specifically, in the first cycle of the second cycle, the fourth row data a3_= The third row data a2_= of the two-dimensional data A is output from the fourth row register group p30 to p33 to the row output module 14. 、The second row of data a1_= And the first row of data a0_= The entire data is shifted downward to be stored in the fourth row register group p30 to p33, the third row register group p20 to p23 and the second row register group p10 to p13 respectively, and the fourth row data b3_= stored in the first row register group p00 to p03; in the second cycle of the second loop, the third row data a2_ of the two-dimensional data A is output from the fourth row register group p30 to p33 to the row output module 14, the second row data a1_ and the first row data a0_ of the two-dimensional data A and the fourth row data b3_ of the two-dimensional data B are shifted down as a whole to be stored in the fourth row register group p30 to p33, the third row register group p20 to p23 and the second row register group p10 to p13 respectively, and the third row data b2_ of the two-dimensional data B= stored in the first row register group p00 to p03; in the third cycle of the second loop, the second row data a1_ of the two-dimensional data A is output from the fourth row register group p30 to p33 to the row output module 14, the first row data a0_ of the two-dimensional data A and the fourth row data b3_ and the third row data b2_ of the two-dimensional data B are shifted down as a whole to be stored in the fourth row register group p30 to p33, the third row register group p20 to p23 and the second row register group p10 to p13 respectively, and the second row data b1_ of the two-dimensional data B= stored in the first row register group p00 to p03; in the fourth cycle of the second loop, the first row data a0_ of the two-dimensional data A is output from the fourth row register group p30 to p33 to the row output module 14, the fourth row data b3_, the third row data b2_ and the second row data b1_ of the two-dimensional data B are shifted down as a whole to be stored in the fourth row register group p30 to p33, the third row register group p20 to p23 and the second row register group p10 to p13 respectively, and the first row data b0_ of the two-dimensional data B= Stored in the first row of registers p00 to p03. So far, after 4 cycles, the transposed two-dimensional data A is completely output from the storage module 15, and the storage module 15 is filled with the two-dimensional data B again.

[0031] In the next third cycle, the two-dimensional data B can be outputted from the storage module 15 by column via the column output module 12, and at the same time, the two-dimensional data C can be inputted to the storage module 15 by column via the column input module 11 again as the two-dimensional data A. The transposition circuit 10 cycles back and forth between column input, row output, and row input, column output, so that a transposition result of the two-dimensional data can be outputted in each cycle.

[0032] It can be seen from the above process that since the transposition circuit 10 is always performing a data shift operation during the transposition operation, all registers need to undergo data flipping in each cycle (flipping means that the signal changes from 0 to 1 or from 1 to 0). Such a high flipping rate causes the dynamic power consumption of the transposition circuit 10 to be very high. In addition, the circuit area consumed by the register is large. However, since the transposition operation of the transposition circuit 10 depends on the data shift operation, and the shift operation requires precise timing control, an edge-triggered register is required to provide strict timing control.

[0033] In this regard, the present disclosure provides a transposition circuit that can perform a transposition operation without performing a data shift operation, thereby having a reduced flip rate and thus a reduced dynamic power consumption. The transposition circuit according to various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the actual circuit may also include other components, and in order to avoid blurring the main points of the present disclosure, these other components are not discussed herein and are not shown in the accompanying drawings.

[0034] Figure 2 FIG. 1 shows a transposition circuit 100 according to some embodiments of the present disclosure. Figure 2 As shown, the transposition circuit 100 includes an input module 110, a storage module 120, a selection module 130, and an output module 140. It should be understood that although the input module 110 is depicted as a column input module and the output module 140 is depicted as a row output module in the drawings, and the transposition operation of converting data input in columns to data output in rows is mainly used as an example for explanation, this is merely exemplary and not restrictive, and in this article, "row" and "column" are relative concepts and can be used interchangeably.

[0035] The input module 110 is configured to receive N rows×M columns of first data. N and M are positive integers and at least one of N and M is greater than 1. In some embodiments, N is equal to M. For example, N and M can each be equal to 2. i , i is a positive integer. In the embodiment shown in the accompanying drawings, N and M are each equal to 4, thereby providing a 4×4 transposition unit. It can be understood that this is merely exemplary and not restrictive, and the present disclosure can also similarly provide transposition units of different specifications such as 2×2, 8×8, 16×16, 32×32, etc. N and M can also have other values ​​as needed. In some embodiments, N may not be equal to M. In this article, for ease of description, N=M=4 will be mainly used as an example for explanation. In addition, the data processed by the present disclosure can be any form of two-dimensional data, such as but not limited to image data.

[0036] The input module 110 includes an input terminal of the transposition circuit 100. In some embodiments, the input module 110 may include a first trigger (which will be illustrated later), which may be in the form of a D flip-flop (D Flip-flop, DFF). The first trigger can cut off the timing outside the transposition circuit 100, thereby ensuring the timing inside the transposition circuit 100.

[0037] The storage module 120 is connected to the input module 110 and includes a first plurality of storage units 122 of N rows×M columns. Since there is no need to perform a data shift operation, the storage units 122 do not need to be connected to each other. The input end of each storage unit 122 can be connected only to the input module 110 without being connected to other storage units 122. The input end of each storage unit 122 can receive data to be written only from the input module 110 without shifting the data in other storage units 122 and storing it therein. Moreover, since there is no need to perform a data shift operation, the storage unit 122 does not need to provide strict timing control, but can be formed by any circuit element that can provide a storage function, and does not necessarily need to use a register. In the case of satisfying the storage function, the storage unit 122 can use a circuit element with as small an area as possible. For example, the storage unit 122 may include a storage element, which may be selected from the group consisting of a latch cell, a dynamic random access memory cell (DRAM Cell), or a static random access memory cell (SRAM Cell). The number of storage elements included in the storage unit 122 may be determined by the bit width of the data to be stored in the storage unit 122. These implementations of the storage unit 122 have greater area advantages than the register implementation. For example, the latch unit may be a dynamic latch unit or a static latch unit. Of course, the storage element of the storage unit 122 may also be a register.

[0038] The storage module 120 is configured to write each column of the first data into a corresponding column of storage cells 122 in a corresponding cycle of the first cycle. Specifically, during the writing process, no data shift operation occurs in the storage module 120, but a new column of data is stored in a new column of storage cells 122 each time. For example, referring to Figure 2 , in the first cycle, the two-dimensional data A = The first column data a_0 of the two-dimensional data A is input to the storage module 120 by column through the input module 110. Specifically, in the first cycle of the first cycle, the first column data a_0 of the two-dimensional data A= Stored in the first column storage unit 1221, 1225, 1229, 122 13 ; In the second cycle of the first loop, the second column data a_1 of the two-dimensional data A = Stored in the second column storage unit 1222, 1226, 122 10 , 122 14 ; In the third cycle of the first loop, the third column data a_2 of the two-dimensional data A = Stored in the third column storage unit 1223, 1227, 122 11 , 122 15 ; In the fourth cycle of the first loop, the fourth column data a_3 of the two-dimensional data A = Stored in the fourth column storage unit 1224, 1228, 122 12 , 122 16 At this point, after 4 cycles, the first plurality of storage cells 122 of the storage module 120 are fully stored with the two-dimensional data A. It can be understood that the above sequence is merely exemplary and not restrictive. Because it is not limited by the shift operation, each column of the first data can actually be stored in any column of storage cells 122 that has not yet stored new data in this cycle.

[0039] For example, the writing to each storage unit 122 can be controlled by a clock signal. For non-limiting illustration purposes, Fig.10 An example implementation of a storage unit is shown. Fig.10 As shown in (A) in FIG. 1 , the memory cell may have an input terminal D, an output terminal Q, and a clock control terminal G. The clock control terminal G is configured to receive a clock signal clk. When the clock signal clk is configured to cause a signal flip at the clock control terminal G of the memory cell, the data wd received at the input terminal D of the memory cell will be written into the memory cell. When the clock signal clk is configured not to cause a signal flip at the clock control terminal G of the memory cell, the data wd received at the input terminal D of the memory cell will not be written into the memory cell. Alternatively, the writing to each memory cell 122 may be controlled by a selection signal. As shown in FIG. Fig.10As shown in (B) in FIG. 1 , a multiplexer MUX may be arranged before the storage unit, wherein the first input terminal of the multiplexer MUX is used to receive the data wd and the second input terminal is used to receive the output at the output terminal Q of the storage unit. The output terminal of the multiplexer MUX is coupled to the input terminal D of the storage unit. In this case, the clock signal clk may always be configured to cause a signal flip at the clock control terminal G of the storage unit, and at the same time, the selection signal sel is used to select whether to use the data wd as the output of the multiplexer MUX so that the data wd is written into the storage unit, or to use the original data of the storage unit as the output of the multiplexer MUX so that the data wd is not written into the storage unit. In these implementations, the data wd may always be provided to the input terminal D of the storage unit.

[0040] In some embodiments, the input module 110 may include N cache units, each of which is used to temporarily store a corresponding row of data (i.e., one data) in a column of data currently received. Each cache unit may be connected to each storage unit 122 in a corresponding row of storage units 122. For example, referring to Figure 2 In the first cycle of the first loop, the four cache units (not shown) of the input module 110 can respectively store each row of data a00, a10, a20, and a30 in the first column data a_0 of the two-dimensional data A. The first cache unit storing the data a00 can be connected to the first row storage units 1221, 1222, 1223, and 1224, so that the data a00 can be provided as wd to the input terminal D of each storage unit 122 in the first row storage units 1221, 1222, 1223, and 1224. At this time, refer to Fig.10 In (A), the clock control terminal G of the storage unit 1221 in the first column can be inverted to write data a00 into the storage unit 1221, and the clock control terminals G of the storage units 1222, 1223, and 1224 in other columns can be not inverted to prevent data a00 from being written into the storage units 1222, 1223, and 1224. Similarly, the input terminals D of the second row storage units, the third row storage units, and the fourth row storage units are also respectively connected to the second cache unit storing data a10, the third cache unit storing data a20, and the fourth cache unit storing data a30 to receive corresponding data a10, a20, and a30 therefrom. At this time, the clock control terminal G of the storage unit in the first column can be inverted to write corresponding data a10, a20, and a30 therein, and the clock control terminals G of the storage units in other columns can be not inverted to prevent corresponding data a10, a20, and a30 from being written therein.

[0041] The above writing process does not involve data shifting operation, and only one column of storage cells 122 undergoes data flipping in each cycle. Such a low flipping rate results in low dynamic power consumption.

[0042] The selection module 130 is connected to the storage module 120. The output module 140 is connected to the selection module 130 and is configured to output the data received from the selection module 130 as the first data after transposition. The output module 140 includes an output end of the transposition circuit 100. In some embodiments, the input module 110 may include M cache units (not shown), each cache unit is used to temporarily store a corresponding column of data (i.e., one data) in a row of data currently received. In some embodiments, the output module 140 may include a second trigger (to be shown later), which may be in the form of a DFF, for example. The second trigger can cut off the timing outside the transposition circuit 100, thereby ensuring the timing inside the transposition circuit 100.

[0043] The selection module 130 is configured to output the data read from a corresponding row of storage cells 122 in the first plurality of storage cells 122 in a corresponding cycle of a second cycle after the first cycle. Specifically, during the readout process, no data shift operation occurs in the storage module 120. For example, referring to Figure 2 In the second cycle, the two-dimensional data A is outputted row by row from the storage module 120 via the selection module 130 and the output module 140. Specifically, in the first cycle of the second cycle, the fourth row data a3_= From the fourth row storage unit 122 13 , 122 14 , 122 15 , 122 16 is output; in the second cycle of the second loop, the third row of two-dimensional data A a2_= From the third row storage units 1229, 122 10 , 122 11 , 122 12 is output; in the third cycle of the second loop, the second row data a1_= The first row data a0_= of the two-dimensional data A is output from the second row storage units 1225, 1226, 1227, and 1228; in the fourth cycle of the second cycle, the first row data a0_= The first row of storage units 1221, 1222, 1223, and 1224 are output. So far, after four cycles, the transposed two-dimensional data A is completely output from the first plurality of storage units 122 of the storage module 120. It can be understood that the above sequence is only exemplary and not restrictive. Because it is not limited by the shift operation, the data in any row of storage units 122 that have not been read in this cycle can actually be read out in each cycle.

[0044] The above-mentioned read-out process does not involve a data shift operation, and no data flip occurs in any storage unit 122 in each cycle. Such a low flip rate results in low dynamic power consumption.

[0045] In some embodiments, the selection module 130 may include a multiplexer combination having N input terminals, each of which is connected to a corresponding row of storage cells 122 in the first plurality of storage cells 122, and 1 output terminal connected to the output module 140. For example, referring to Figure 2 The selection module 130 may be formed by a single 4-to-1 multiplexer (not shown), or by a 4-to-2 multiplexer and a 2-to-1 multiplexer (not shown) respectively arranged in two stages, or by a pair of 2-to-1 multiplexers and a 2-to-1 multiplexer (not shown) respectively arranged in two stages, or by a 3-to-1 multiplexer and a 2-to-1 multiplexer (not shown) respectively arranged in two stages, etc. When N is large, an N-to-1 multiplexer may be difficult to obtain. In this case, a large-scale multiplexing function may be realized by cascading a plurality of smaller-scale multiplexers.

[0046] In the case where the storage module 120 of the transposition circuit 100 includes only the first plurality of storage units 122, each writing process (a cycle with an odd number such as the first cycle) requires M cycles, and each reading process (a cycle with an even number such as the second cycle) requires N cycles. By repeating the writing process and the reading process alternately, a transposition result of two-dimensional data can be obtained every two cycles (M+N cycles).

[0047] In addition, in the transposition circuit 100, only one column of storage cells 122 undergoes data flipping in each cycle of each write cycle, and no storage cell 122 undergoes data flipping in each cycle of each read cycle. Such a low flipping rate results in low dynamic power consumption, especially lower than the dynamic power consumption of the transposition circuit 10 in which all registers undergo data flipping in each cycle of each cycle. In addition, when used as transposition units of the same specification, even if the number of storage cells in the transposition circuit 100 is the same as the number of registers in the transposition circuit 10, since the storage cells in the transposition circuit 100 do not need to be implemented as registers, but circuit elements (such as latch units) with the smallest possible area that meet the storage function can be used, the transposition circuit 100 has a greater area advantage than the transposition circuit 10.

[0048] Figure 3 FIG. 2 shows a transposition circuit 200 according to some other embodiments of the present disclosure. Figure 3As shown, the difference between the transposition circuit 200 and the transposition circuit 100 is that the storage module 120 of the transposition circuit 200 also includes a second plurality of storage cells 124 of N rows×M columns. Since there is no need to perform a data shift operation, the storage cells 124 do not need to be connected to each other, let alone to the storage cell 122. The input end of each storage cell 124 can be connected only to the input module 110 without being connected to other storage cells 124 or 122. The input end of each storage cell 124 can receive data to be written only from the input module 110 without shifting the data in other storage cells 124 or 122 and storing them therein. The configuration of the storage cell 124 can be similar to the configuration of the storage cell 122, and will not be described in detail here.

[0049] For example, the input module 110 may also be configured to receive N rows×M columns of second data, and the storage module 120 may be configured to write each column of the second data into a corresponding column of storage cells 124 in a corresponding cycle of the second cycle. In other words, the second data may be written to the second plurality of storage cells 124 while the first data is read out from the first plurality of storage cells 122.

[0050] Specifically, in the process of writing the second data into the second plurality of storage units 124, no data shift operation occurs in the storage module 120, but a new column of data is stored in a new column of storage units 124 each time. Figure 3 The writing and reading processes occurring at the first plurality of memory cells 122 in the first cycle and the second cycle are similar to those described above with respect to Figure 2 Same as those described above. In addition, in the second loop, the two-dimensional data B = The first column data b_0 of the two-dimensional data B is input to the storage module 120 by column through the input module 110. Specifically, in the first cycle of the second cycle, the first column data b_0 of the two-dimensional data B= Stored in the first column storage unit 1241, 1245, 1249, 124 13 ; In the second cycle of the second loop, the second column data b_1 of the two-dimensional data B = Stored in the second column storage units 1242, 1246, 124 10 , 124 14 ; In the third period of the second loop, the third column data b_2 of the two-dimensional data B = Stored in the third column storage unit 1243, 1247, 124 11 , 124 15 ; In the fourth period of the second loop, the fourth column data b_3 of the two-dimensional data B = Stored in the fourth column storage unit 1244, 1248, 124 12 , 12416 At this point, after 4 cycles, the second plurality of storage cells 124 of the storage module 120 are fully stored with the two-dimensional data B. It can be understood that the above sequence is merely exemplary and not restrictive. Because it is not limited by the shift operation, each column of the second data can actually be stored in any column of storage cells 124 that has not yet stored new data in this cycle.

[0051] Similarly, the writing to each storage unit 124 can be controlled by various suitable methods such as clock signals or selection signals, which will not be described in detail here. In some embodiments, the input module 110 may include N cache units, each of which is used to temporarily store a corresponding row of data (i.e., one data) in a column of data currently received. Each cache unit can be connected to each storage unit 122 in a corresponding row of storage units 122 and to each storage unit 124 in a corresponding row of storage units 124. For example, referring to Figure 3 , in the first cycle of the second loop, the four cache units (not shown) of the input module 110 can respectively store each row of data b00, b10, b20, b30 in the first column data b_0 of the two-dimensional data B. The first cache unit storing the data b00 can be connected to the first row storage units 1221, 1222, 1223, 1224 and 1241, 1242, 1243, 1244, so that the data b00 can be provided as wd to the input terminal D of each storage unit in the first row storage units 1221, 1222, 1223, 1224 and 1241, 1242, 1243, 1244. At this time, refer to Fig.10(A) in the figure can cause the clock control terminal G of the storage unit 1241 located in the first column of the second N×M matrix to have a signal inversion, thereby writing the data b00 into the storage unit 1241, and can prevent the clock control terminal G of the storage units 1221, 1222, 1223, 1224 located in the first N×M matrix and the storage units 1242, 1243, 1244 located in other columns of the second N×M matrix from having a signal inversion, thereby preventing the data b00 from being written into the storage units 1221, 1222, 1223, 1224 and 1242, 1243, 1244. Similarly, the input terminals D of the second row storage units, the third row storage units and the fourth row storage units are also respectively connected to the second cache unit storing data b10, the third cache unit storing data b20 and the fourth cache unit storing data b30 to receive corresponding data b10, b20 and b30 therefrom. At this time, the clock control terminal G of the storage unit located in the first column of the second N×M matrix may be inverted to write the corresponding data b10, b20 and b30 therein, and the clock control terminal G of the storage unit located in the first N×M matrix and the storage units located in other columns of the second N×M matrix may not be inverted to prevent the corresponding data b10, b20 and b30 from being written therein.

[0052] The above writing process does not involve data shifting operation, and only one column of storage cells 124 undergoes data flipping in each cycle. Such a low flipping rate results in low dynamic power consumption.

[0053] The selection module 130 is further configured to output the data read from each row of the second plurality of storage cells 124 in a corresponding cycle of a third cycle after the second cycle. The output module 140 is further configured to output the data received from the selection module 130 as the transposed second data. Specifically, in the process of reading the second data from the second plurality of storage cells 124, no data shift operation occurs in the storage module 120. For example, referring to Figure 3 In the third cycle, the two-dimensional data B is outputted row by row from the storage module 120 via the selection module 130 and the output module 140. Specifically, in the first cycle of the third cycle, the fourth row data b3_= From the fourth row memory cell 124 13 , 124 14 , 124 15 , 124 16 In the second cycle of the third loop, the third row of two-dimensional data B b2_= From the third row storage units 1249, 124 10 , 124 11 , 124 12is output; in the third cycle of the third loop, the second row data b1_= is output from the second row storage units 1245, 1246, 1247, 1248; in the fourth cycle of the third cycle, the first row data b0_= The first row of storage units 1241, 1242, 1243, and 1244 are output. So far, after four cycles, the transposed two-dimensional data B is completely output from the second plurality of storage units 124 of the storage module 120. It can be understood that the above sequence is only exemplary and not restrictive. Because it is not limited by the shift operation, the data in any row of storage units 124 that have not been read in this cycle can actually be read out in each cycle.

[0054] The above-mentioned read-out process does not involve a data shift operation, and no data flip occurs in any storage unit 124 in each cycle. Such a low flip rate results in lower dynamic power consumption.

[0055] In some embodiments, the input module 110 is further configured to receive N rows×M columns of third data, the storage module 120 is further configured to write each column of the third data into a corresponding column of storage cells 122 in the first plurality of storage cells 122 in a corresponding cycle of the third cycle, the selection module 130 is further configured to output the data read from a corresponding row of storage cells 122 in the first plurality of storage cells 122 in a corresponding cycle of the fourth cycle after the third cycle, and the output module 140 is further configured to output the data received from the selection module 130 as the transposed third data. In other words, while the second data is read out from the second plurality of storage cells 124, the third data can be written into the first plurality of storage cells 122. By analogy, while the third data is read out from the first plurality of storage cells 122, new data can be written into the second plurality of storage cells 124.

[0056] In the case where the storage module 120 of the transposition circuit 200 includes both the first plurality of storage cells 122 and the second plurality of storage cells 124, each write process (a cycle with an odd number such as the first cycle) requires M cycles, and each read process (a cycle with an even number such as the second cycle) requires N cycles. Each cycle can include MAX (N, M) cycles (the MAX function is used to take the maximum value of N and M). By repeating the write process and the read process alternately in this way, a transposition result of a two-dimensional data can be obtained in each cycle (MAX (N, M) cycles). Therefore, compared with the transposition circuit 100, the transposition circuit 200 can have an improved data throughput. In addition, compared with the transposition circuit 10, the transposition circuit 200 can have a considerable data throughput.

[0057] It can be understood that when N is equal to M, the number of cycles required for the writing process and the reading process is the same, so each cycle can include N cycles, and in each cycle of the N cycles, the writing of the corresponding column of storage cells 122 and the reading of the corresponding row of storage cells 124 can be performed simultaneously, or the reading of the corresponding row of storage cells 122 and the writing of the corresponding column of storage cells 124 can be performed simultaneously. When N is not equal to M, for example, assuming that N is greater than M, each cycle can include N cycles, and in each cycle of the N cycles, the reading of the corresponding row of storage cells 122 can be performed, and in each cycle of the selected M cycles among the N cycles, the writing of the corresponding column of storage cells 124 can be performed, or in each cycle of the N cycles, the reading of the corresponding row of storage cells 124 can be performed, and in each cycle of the selected M cycles among the N cycles, the writing of the corresponding column of storage cells 122 can be performed. The case where N is less than M is similar, and will not be repeated here.

[0058] In addition, even when fully loaded (i.e., each cycle receives new data to be transposed), the transposition circuit 200 has at most one column of storage cells 122 or 124 undergoing data flipping in each cycle of each cycle. Such a low flipping rate results in low dynamic power consumption, especially lower than the dynamic power consumption of the transposition circuit 10 in which all registers undergo data flipping in each cycle of each cycle. In addition, when used as transposition units of the same specification, even if the number of storage cells in the transposition circuit 200 is twice the number of registers in the transposition circuit 10, since the storage cells in the transposition circuit 200 do not need to be implemented as registers, but circuit elements (such as latch units) with the smallest possible area that meet the storage function can be used, the transposition circuit 200 still has a large area advantage compared to the transposition circuit 10.

[0059] exist Figure 3 In an embodiment, the first plurality of storage cells 122 and the second plurality of storage cells 124 share the same input module 110. This can advantageously save circuit area. In some embodiments, the input module 110 can also include a first input module separately provided for the first plurality of storage cells 122 and a second input module separately provided for the second plurality of storage cells 124. In the case where the first input module is configured as a column input module as described above with respect to the input module 110, the second input module can be configured as a column input module or as a row input module. That is, the first plurality of storage cells 122 and the second plurality of storage cells 124 can both be used to perform the conversion from column input to row output, or one can be used to perform the conversion from column input to row output and the other can be used to perform the conversion from row input to column output. In the latter case, the corresponding modules of the circuit can be adaptively adjusted, which will not be described in detail here.

[0060] In some embodiments, the selection module 130 of the transposition circuit 200 may include a multiplexer combination having 2N input terminals and 1 output terminal, each of the 2N input terminals being connected to a corresponding row of memory cells in the N rows of memory cells of the first plurality of memory cells and the N rows of memory cells of the second plurality of memory cells 124, and the 1 output terminal being connected to the output module 140. Similar to before, when a 2N to 1 multiplexer is available, the 2N to 1 multiplexer may be used directly. A larger-scale multiplexing function may also be implemented by a cascade arrangement of multiple smaller-scale multiplexers, especially when a 2N to 1 multiplexer may be difficult to obtain.

[0061] Further, the selection module 130 of the transposition circuit 200 may include first to third selection submodules. The first selection submodule may include a first multiplexer combination having N input terminals and y output terminals, where y is an integer and 0<y<N. Each of the N input terminals of the first multiplexer combination may be connected to a corresponding row of storage cells in the x row storage cells of the first plurality of storage cells 122 and the Nx row storage cells of the second plurality of storage cells 124, where x is an integer and 0≤x≤N. The second selection submodule may include a second multiplexer combination having N input terminals and z output terminals, where z is an integer and 0<z<N. Each of the N input terminals of the second multiplexer combination is connected to a corresponding row of storage cells in the remaining Nx row storage cells of the first plurality of storage cells 122 and the remaining x row storage cells of the second plurality of storage cells. The third selection submodule may include a third multiplexer combination having y+z input terminals and 1 output terminal. The y output terminals of the first multiplexer combination and the z output terminals of the second multiplexer combination can be respectively connected to corresponding input terminals among the y+z input terminals of the third multiplexer combination, and 1 output terminal of the third multiplexer combination can be connected to the output module 140.

[0062] In some embodiments, x is equal to 0 or N. In this case, one of the first selection submodule and the second selection submodule is specifically used to control the sequential output of data in the first plurality of storage units 122, and the other of the first selection submodule and the second selection submodule is specifically used to control the sequential output of data in the second plurality of storage units 124, so that the operation of the first plurality of storage units 122 can be decoupled from the operation of the second plurality of storage units 124. For example, Figure 4An example implementation 130A of the selection module 130 is shown, in which the first selection submodule 132 is implemented as a 4-to-1 multiplexer (MUX 4-1) and is used to selectively output data read from a row of storage cells 122 in the first plurality of storage cells 122, the second selection submodule 134 is also implemented as a 4-to-1 multiplexer (MUX 4-1) and is used to selectively output data read from a row of storage cells 124 in the second plurality of storage cells 124, and the third selection submodule 136 is implemented as a 2-to-1 multiplexer (MUX 2-1) and is used to selectively output the output of one of the first selection submodule 132 and the second selection submodule 134. Specifically, refer to Figure 4 The first input end of the first selection submodule 132 is connected to the first row storage units 1221, 1222, 1223, 1224 of the first plurality of storage units 122, the second input end is connected to the second row storage units 1225, 1226, 1227, 1228, and the third input end is connected to the third row storage units 1229, 122 10 , 122 11 , 122 12 , the fourth input terminal is connected to the fourth row storage unit 122 13 , 122 14 , 122 15 , 122 16 , and the output end is connected to an input end of the third selection submodule 136. In addition, the first input end of the second selection submodule 134 is connected to the first row storage units 1241, 1242, 1243, 1244 of the second plurality of storage units 124, the second input end is connected to the second row storage units 1245, 1246, 1247, 1248, and the third input end is connected to the third row storage units 1249, 124 10 , 124 11 , 124 12 , the fourth input terminal is connected to the fourth row storage unit 124 13 , 124 14 , 124 15 , 124 16 , and the output end is connected to another input end of the third selection submodule 136. Figure 4 In the example shown, y=z=1, but this is not restrictive, and y and z may not be equal to 1, as long as a single output terminal is finally achieved through the third selection submodule 136 .

[0063] In other embodiments, x is not equal to 0 or N. In such a case, the first selection submodule and the second selection submodule each receive data read from one or more rows of memory cells 122 in the first plurality of memory cells 122, and also receive data read from one or more rows of memory cells 124 in the second plurality of memory cells 124. Since the readout process of the first plurality of memory cells 122 and the readout process of the second plurality of memory cells 124 do not occur at the same time, this configuration can also operate correctly.

[0064] In some examples, x=y=z=N / 2. For example, the first multiplexer combination may include N / 2 2-to-1 multiplexers, each 2-to-1 multiplexer having a first input connected to a corresponding row of memory cells 122 in the x rows of memory cells 122 of the first plurality of memory cells 122 and a second input connected to a corresponding row of memory cells 124 in the Nx rows of memory cells 124 of the second plurality of memory cells 124. The second multiplexer combination may also include N / 2 2-to-1 multiplexers, each 2-to-1 multiplexer having a first input connected to a corresponding row of memory cells 122 in the remaining Nx rows of memory cells 122 of the first plurality of memory cells 122 and a second input connected to a corresponding row of memory cells 124 in the remaining x rows of memory cells 124 of the second plurality of memory cells 124. For example, Figure 5 Another example implementation 130B of the selection module 130 is shown. The first selection submodule 132 is implemented as two 2-to-1 multiplexers (MUX 2-1), one of the 2-to-1 multiplexers being used to selectively output data read from a first row of storage cells 122 (e.g., storage cells 1221, 1222, 1223, 1224 as shown) in the first plurality of storage cells 122 or data read from a first row of storage cells 124 (e.g., storage cells 1241, 1242, 1243, 1244 as shown) in the second plurality of storage cells 124, and the other 2-to-1 multiplexer being used to selectively output data read from a second row of storage cells 122 (e.g., storage cells 1225, 1226, 1227, 1228 as shown) in the first plurality of storage cells 122 or data read from a second row of storage cells 124 (e.g., storage cells 1245, 1246, 1247, 1248 as shown) in the second plurality of storage cells 124. The second selection submodule 134 is also implemented as two 2-to-1 multiplexers (MUX 2-1), wherein one of the 2-to-1 multiplexers is used to selectively output the third row of storage cells 122 (eg, storage cells 1229, 122 as shown in FIG. 1 ) from the first plurality of storage cells 122. 10 , 122 11 , 122 12) or data read from a third row of memory cells 124 in the second plurality of memory cells 124 (eg, memory cells 1249, 124 as shown in FIG. 1 ). 10 , 124 11 , 124 12 ), and another 2-to-1 multiplexer is used to selectively output the data read from a fourth row of memory cells 122 in the first plurality of memory cells 122 (eg, memory cells 122 as shown in FIG. 1 ). 13 , 122 14 , 122 15 , 122 16 ) or from a fourth row of memory cells 124 in the second plurality of memory cells 124 (eg, memory cells 124 as shown in FIG. 1 ). 13 , 124 14 , 124 15 , 124 16 ). The third selection submodule 136 is implemented as a 4-to-1 multiplexer (MUX 4-1) and is used to selectively output the output of one of the 2-to-1 multiplexers of the first selection submodule 132 and the second selection submodule 134. Figure 5 In the example shown, y=z=2, but this is not restrictive, and y and z may not be equal to 2, as long as a single output terminal is finally achieved through the third selection submodule 136 .

[0065] It can be understood that the above implementation of dividing the selection module 130 into the first to third selection submodules is a division in terms of logical functions, which is exemplary and not restrictive. Other suitable division methods are also feasible.

[0066] To further explain the write logic and read logic of the transposition circuit 200, Figure 6 A non-limiting example implementation of the data write portion of the transposition circuit 200 is shown, and Figure 7 and Figure 8 Various non-limiting example implementations of the data readout portion of transpose circuit 200 are shown.

[0067] like Figure 6As shown, each long horizontal frame represents a column of storage cells. A first trigger DFF1 is arranged upstream of these storage cells, which is configured to output each column of received data to a corresponding column of storage cells based on the received clock signal. The first trigger DFF1 can be always enabled, and its function is to cut off the external timing and ensure the internal timing, rather than to control the selective writing of data to a specific storage cell. A column of data received via the first trigger DFF1 can be written to a corresponding column of storage cells in the eight columns of storage cells of the storage module 120 of the transposition circuit 200 according to corresponding control information (for example, by controlling the signal flip at the clock control end of the storage cell, etc.). A column of data can be written in each cycle, and only at most one column of storage cells generates data flip in each cycle.

[0068] like Figure 7 and Figure 8 As shown, each long horizontal bar represents a row of storage cells. A plurality of 2-to-1 multiplexers are cascaded together to provide a selection from 8 inputs to 1 output. A second flip-flop DFF2 is arranged downstream of these multiplexers, which is configured to output the received data read out from each row of storage cells based on the received clock signal. The second flip-flop DFF2 can be always enabled, and its function is to cut off the external timing and ensure the internal timing, rather than to control the selective reading of data from a specific storage cell. According to the corresponding control information (for example, through a selection signal, etc.), these multiplexers are used to read a row of data from a corresponding row of storage cells in the eight rows of storage cells of the storage module 120 of the transposition circuit 200, and output via the second flip-flop DFF2. At most one row of data can be read out in each cycle, and the read operation will not cause data flipping in the storage cell. Figure 7 and Figure 8 The difference is that in Figure 7 The readout of each row of storage cells 122 and the readout of each row of storage cells 124 are decoupled from each other.

[0069] Accordingly, the present disclosure also provides a transposition method. Fig. 9 FIG. 3 shows a transposition method 300 according to some embodiments of the present disclosure. Fig. 9As shown, the transposition method 300 includes: in step S302, receiving N rows×M columns of first data and writing each column of the first data into a corresponding column of storage cells in a first plurality of storage cells of N rows×M columns in a corresponding cycle of the first cycle; in step S304, outputting the data read out from each row of storage cells in the first plurality of storage cells in a corresponding cycle of the second cycle after the first cycle, and receiving N rows×M columns of second data and writing each column of the second data into a corresponding column of storage cells in a second plurality of storage cells of N rows×M columns in a corresponding cycle of the second cycle; in step S306, outputting the data read out from each row of storage cells in the second plurality of storage cells in a corresponding cycle of the third cycle after the second cycle, wherein N and M are positive integers and at least one of N and M is greater than 1.

[0070] In some embodiments, step S306 further includes receiving N rows×M columns of third data and writing each column of the third data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of the third cycle. In some embodiments, the transposition method 300 further includes outputting the data read from each row of storage cells in the first plurality of storage cells in a corresponding cycle of a fourth cycle after the third cycle. Various embodiments of the transposition method 300 can be similar to the various embodiments described above with respect to the transposition circuit, and will not be described in detail herein.

[0071] On the other hand, the present disclosure further provides a two-dimensional discrete cosine transform device, which includes the transposition circuit according to any embodiment of the present disclosure, wherein N is equal to M.

[0072] The present disclosure further provides a processor in another aspect, which includes the transposition circuit according to any embodiment of the present disclosure or the two-dimensional discrete cosine transform device according to any embodiment of the present disclosure. For example, such a processor can be a neural network processor, a central processing unit, a coprocessor, a digital signal processor, an image processor, a video processor, a dedicated instruction processor, and other processors.

[0073] The present disclosure also provides a computing device in another aspect, which includes the transposition circuit according to any embodiment of the present disclosure or the two-dimensional discrete cosine transform device according to any embodiment of the present disclosure or the processor according to any embodiment of the present disclosure. Examples of such computing devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, etc. Examples of computing devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, peripheral devices, clocks, etc. In addition, computing devices may include incomplete products.

[0074] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words used in this way are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0075] In the specification and claims, when an element is referred to as being "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is located above or below an adjacent feature.

[0076] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly copied. Any implementation described as exemplary herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be limited by any expressed or implied theory given in the technical field, background, summary, or detailed description.

[0077] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0078] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0079] It should also be understood that the term "including / comprising" when used herein indicates the presence of the indicated features, integral bodies, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, units and / or components and / or combinations thereof. In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc.

[0080] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0081] The same or similar parts between the various embodiments of the present disclosure can refer to each other, and each embodiment focuses on the differences from other embodiments. In the description of the present disclosure, the description of reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", "exemplary", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present disclosure and the features of the different embodiments or examples without contradiction.

[0082] In addition, when used in the present disclosure, the words "herein," "above," "below," "herein," "herein below," "herein," "above," and words of similar meaning shall refer to the present disclosure as a whole rather than to any particular portion of the present disclosure. Furthermore, unless expressly stated otherwise or understood otherwise in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to express that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0083] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0084] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A transposition circuit, comprising: An input module is configured to receive N rows×M columns of first data; a storage module connected to the input module and comprising a first plurality of storage cells of N rows×M columns, wherein the storage module is configured to write each column of the first data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of the first cycle; a selection module connected to the storage module and configured to output data read from each row of storage cells in the first plurality of storage cells in a corresponding one cycle of a second cycle after the first cycle; an output module connected to the selection module and configured to output the data received from the selection module as the transposed first data, Wherein, N and M are positive integers and at least one of N and M is greater than 1.

2. The transposition circuit according to claim 1, wherein: The selection module comprises a multiplexer combination having N input terminals and 1 output terminal, each of the N input terminals being connected to a corresponding row of storage cells in the first plurality of storage cells, and the 1 output terminal being connected to the output module.

3. The transposition circuit according to claim 1, wherein: The input module is further configured to receive N rows×M columns of second data, and the storage module further includes a second plurality of storage cells of N rows×M columns and is configured to write each column of the second data into a corresponding column of storage cells in the second plurality of storage cells in a corresponding cycle of the second cycle, The selection module is further configured to output the data read from each row of storage cells in the second plurality of storage cells in a corresponding cycle of a third cycle after the second cycle, The output module is further configured to output the data received from the selection module as transposed second data.

4. The transposition circuit according to claim 3, wherein: The input module is further configured to receive third data of N rows×M columns, The storage module is further configured to write each column of the third data into a corresponding column of storage cells in the first plurality of storage cells in a corresponding cycle of the third cycle. The selection module is further configured to output the data read out from each row of memory cells in the first plurality of memory cells in a corresponding one cycle of a fourth cycle after the third cycle, The output module is further configured to output the data received from the selection module as transposed third data.

5. The transposition circuit according to claim 3, wherein: The selection module includes a multiplexer combination having 2N input terminals and 1 output terminal, each of the 2N input terminals is connected to a corresponding row of storage cells in the N rows of storage cells of the first plurality of storage cells and the N rows of storage cells of the second plurality of storage cells, and the 1 output terminal is connected to the output module.

6. The transposition circuit according to claim 5, wherein: The selection module comprises: A first selection submodule includes a first multiplexer combination having N input terminals and y output terminals, each of the N input terminals of the first multiplexer combination being connected to a corresponding row of storage cells in the x rows of storage cells of the first plurality of storage cells and the Nx rows of storage cells of the second plurality of storage cells; a second selection submodule, comprising a second multiplexer combination having N input terminals and z output terminals, each of the N input terminals of the second multiplexer combination being connected to a corresponding row of storage cells among the remaining Nx rows of storage cells of the first plurality of storage cells and the remaining x rows of storage cells of the second plurality of storage cells; The third selection submodule comprises a third multiplexer combination having y+z input terminals and one output terminal, wherein the y output terminals of the first multiplexer combination and the z output terminals of the second multiplexer combination are respectively connected to corresponding input terminals among the y+z input terminals of the third multiplexer combination, and the one output terminal of the third multiplexer combination is connected to the output module. Wherein, x is an integer and 0≤x≤N, y is an integer and 0<y<N, and z is an integer and 0<z<N.

7. The transposition circuit according to claim 6, wherein: x=0 or N, y=z=1.

8. The transposition circuit according to claim 6, wherein: x=y=z=N / 2, and where The first multiplexer combination includes N / 2 2-to-1 multiplexers, each 2-to-1 multiplexer having a first input connected to a corresponding row of memory cells in the x rows of memory cells in the first plurality of memory cells and a second input connected to a corresponding row of memory cells in the Nx rows of memory cells in the second plurality of memory cells, and The second multiplexer combination includes N / 2 2-to-1 multiplexers, and a first input end of each 2-to-1 multiplexer is connected to a corresponding row of storage cells among the remaining Nx rows of storage cells of the first plurality of storage cells and a second input end is connected to a corresponding row of storage cells among the remaining x rows of storage cells of the second plurality of storage cells.

9. The transposition circuit according to any one of claims 1 to 8, wherein: The input module includes a first trigger, wherein the first trigger is configured to output each column of received data to a corresponding column of storage units based on a received clock signal; and / or The output module includes a second flip-flop configured to output the received data read out from each row of memory cells based on the received clock signal.

10. The transposition circuit according to any one of claims 1 to 8, wherein: The storage unit includes: a latch unit; or Dynamic random access memory DRAM cell; or Static Random Access Memory SRAM cell.

11. The transposition circuit according to any one of claims 1 to 8, wherein: N is equal to M.

12. The transposition circuit according to any one of claims 1 to 8, wherein: The data is image data. 13 . A two-dimensional discrete cosine transform device, comprising a transposition circuit according to claim 1 , wherein N is equal to M.

14. A processor comprising the transposition circuit according to any one of claims 1 to 12 or the two-dimensional discrete cosine transform device according to claim 13.

15. A computing device, comprising the transposition circuit according to any one of claims 1 to 12, the two-dimensional discrete cosine transform device according to claim 13, or the processor according to claim 14.

16. A transposition method, comprising: Receive N rows×M columns of first data and write each column of the first data into a corresponding column of storage cells in a corresponding cycle of a first cycle among the N rows×M columns of first storage cells; Outputting the data read from each row of memory cells in the first plurality of memory cells in a corresponding cycle of a second cycle after the first cycle, and receiving N rows×M columns of second data and writing each column of the second data into a corresponding column of memory cells in the N rows×M columns of the second plurality of memory cells in a corresponding cycle of the second cycle; outputting the data read out from each row of memory cells in the second plurality of memory cells in a corresponding one cycle of a third cycle after the second cycle, Wherein, N and M are positive integers and at least one of N and M is greater than 1.

17. The transposition method according to claim 16, further comprising: receiving N rows×M columns of third data and writing each column of the third data into a corresponding column of storage cells in a corresponding cycle of the third cycle; The data read out from each row of memory cells in the first plurality of memory cells are outputted in a corresponding one cycle of a fourth cycle after the third cycle.

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