Apparatus and method for row hammer counter initialization

Abstract

The embodiment of the invention relates to equipment and a method for row hammer counter initialization. Repeated accesses to aggressor word lines may cause increased data degradation in nearby victim word lines of the memory. An access count value for a given word line may be stored in a counter memory cell positioned along that word line. The count value may be initialized randomly or pseudo-randomly. In some examples, a memory device may initialize the counter memory cell with residual charge present on the counter memory cell during startup. In some other examples, a memory device may initialize the counter memory cell with a threshold voltage compensation VtC setting at boot-up. In some other examples, a memory device may initialize the counter memory cell with a combination of the residual charge present on the counter memory cell and a VtC setting at startup.

Description

Technical Field

[0001] The present application relates to a device and method for initializing a row hammer counter. Background Art

[0002] Information may be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of the memory. The memory may be volatile memory, and the physical signals may decay over time (which may degrade or destroy the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells, for example by rewriting the information to restore the physical signals to the initial values.

[0003] As the size of memory components decreases, the density of memory cells increases greatly.Repeated accesses to a particular memory cell or group of memory cells, often referred to as 'row hammering', can cause an increased rate of degradation of data in nearby memory cells. Summary of the invention

[0004] An embodiment of the present disclosure provides an apparatus comprising: a first digit line; a first word line; and a first memory cell coupled to the first digit line and the first word line, wherein the first memory cell is configured to store a first value, and wherein the first value is generated at least in part based on a first residual charge in the first memory cell.

[0005] Another embodiment of the present disclosure provides a device comprising: a first digital line; a first word line; a threshold voltage compensation sense amplifier coupled to the first digital line; and a first memory cell coupled to the first digital line and the first word line, wherein the first memory cell is configured to store a first value based at least in part on a random or pseudo-random threshold voltage compensation pulse width.

[0006] Yet another embodiment of the present disclosure provides a method for initializing a counter memory cell of a memory device, comprising: powering on the memory device; and initializing the counter memory cell with a value based at least in part on a residual charge of the counter memory cell of the memory device.

[0007] Yet another embodiment of the present disclosure provides a method for initializing a counter memory cell of a memory device, comprising: powering on the memory device; and initializing the counter memory cell of the memory device with a value based at least in part on a random or pseudo-random threshold voltage compensation pulse width of a threshold voltage compensation sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a block diagram of a memory cell array according to an embodiment of the present disclosure.

[0010] Figure 3 is a block diagram of a refresh address control circuit according to an embodiment of the present disclosure.

[0011] Figure 4 is a schematic diagram of a memory system according to an embodiment of the present disclosure.

[0012] Figure 5 is a schematic diagram of a memory system according to an embodiment of the present disclosure.

[0013] Figure 6a and 6b is a timing diagram according to an embodiment of the present disclosure.

[0014] Figure 7 is a block diagram of a sense amplifier threshold voltage compensation pulse width system according to an embodiment of the present disclosure.

[0015] Figure 8 is a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.

[0016] Fig. 9 is a timing diagram according to an embodiment of the present disclosure.

[0017] Fig.10a , 10b 10c are timing diagrams according to an embodiment of the present disclosure.

[0018] Fig.11 A memory system according to an embodiment of the present disclosure.

[0019] Fig.12a , 12b and 12c are flow charts according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and show in an illustrative manner the specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, when certain features will be apparent to those skilled in the art, the detailed description of the features will not be discussed to avoid blurring the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0021] Information in a volatile memory device may be stored in a memory cell (e.g., as a charge on a capacitive element) and may decay over time. The memory cells may be organized into rows (word lines) and columns (bit lines), and the memory cells may be accessed on a row-by-row basis. As part of an auto-refresh operation, the memory cells may also be periodically refreshed on a row-by-row basis, where information along the row is restored to prevent data loss due to decay over time (e.g., the memory cell may be restored to an initial charge value associated with a logic level stored in that memory cell). Repeated access to a particular memory row (e.g., an aggressor row) may cause an increase in the decay rate of an adjacent row (e.g., a victim row) due to, for example, electromagnetic coupling between rows. The aggressor row may decay faster than the timing of the auto-refresh operation. To prevent information loss, it may be desirable to identify the aggressor row so that the corresponding victim row may be refreshed as part of a target refresh operation.

[0022] The aggressor row may be determined based on one or more of the number of accesses to the row, the rate at which the row is accessed, and / or the length of time the row is accessed.To prevent missed row hammering, it may be desirable to track accesses to each row of a memory device.

[0023] There are some techniques for managing row access counts. Each row of memory may include several memory cells that store the access counts of the rows in which they are located. These memory cells may generally be referred to as counter memory cells. In some embodiments of the present disclosure, the counter memory cells are additional memory cells as memory cells in the memory rows. In some embodiments of the present disclosure, the counter memory cells are included in the memory cells of the memory rows. Individual counter memory cells of a given row may store bits that together represent the access count of that row. When a row is accessed, the counter memory cells may be read to the counter circuit. The counter circuit may check the value of the count. If the value of the count is lower than (or equal to) a threshold, the value of the count may be changed (e.g., incremented), and the changed value may be written back to the counter memory cell of the accessed row. If the value of the count is higher than a threshold, a control signal indicating that the row currently accessed is an aggressor row may be provided. The value of the count may then be reset, and the reset value may be written back to the counter memory cell. Based on the control signal, the memory device can determine the location of one or more victim rows associated with an aggressor row (e.g., a currently accessed row) and perform a targeted refresh on the victim rows (and / or queue the aggressor rows for a later targeted refresh operation). By storing the access count on the row associated with the access count, improved reliability and / or speed of access tracking may be achieved.

[0024] However, in some scenarios, it may be possible to know the value of the count. For example, at computer startup, the value of the count may be initialized to zero, since no access to any row has occurred yet. If the threshold is known, then one may be able to track the count of a row to cause damage to the row. For example, a malicious user may be able to continuously generate queue overflows by activating multiple rows in sequence, thereby causing performance degradation of the memory system.

[0025] The present disclosure relates to apparatus, systems, and methods for initializing a counter memory cell with a random or pseudo-random count value. In some examples, a memory device may initialize a counter memory cell with an initial charge (e.g., a residual charge) present on the counter memory cell during startup. In some other examples, a memory device may initialize a counter memory cell with a threshold voltage compensation (VtC) setting at startup. In some other examples, a memory device may initialize a counter memory cell with a combination of an initial charge present on the counter memory cell and a VtC setting at startup.

[0026] Figure 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0027] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present disclosure, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes multiple word lines WL (rows), multiple bit lines BL (columns), and multiple memory cells MC arranged at the intersection of the multiple word lines WL and the multiple bit lines BL. Some memory cells MC along the word lines may be counter memory cells 126. The counter memory cells 126 may be located at the intersection of the counter bit lines and the word lines. There may be multiple counter memory cells 126 along a given word line, and the values ​​stored in the counter memory cells 126 may collectively represent the corresponding access counts XCount of the word lines. The data bus associated with the counter memory cells 126 may be coupled to the refresh address control circuit 116. In some embodiments of the present disclosure, the data bus associated with the counter memory cells 126 may be separated from the data bus that couples other memory cells to the IO circuit 122.

[0028] The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit line BL is coupled to a corresponding sense amplifier (SAMP). The read data from the bit line BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through the complementary local data line (LIOT / B), the transfer gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG and the complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL. Information can generally be read from and written to the counter memory cell 126 in a similar manner, except that the data in the counter memory cell 126 is read and written by the refresh address control circuit 116.

[0029] The semiconductor device 100 may employ a plurality of external terminals including a command and address (CA) terminal coupled to a command and address bus to receive a command and address and a CS signal, a clock terminal for receiving clocks CK_t and CK_c, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, and VDDQ.

[0030] The clock terminal is supplied with external clocks CK_t and CK_c provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, to the data receiver to time the reception of the write data.

[0031] The CA terminal may be supplied with a memory address. The memory address supplied to the CA terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate a memory bank of the memory array 118 containing the decoded row address XADD and the column address YADD. The CA terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the (several) memory cells to be accessed.

[0032] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuits to decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal to select a word line and a column command signal to select a bit line.

[0033] The device 100 may receive an access command as a row activation command ACT. When the row activation command ACT is received, the bank address BADD and the row address XADD are supplied in time with the row activation command ACT.

[0034] The device 100 can receive an access command as a read command. When the read command is received, the column address YADD is supplied together with the read command in time, and the read data is read out from the memory cell corresponding to the row address XADD and the column address YADD in the memory array 118. The read command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the read data from the memory array 118 is provided to the read / write amplifier 120. The read data is output to the outside from the data terminal DQ via the input / output circuit 122. The access count XCount stored in the counter memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value XCount' of the access count is written back to the counter memory cell 126 of the row XADD.

[0035] The device 100 can receive an access command as a write command. When the write command is received, the column address YADD is supplied in time with the write command, and the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. The write clock can also be provided to the external clock terminal to time the data receiver of the input / output circuit 122 to receive the write data. The write data is supplied to the read / write amplifier 120 via the input / output circuit 122, and is supplied to the memory array 118 through the read / write amplifier 120 to be written into the memory cell MC. Similar to the read operation described above, the access count XCount stored in the counter memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value XCount' of the access count is written back to the counter memory cell 126 of the row XADD.

[0036] The device 100 may also receive a command that causes it to perform an automatic refresh operation. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating an automatic refresh command. In some embodiments, the automatic refresh command may be issued to the memory device 100 from the outside. In some embodiments, the automatic refresh command may be periodically generated by a component of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be activated once immediately after the command is input, and may thereafter be cyclically activated at the desired internal timing. Therefore, the refresh operation may continue automatically. The self-refresh exit command may stop the automatic activation of the refresh signal AREF and return to an idle state.

[0037] The refresh signal AREF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, and the row decoder 108 can refresh the word line WL indicated by the refresh row address RXADD. The refresh address control circuit 116 can control the timing of the refresh operation, and can generate and provide the refresh address RXADD. The refresh address control circuit 116 can be controlled to change the details of the refresh address RXADD (e.g., how to calculate the refresh address, the timing of the refresh address), or can operate based on internal logic.

[0038] The refresh address control circuit 116 may selectively output a target refresh address (e.g., a victim address) or an auto-refresh address (auto-refresh address) as the refresh address RXADD. The auto-refresh address may be an address sequence provided based on activation of the auto-refresh signal AREF. The refresh address control circuit 116 may cycle through the auto-refresh address sequence at a rate determined by AREF. In some embodiments, the auto-refresh address sequence may include all addresses in the memory bank 118. In some embodiments, the auto-refresh signal AREF may be issued at a frequency such that most or all addresses in the memory bank 118 are refreshed within a certain period, which period may be based on an expected rate of information decay in the memory cells MC.

[0039] The refresh address control circuit 116 may also determine a target refresh address, which is an address that needs to be refreshed (e.g., a victim address corresponding to a victim row), based on access patterns of nearby addresses in the memory array 118 (e.g., an aggressor address associated with an aggressor row). The refresh address control circuit 116 may monitor accesses to different word lines WL of a memory bank. When the row decoder 108 sends an access command to a particular row, the counter memory cells 126 along that row may read their information as an access count XCount to the refresh address control circuit 116. The refresh address control circuit 116 may determine the access count of the row based on the value stored in the counter memory cell 126 of the accessed row.

[0040] The refresh address control circuit 116 may determine whether the accessed row is an aggressor row based on the access count from the counter memory unit 126. If the current row is not an aggressor row, the value of the access count may be changed, and then the refresh address control circuit may write the new value of the access count back to the counter memory unit 126 of the accessed row. If the refresh address control circuit 116 determines that the accessed row is an aggressor, the refresh address control circuit 116 may use the row address XADD of the accessed row to determine one or more victim row addresses and provide the one or more victim row addresses as refresh addresses RXADD as part of the targeted refresh operation. When the accessed row is determined to be an aggressor, the access count XCount associated with that row may be reset (e.g., to a minimum value, such as 0). In some embodiments, the refresh address control circuit 116 may queue the identified aggressor address (e.g., in a register) for later use in the targeted refresh operation.

[0041] The refresh address RXADD may have a timing based on the timing of the refresh signal AREF. The refresh address control circuit 116 may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be issued (e.g., 'stolen') in a time slot that would have been assigned to an auto-refresh address. In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh address control circuit 116 may determine whether to provide a target refresh address, not provide an address during that time slot, or instead provide an auto-refresh address during that time slot.

[0042] The target refresh address may be based on the access characteristics of the row address XADD received from the address decoder 104 over time. For example, the access characteristics may be determined based on the value of the access count XCount stored in the count memory unit 126. The refresh address control circuit 116 may use different methods to calculate the target refresh address based on the row address XADD, which is identified as an aggressor address based on the access count. For example, the refresh address control circuit 116 may determine whether a given row is an aggressor address, and then calculate and provide the address of the victim address corresponding to the aggressor address as the target refresh address. In some embodiments, more than one victim address may correspond to a given aggressor address. In this case, the refresh address control circuit may queue a plurality of target refresh addresses, and when it determines that a target refresh address should be provided, provide the plurality of target refresh addresses sequentially. The refresh address control circuit 116 may provide the target refresh address immediately, or may queue the target refresh address to be provided at a later time (e.g., in the next time slot available for target refresh).

[0043] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminal. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0044] The power supply terminal is also supplied with a power supply potential VDDQ. The power supply potential VDDQ and VSS are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potential VDDQ supplied to the power supply terminal may be the same potential as the power supply potential VDD supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potential VDDQ supplied to the power supply terminal may be a different potential from the power supply potential VDD supplied to the power supply terminal. The power supply potential VDDQ supplied to the power supply terminal is used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0045] Figure 2 2 is a block diagram of a memory cell array according to an embodiment of the present disclosure. The memory cell array 200 may represent a memory array (e.g. Figure 1 2. The memory cell array 200 includes a plurality of word lines WL (rows) and bit lines BL (columns). A row driver 234 is coupled to the rows. A plurality of memory cells MC (such as the example memory cell 230) are located at the intersection of the rows and columns. The memory cells along each of the word lines WL may be a counter memory cell 226. Each of the bit lines BL may be coupled to a respective sense amplifier 232.

[0046] Each of the memory cells MC can store information. In some embodiments, the information can be stored as binary code, and each memory cell MC can store a bit, which can be at a logic high level or a logic low level. The example memory cell 230 shows a specific implementation that can be used to store information bits in some embodiments. Other types of memory cells can be used in other examples. In the example memory cell 230, the capacitive element stores the information bit as a charge. The first charge level can represent a logic high level, and the second charge level can represent a logic low level. One node of the capacitive element is coupled to a reference voltage (e.g., VSS). Another node of the capacitive element is coupled to a switch. In the example memory cell 230, the switch is implemented using a transistor. The activation node of the switch (e.g., the gate of the transistor) is coupled to a word line. The word line WL can be accessed by a row driver 234 that sets a voltage along the word line, so that the switch in the memory cell MC is activated to provide the charge level of the capacitive element (or other bit storage element) to the associated bit line BL.

[0047] Sense amplifier 232 can read or write the value of an information bit along bit line BL to memory cell MC at accessed word line WL. The sense amplifier can convert the signal along the bit line into a signal that can be 'read' by other elements of the memory device (e.g., by amplifying the voltage). The signal on the bit line can be provided to an input / output circuit (e.g., Figure 1 The column selection switch may be an input / output circuit 122 of the embodiment of the present invention, and the column selection switch may be a column selection transistor.

[0048] In an example read operation, when word line WL is accessed, memory cell MC may provide its charge onto coupled bit line BL, which may cause a change in voltage and / or current along bit line BL. Corresponding sense amplifier 232 may determine the logic level of accessed memory cell MC based on the resulting voltage and / or current along bit line BL, and may provide a signal corresponding to the logic level to the input / output circuit through a column select transistor.

[0049] In an example write operation, the sense amplifier 232 may receive a signal from the input / output circuit indicating a logic level to be written to the accessed memory cell. The sense amplifier 232 may provide a voltage and / or current along a coupled bit line BL (e.g., along a bit line having an active column select transistor) at a level corresponding to the logic level to be written. The voltage and / or current along the bit line BL may charge the capacitive element at the intersection of the bit line and the accessed word line to a charge level associated with the written logic level. In this manner, by specifying the accessed row and which bit lines to record data from (and / or which bit lines to write data to), a specific memory cell MC may be accessed during one or more operations of the memory device.

[0050] During an example refresh operation (either targeted refresh or auto-refresh), the word line WL to be refreshed can be read, and then the logic value read from each of the memory cells along that row can be written back to the same memory cell. In this way, the charge level in the refreshed memory cell MC can be restored to the full value associated with the logic level stored in that memory cell.

[0051] Certain memory cells along each of the word lines may be counter memory cells 226. Counter memory cells 226 may be substantially similar to other memory cells of memory array 200. In some embodiments, counter memory cells 226 may be physically identical to other memory cells MC. However, counter memory cells 226 may be coupled to refresh address control circuitry (e.g., Figure 1 The refresh address control circuit 116 is coupled to the memory instead of the input / output circuits of the memory. The refresh address control circuit can read and / or write the value of the access count, which can be stored as a binary number in the counter memory cell 226 for a given word line. In some embodiments, the refresh address control circuit can be in an area local to the counter memory cell 226, and thus the communication between the refresh address control circuit and the counter memory cell 226 can be very fast.

[0052] In some embodiments, the counter memory cells 226 may be organized along specific bit lines of the memory array 200. Thus, there may be a counter bit line (and associated counter sense amplifier 242) coupled to the counter memory cells 226. The counter memory cells 226 may be arranged at the intersection of the counter bit line and the word line. The counter bit line may include a counter select transistor 246 (similar to a column select transistor) that selectively allows data from the counter bit line to be read to the counter of the refresh address control circuit. The counter bit line and the counter sense amplifier 242 may be coupled to the counter of the refresh address control circuit via a data bus. In some embodiments, the counter memory cells 226 may be located along the end of the memory array 200. This may reduce the length of the counter data bus. For example, if there is a certain number n of counter memory cells 226 along each word line, the counter memory cells 226 may be the first n memory cells of the word line, or the last n memory cells of the word line. The SAMPs 232 and 242 may have complementary bit lines and memory cells on opposite sides of the SAMPs 232 and 242, as illustrated.

[0053] For the sake of clarity, Figure 2 Only a few word lines WL and bit lines BL (and their corresponding memory cells MC) are shown in FIG. More word lines WL and bit lines BL may be provided in the memory array of the present disclosure. Similarly, Figure 2Only a single counter bit line of counter memory cells 226 is shown. However, each word line WL may have several counter memory cells 226 based on the expected maximum value of access counts that may need to be stored in the counter memory cells 226. In some embodiments, there may be between 8 and 16 counter memory cells 226 along each word line. More or fewer counter memory cells 226 may be used in other examples.

[0054] Figure 3 3 is a block diagram of RHR control logic 300 according to an embodiment of the present disclosure. The RHR control logic includes RHR activation logic 310 and further includes refresh address control circuitry 320 associated with each memory bank. In some embodiments, part or all of the RHR control logic 300 may be included in the refresh address control circuitry 116 and / or associated with the refresh address control circuitry 116. Figure 1 The refresh address control circuit 320 is shown to represent that in some embodiments, these components may be repeated for each of the banks of memory. For the sake of brevity, the components of only a single bank will be described.

[0055] The RHR activation logic 310 includes an RHR control 312 and a threshold control 314. The RHR control 312 provides an effective RHR activation signal RHR when one or more of the threshold signals overTH1 and overTH2 are effective. The effective overTH1 signal indicates that the access count of the row exceeds the threshold TH1, and the effective overTH2 signal indicates that the access count of the row exceeds the threshold TH2. Exceeding one or more of the thresholds TH1 and / or TH2 may indicate that the row is considered an aggressor row. The effective RHR signal causes a target refresh operation on a row of memory of the memory bank (e.g., a victim row of the memory that is physically adjacent to the aggressor row). The RHR activation logic 310 further includes a threshold control 314 that provides a threshold to the refresh address control circuit 320 of each of the memory banks. Two thresholds may be used in some embodiments of the present disclosure. One of the thresholds may be used to trigger a target refresh for a first set of adjacent victim rows, and the other threshold may be used to trigger a target refresh for a second set of adjacent victim rows. In some embodiments of the present disclosure, a first set of adjacent victim rows may be physically adjacent to an aggressor row (eg, + / - 1) and a second set of adjacent victim rows may be two physical rows away from the aggressor row (eg, + / - 2).

[0056] Each memory bank may be associated with a corresponding refresh address control circuit 320. The refresh address control circuit 320 includes a counter 322, a comparator 324, a read / write control 326, and an address logic 330. When a row of the memory array 340 is accessed, the value of the counter memory cell 342 along that row is read to the counter 322 under the control of the read / write control 326. The counter 322 may determine the value of the access count for that row based on the value read from the counter memory cell 340. The counter 322 may be a count control circuit that may manage the value of the count stored in the counter memory cell 342 (e.g., by reading the original data in the counter memory cell 342 as a value, writing a new value to the counter memory cell 342, etc.). The counter 322 may provide the count value to a threshold comparator 324, which may determine whether the value of the count exceeds one or more of the thresholds TH1 and TH2 (e.g., whether the value is greater than the threshold). The thresholds TH1 and TH2 are provided by the threshold control 314 of the RHR activation logic 310. If the value does not exceed the threshold (e.g., if the value is less than or equal to the threshold), the counter 322 may increment the value of the count and write the incremented count back to the counter memory unit 342 under the control of the read / write control 326. If the value exceeds one or more of the thresholds TH1 and TH2, the current address XADD of the accessed row may be determined to be the aggressor address. When the value of the count exceeds the threshold TH1, the comparator 324 provides a valid threshold signal overTH1, and when the count value exceeds the threshold TH2, the comparator 324 provides a valid threshold signal overTH2. The valid threshold signal overTH1 or overTH2 causes the RHR control 312 to provide a valid RHR activation signal RHR. The valid RHR activation signal RHR causes the address logic 330 of the refresh address control circuit 320 to provide a row address for the target refresh. The current address of the row that has been identified as the aggressor row is stored in the aggressor address register 332 of the address logic 330, and the address of the aggressor row is used by the refresh address generator 334 to provide the address RXADD for the target refresh. In some embodiments of the present disclosure, when the RHR activation signal RHR is valid for exceeding the threshold TH1, the address logic 330 provides the address RXADD for the target refresh of the first set of adjacent victim rows, and when the RHR activation signal RHR is valid for exceeding the threshold TH2, the address logic 330 provides the address RXADD for the target refresh of the second set of adjacent victim rows.

[0057] Figure 4 4 is a schematic diagram of a memory system 400 according to an embodiment of the present disclosure. In some examples, sense amplifier region 405 - a may include SAMP 232 , 242 , or a combination thereof in some embodiments.

[0058] The memory system 400 may include sense amplifier regions 405-a, 405-b, 405-c, memory cells 410-a, memory cells 410-b, digit lines 415-a, digit lines 415-b, word lines 420-a, and word lines 420-b. The term "digit line" may be used interchangeably with the term "bit line." In some cases, digit line 415-a may be a target digit line, and digit line 415-b may be a reference digit line. Memory cells 410-a, 410-b, or both may be counter memory cells that, when taken together or when taken together with additional memory cells, may represent an access count for a given row. Sense amplifier regions 405-a, 405-b, 405-c may each include one or more sense amplifiers. For example, one sense amplifier may correspond to one memory cell on one side of the sense amplifier, and another memory cell on the other side of the sense amplifier (see Figure 5 ).

[0059] Sense amplifier region 405 may include additional sense amplifiers, each coupled to other memory cells 410. In some cases, a word line 420 may activate multiple memory cells 410 to which it is connected. For example, word line 420-a may activate memory cell 410-a, and word line 420-b may activate memory cell 410-b.

[0060] At startup, there may be residual charge stored in memory cells 410-a and 410-b, there may be no charge, or some combination thereof. Different scenarios with memory cells of different charges are further explained in FIG. 6 . Word lines 420-a and 420-b may be activated. The sense amplifiers in sense amplifier region 405-b may sense these voltages, determine which digit line has the larger voltage, and drive the digit line with the larger voltage to a high logic level voltage (e.g., to a supply voltage (e.g., Vdd)) and drive the digit line with the smaller voltage to a low logic level voltage (e.g., to ground). Since word lines 420-a and 420-b are still activated, memory cells 410-a and 410-b coupled to corresponding digit lines 415-a and 415-b are charged to Vdd or ground. Word lines 420-a and 420-b are deactivated, and thus corresponding charges are stored to each memory cell. Depending on which digit line is driven high or low, memory cells 410-a and 410-b now store complementary logic values ​​(eg, 1 and 0).

[0061] In this manner, the initialized values ​​of the memory cells 410-a and 410-b (e.g., counter memory cells that count refreshes) are based on any residual charge remaining on the memory cells (e.g., prior to startup). Thus, the initialized values ​​of the memory cells are random, pseudo-random, substantially random, or arbitrary. Such techniques for initializing the counter memory cells may make it more difficult for a malicious user to determine the counter values ​​of the counter memory cells for a row hammering attack or to cause some other performance degradation in the system (e.g., a waterfall or cascade attack). At least in Figure 5 Further explanation can be found in .

[0062] Figure 5 5 is a schematic diagram of a memory system 500 according to an embodiment of the present disclosure. In some examples, sense amplifier 505 can be included in SAMP 232, 242, sense amplifier region 405, or a combination thereof in some embodiments.

[0063] Memory system 500 may include sense amplifier 505, memory cell 510-a, memory cell 510-b, target digit line 515-a (true), reference digit line 515-b (complementary), word line 520-a, and word line 520-b. Memory cell 510-a may include transistor 525-a and capacitor 530-a, and memory cell 510-b may include transistor 525-b and capacitor 530-b. Memory cells 510-a, 510-b, or both may be counter memory cells that, when taken together or when taken together with additional memory cells, may represent an access count for a given row.

[0064] At startup, there may be residual charge stored in memory cells 510-a and 510-b, there may be no charge, or some combination thereof. Different scenarios for memory cells with different charges are further explained in FIG. 6. Word lines 520-a and 520-b may be activated, and the voltages of corresponding capacitors 530-a and 530-b may be provided to digit lines 515-a and 515-b. Sense amplifier 505 may sense these voltages, determine which digit line has a larger voltage, and drive the digit line with the larger voltage to a high logic level voltage (e.g., to a supply voltage (e.g., Vdd)) and drive the digit line with the smaller voltage to a low logic level voltage (e.g., to ground). Since word lines 520-a and 520-b are still activated, the corresponding capacitors 530-a and 530-b coupled to the corresponding digit lines 515-a and 515-b are charged to Vdd or ground. Word lines 520-a and 520-b are deactivated, and thus corresponding charges are stored to each capacitor. Depending on which digit line is driven high or low, memory cells 510-a and 510-b now store complementary logic values ​​(eg, 1 and 0).

[0065] For example, at startup or just before startup, or during some other time, memory cell 510-a (e.g., capacitor 530-a) may store residual charge, and memory cell 510-b (e.g., capacitor 530-b) may store less residual charge. Such residual charge may be from a previous operation of memory system 500 or from any other operation, including startup and / or initialization. Word line 520-a may be activated, which may activate transistor 525-a. The residual voltage from capacitor 530-a may be provided to digit line 515-a. Sense amplifier 505 may sense the voltage from digit line 515-a. Word line 520-b may be activated, which may activate transistor 525-b. The less residual voltage from capacitor 530-b may be provided to digit line 515-b. Sense amplifier 505 may sense the voltage from digit line 515-b.

[0066] Sense amplifier 505 may amplify the differential voltage between the digit lines based on which digit line has a higher voltage value. In the present example, digit line 515-a has a higher voltage than digit line 515-b, sense amplifier 505 may amplify digit line 515-a higher (e.g., to Vdd) and may drive digit line 515-b lower (e.g., to ground).

[0067] Since word line 520-a is still activated, the amplified voltage on digit line 515-a is provided to capacitor 530-a. Since word line 520-b is still activated, the lower voltage on digit line 515-b is provided to capacitor 530-b. Word lines 520-a and 520-b are deactivated and the corresponding charged voltages on the capacitors are stored. Memory cell 510-a stores a logical '1' and memory cell 510-b stores a logical '0'.

[0068] In this manner, the initialized values ​​of the memory cells 510-a and 510-b (e.g., counter memory cells that count refreshes) are based on any residual charge remaining on the memory cells (e.g., prior to startup). In this manner, the initialized values ​​of the memory cells are random, pseudo-random, substantially random, or arbitrary. Such techniques for initializing the counter memory cells may make it more difficult for a malicious user to determine the counter values ​​of the counter memory cells for a row hammering attack or to cause some other performance degradation in the system (e.g., a waterfall or cascading attack).

[0069] Figure 6a and 6b 600 - a and 600 - b according to an embodiment of the present disclosure. The timing diagrams 600 a and 600 b may represent the timing diagrams according to Figure 4 , 56 . The timing of various processes of the present invention may be described in detail in detail. The timing diagram 600-a may represent a scenario in which the true memory cell has an initial charge that is smaller than the initial charge of the complementary memory cell (or in other words, the initial charge of the complementary memory cell is greater than the initial charge of the true memory cell). The timing diagram 600-b may represent a scenario in which the true memory cell has an initial charge that is larger than the initial charge of the complementary memory cell (or in other words, the initial charge of the true memory cell is greater than the initial charge of the complementary memory cell). Additional potential combinations may be described in FIG. 6 , such as when the two memory cells have the same or similar initial charge, or when the two memory cells have no charge or substantially no charge.

[0070] At startup, there may be residual charge stored in memory cells 510-a and 510-b, there may be no charge, or some combination thereof. Figure 6a In , the residual charge of the true memory cell (e.g., memory cell 510-a) may be less than the residual charge of the complementary memory cell (e.g., memory cell 510-b). Figure 6b In the embodiment of the present invention, the residual charge of the true memory cell (eg, memory cell 510 - a ) may be greater than the residual charge of the complementary memory cell (eg, memory cell 510 - b ).

[0071] Reference Figure 5 Circuit Components Explained Figure 6a Timing diagram of .

[0072] Before word lines 520-a and 520-b are activated at time t1, digit lines 515-a and 515-b may be precharged (in this example, digit line 515-a corresponds to DL_T and digit line 515-b corresponds to DL_F). The voltages in the two memory cells 510-a and 510-b may be their respective charges (e.g., 0 mV and 200 mV, respectively, as shown in FIG. 1 ). Figure 6a). After word lines 520-a and 520-b are activated, the voltages of respective capacitors 530-a and 530-b may be provided to digit lines 515-a and 515-b. As shown between t1 and t2, the voltage DL_T of true digit line 515-a is driven lower than the voltage DL_F of complementary digit line 515-b due to charge sharing. The voltages of memory cell 510-a and digit line 515-a eventually match in voltage, and 510-b and 515-b eventually match in voltage. At t2, sense amplifier 505 is activated via an activation signal (e.g., SAP, SAN), and sense amplifier 505 amplifies the digit line voltage based on the sensed digit line difference due to the voltage difference initially stored in the memory cell. The sense amplifier 505 can sense these voltages, determine which digit line has the larger voltage (e.g., relative to their initial voltage difference before charge sharing, or a larger voltage change indicating a lower charged memory cell), and drive the digit line with the larger voltage (or smaller changed voltage) upward as seen after t2, and drive the digit line with the smaller voltage (or larger changed voltage) downward as seen after t2. For example, at t2, the sense amplifier determines that the true digit line DL_T has a lower voltage than the complementary digit line DL_F, and therefore amplifies this difference after t2.

[0073] Reference Figure 5 Circuit Components Explained Figure 6b Timing diagram of .

[0074] Before word lines 520-a and 520-b are activated at time t1, digit lines 515-a and 515-b may be precharged. The voltages in two memory cells 510-a and 510-b may be their respective charges (e.g., 200 mV and 0 mV, respectively, as shown in FIG. Figure 6b). After word lines 520-a and 520-b are activated, the voltages of respective capacitors 530-a and 530-b may be provided to digit lines 515-a and 515-b. As shown between t1 and t2, the voltage of true digit line DL_T is driven low, but the voltage of complementary digit line DL_F is driven even lower (due to charge sharing) because the complementary digit line has 0 mV while the true digit line has 200 mV. Since the complementary digit line started out higher before t1, the voltages of the true and complementary lines are similar at t2, indicating that the true memory cell has a higher voltage than that of the complementary memory cell. The voltages of memory cell 510-a and digit line 515-a eventually match in voltage, and 510-b and 515-b eventually match in voltage. At t2, sense amplifier 505 is activated via an activation signal (e.g., SAP, SAN), and sense amplifier 505 amplifies the digit line voltages based on the sensed digit line differences due to the voltage differences initially stored in the memory cells. Sense amplifier 505 can sense these voltages, determine which digit line has a larger voltage (e.g., relative to their initial voltage differences before charge sharing, or a larger voltage change downward indicating a lower charged memory cell), and drive the digit line with the larger relative voltage (or smaller changed voltage) upward as seen after t2, and drive the digit line with the smaller voltage (or larger changed voltage) downward as seen after t2. For example, at t2, the sense amplifier determines that the true digit line DL_T has a smaller relative voltage change than the complementary digit line DL_F, and therefore drives DL_T upward.

[0075] In some other examples, both the true memory cell and the complementary memory cell may have the same or similar residual charge or no residual charge. In such examples, the sense amplifier may simply determine which digit line has the larger voltage after charge sharing, and amplify that digit line, and drive the other digit line down. This is because the true and complementary digit lines have some voltage difference even before charge sharing, and since the charges in both the true memory cell and the complementary memory cell are the same or similar or both are zero, this voltage difference does not change when charge sharing occurs. In this case, the digit line that initially has the larger voltage (e.g., just before charge sharing) is driven higher. Figure 6a or before t1 in 6b) will be amplified simply due to the pre-existing voltage difference. In some cases, the true digital line may be the digital line that was initially driven high, rather than Figure 6a and 6b The complementary number lines shown in .

[0076] The initialized values ​​of the memory cells 510-a and 510-b (e.g., counter memory cells that count refreshes) are based on any residual charge remaining on the memory cells (e.g., prior to startup). In this way, the initialized values ​​of the memory cells are random, pseudo-random, substantially random, or arbitrary. The residual charge on the memory cells informs the operation of the sense amplifiers, i.e., by identifying which memory cell holds a larger charge. The sense amplifiers then write a "1" back to the memory cell with the higher residual charge and a "0" back to the memory cell with the lower residual charge. Such techniques for initializing the counter memory cells may make it more difficult for a malicious user to determine the counter value of the counter memory cells for a row hammering attack or cause some other performance degradation in the system (e.g., a waterfall or cascade attack).

[0077] Figure 7 7 is a block diagram of a sense amplifier threshold voltage compensation pulse width system 700 according to an embodiment of the present disclosure. The sense amplifier threshold voltage compensation pulse width system 700 may include a linear feedback shift register (LFSR) 705, a threshold voltage compensation (VtC) pulse width generator circuit 710, and a VtC sense amplifier circuit 715.

[0078] The LFSR 705 may generate a multi-bit (e.g., four-bit) pseudo-random number or a series of values ​​(e.g., in binary). For example, the LFSR 705 may generate 0001, 0011, 0010, 1010, etc. The LFSR 705 may provide the numbers to the VtC pulse width generator circuit 710. The VtC pulse width generator circuit 710 may provide a VtC pulse having a pulse width based on the provided numbers. In some embodiments of the present disclosure, some values ​​from the LFSR 705 may be mapped to a specific VtC pulse width setting. For example, a value of 1000 may correspond to a first VtC pulse width and a value of 0001 may correspond to a second VtC pulse width, wherein the first VtC pulse width is wider than the second VtC pulse width. Other mapping schemes may also be used. The VtC pulse width generator circuit 710 provides an indication of the VtC pulse width to a VtC sense amplifier 715, such as the sense amplifier 505.

[0079] Figure 8 is a schematic diagram of a sense amplifier 800 according to an embodiment of the present disclosure. The sense amplifier 800 may include a threshold voltage compensation sense amplifier. In some embodiments of the present disclosure, the sense amplifier 800 may be included in Figure 7 of the VtC sense amplifier circuit 715.

[0080] The sense amplifier 800 selectively amplifies signals on digital lines DLb and DLa. The sense amplifier 800 includes a pair of ISO switches 810 and 812 (e.g., NMOS switches or isolation transistors). These ISO switches 810 and 812 can be coupled to isolation control signals ISO (not shown), respectively. The sense amplifier 800 includes p-type transistors P1 822 and P2 823 and n-type transistors M1 824 and M2 826. Transistor P1 822 has a node coupled to node ACT, a node coupled to node GutB, and a gate coupled to node GutA. Node GutB can be coupled to bit line DLa through transistor 832, and node GutA can be coupled to bit line DLb through transistor 833. Transistors 832 and 833 are provided with control signals BLCP ( Figure 8 823 has a node coupled to node ACT, a node coupled to node GutA, and a gate coupled to node GutB. Transistor M1 has a node coupled to node GutB, a node coupled to node RNL, and a gate coupled to bit line DLa. Transistor M2 has a node coupled to node GutA, a node coupled to node RNL, and a gate coupled to bit line DLb. During access operations, a supply voltage (e.g., Vdd) is provided to the ACT node and ground is provided to the RNL node to activate sense amplifier 800.

[0081] A first ISO switch 810 is coupled between a bit line DLb and a node GutB. The first ISO switch 810 may act as a switch and may couple the bit line DLb to the node GutB when activated. The first ISO switch 810 may be an n-type transistor. A second ISO switch 812 is coupled between the bit line DLa and the node GutA. When activated, the second ISO switch 812 couples the bit line DLa 806 to the node GutA. The gates of the first ISO switch 810 and the second ISO switch 812 are provided with an ISO signal, which activates the first ISO switch 810 and the second ISO switch 812 when active (e.g., active logic high).

[0082] In operation, the charge state of the activated memory cell is provided to the sense amplifier 800, and when the sense amplifier 800 is activated by providing a supply voltage (e.g., Vdd) to the ACT node and ground to the RNL node, the charge state is amplified, resulting in one of the digit lines DLb or DLa being driven to the supply voltage and the other digit line being driven to ground.

[0083] The driving transistor 850 is coupled to the RNL node and the driving transistor 851 is coupled to the ACT node. When the driving transistor 850 is activated, ground is provided to the RNL node, and when the driving transistor 851 is activated, a supply voltage (e.g., Vdd) is provided to the ACT node. The driving transistors 850 and 851 are activated to activate the sense amplifier during one or more stages of sense amplification (e.g., threshold voltage compensation stage, sense amplifier activation stage). The driving transistor 850 is activated by the control signal 855 and the driving transistor 851 is activated by the control signal 856. The duration of the voltage of the control signal 855 and / or the control signal 856 applied to the gate of the driving transistor 850 and / or the driving transistor 851 may indicate or include the duration of the corresponding stage (e.g., threshold voltage compensation stage, sense amplifier amplification stage). Thus, the phase width is increased or decreased accordingly. In some embodiments of the present disclosure, by widening or shortening the VtC pulse width, the voltage from the VtC pulse width generator (e.g., Figure 7 The output of the VtC pulse width generator circuit 710) can extend or shorten the duration of applying the voltage to the gate of the transistor to activate the drive transistor 850 and / or the drive transistor 851.

[0084] Fig. 9 A timing diagram according to an embodiment of the present invention is described. The timing diagram illustrates Figure 8 A control signal sequence associated with the operation of the threshold voltage compensation (VtC) sense amplifier 800.

[0085] In the initial stage, the control signal BLCP (e.g., coupled to Figure 8 The gates of transistors 832 and 833 in the sense amplifier 800 are at a high logic level, thereby activating transistors 832 and 833 and preparing the sense amplifier 800 for operation. The isolation (ISO) control signal is also at a high logic level to activate ISO switches 810 and 812 to provide a current path between the bit line DLb and the node GutB and to provide a current path between the bit line DLa and the node GutA. Concurrently, the bit line equalization (BLEQ) control signal ( Figure 8 Sense amplifier enable signals (i.e., sense amplifier positive (SAP) and sense amplifier negative (SAN)) are at low and negative logic levels, respectively, indicating that the sense amplifiers are in a deactivated state.

[0086] During the threshold voltage compensation (VtC) phase, the SAP and SAN control signals transition to a high logic level, activating the sense amplifier. The BLCP control signal remains at a high logic level, ensuring that the gates and drains of transistors M1 824 and M2 826 are coupled (e.g., diode connected). The BLEQ control signal transitions to a low logic level, terminating voltage equalization on the bit lines. During this phase, the ISO control signal is at a low logic level, indicating that the bit line DLb is isolated from the node GutB and the bit line DLa is isolated from the node GutA. The VtC phase width (e.g., duration via SAN) may be controlled by a VtC pulse width generator (e.g., Figure 7 The phase width is controlled by a VtC pulse width generator circuit 710, such as by the activation width of a control signal 855 and / or a control signal 856 of the drive transistor 850 and / or the drive transistor 851. As a result of the VtC phase, a compensation voltage may be generated at one or both of the nodes DLb and / or DLa.

[0087] After the post-VtC phase, the BLCP, SAP, ISO, and SAN control signals transition to low logic levels, thereby deactivating the bit line precharge and sense amplifier functions. The BLEQ control signal transitions to a high logic level, thereby facilitating re-equalization of the voltages on the bit lines in preparation for subsequent operation cycles, while nodes GutB and GutA maintain their voltages (e.g., compensation voltages).

[0088] In the final phase, the SAP, ISO, and SAN control signals transition back to high logic levels, activating the sense amplifiers to amplify the voltage difference on the bit lines DLb and DLa. The BLCP and BLEQ control signals remain at low logic levels, indicating that the bit lines are neither precharged nor equalized.

[0089] Fig.10a , 10b 1000-a, 1000-b, and 1000-c may represent timing diagrams according to embodiments of the present disclosure. Figure 8 The timing of various processes related to VtC compensation of a VtC sense amplifier 800) wherein the sense amplifier may be coupled to two complementary memory cells at digit line a and digit line b. Fig.10a , 10b The timing diagrams of 10c and 10d may represent a scenario where the true memory cell and the complementary memory cell have similar residual charges. Fig.10a , 10b 10c and the associated disclosure, the enhanced random or pseudo-random aspects of the embodiments may be at least partially due to, for example, the randomness of the VtC pulse width generator (e.g. Figure 7The random VtC pulse width setting provided by the VtC pulse width generator circuit 710 of FIG. 7A . However, since the residual charge is already essentially random, an additional layer of randomness can be introduced through the present technique.

[0090] Fig.10a Describes a scenario where VtC is undercompensated (e.g., less than 3 nanoseconds in width). Fig.10b The VtC pulse width is shorter than the VtC pulse width of the counter. If the VtC pulse width is too short, the sense amplifier may not have enough time to fully compensate for the threshold voltage mismatch. Therefore, the sense amplifier may not be able to correctly sense and amplify the small voltage difference between the bit lines. This may cause incorrect data to be read from the memory cell, resulting in a read error. However, in the present invention, it is expected that different values ​​are written back to the memory cell to increase the randomness of the initialization of the counter memory cell.

[0091] During the precharge phase before t1, the two bit lines are brought to equal potential (BLCP high) by the bit line precharge circuit. This sets up the bit lines for sensing the small voltage differences caused by the memory cells.

[0092] Activation of the word line at t1 connects the particular memory cell to the bit line.The stored charge in the memory cell (representing a binary "0" or "1") causes a small voltage difference between the bit lines.

[0093] As an example of undercompensated VtC, Fig.10a The VtC phase is not included. In general, if the VtC pulse width is undercompensated (ie, too short), the sense amplifier may not have enough time to properly compensate for the threshold voltage mismatch between the transistors of the sense amplifier. Fig.10a In this case, the width of the VtC pulse is zero.

[0094] At t2, the sense amplifier senses a small voltage difference between the bit lines. Due to undercompensation, the sense amplifier may not accurately amplify this small voltage difference, i.e., a certain degree of randomness may be introduced in the sensing of the memory cell. The bit line that is slightly positive may be driven to a high voltage, and the bit line that is slightly negative (or just not too positive) may be driven to a low voltage. Fig.10a In the case of , the true digit line DL_T is high, so the sense amplifier drives it high. The complementary digit line DL_C is low, so the sense amplifier drives it low.

[0095] Fig.10b Explain that VtC ratio Fig.10aThe example of the VtC pulse width can be more compensated (e.g., compensated at the trip point). For example, the VtC pulse width can be a default width. If the VtC pulse width is the default value, the sense amplifier can have enough time to compensate for the threshold voltage mismatch. Therefore, the sense amplifier can correctly sense and amplify the small voltage difference between the bit lines. In the present invention, it is expected that the correct value is written back to the memory cell to increase the randomness of the initialization of the counter memory cell, because proper compensation is an alternative to under-compensation. As previously discussed, the VtC pulse width can be randomized, for example by Figure 7 The LFSR 705 and the VtC pulse width generator circuit 710 in are randomly selected.

[0096] During the precharge phase before t0, the two bit lines are brought to equal potential (BLCP high) by the bit line precharge circuit. This sets up the bit lines for sensing the small voltage differences caused by the memory cells.

[0097] The sense amplifier enable signals SAP and SAN activate the sense amplifier at the beginning of the VtC compensation phase at t0. The VtC phase begins and the VtC pulse width determines the duration of this phase (from t0 to t1). This is consistent with Fig.10a This contrasts with the apparent lack of a VtC phase in the examples.

[0098] Generally, if the VtC pulse width is compensated, the sense amplifier may have enough time to compensate for the threshold voltage mismatch between the transistors of the sense amplifier.

[0099] Activation of the word line at t1 connects the particular memory cell to the bit line. The stored charge in the memory cell (representing a binary "0" or "1") causes a small voltage difference between the bit lines. The VtC phase also stops at t1.

[0100] At t2, the sense amplifier senses the small voltage difference between the bit lines. The bit line that is slightly more positive may be driven to a high voltage, and the bit line that is slightly more negative (or just not too positive) may be driven to a low voltage. Fig.10b In the case of , the complementary digit line DL_F is high, so the sense amplifier drives it high. The true digit line DL_T is low, so the sense amplifier drives it low.

[0101] Fig.10c Explanation: VtC is overcompensated (for example, the pulse width is greater than Fig.10bIn the present invention, different values ​​are written back to the memory cells to increase the randomness of the initialization of the counter memory cells.

[0102] During the precharge phase before t0, the two bit lines are brought to equal potential (BLCP high) by the bit line precharge circuit. This sets up the bit lines for sensing the small voltage differences caused by the memory cells.

[0103] The sense amplifier enable signals SAP and SAN activate the sense amplifier at the beginning of the VtC phase. The VtC phase begins and the VtC pulse width determines the duration of this phase (from t0 to t1).

[0104] In general, if the VtC pulse width results in an overcompensated VtC (ie, is too long), then the sense amplifier may overcompensate for the threshold voltage mismatch between the transistors of the sense amplifier.

[0105] Activation of the word line at t1 connects the particular memory cell to the bit line. The stored charge in the memory cell (representing a binary "0" or "1") causes a small voltage difference between the bit lines. The VtC phase also stops at t1.

[0106] At t2, the sense amplifier senses a small voltage difference between the bit lines. Due to overcompensation, the sense amplifier may not accurately amplify this small voltage difference, i.e., a degree of randomness may be introduced in the sensing of the memory cell. The bit line that is slightly positive may be driven to a high voltage, and the bit line that is slightly negative (or just not too positive) may be driven to a low voltage. Fig.10c In the case of , the complementary digit line DL_F is high, so the sense amplifier drives it high. The true digit line DL_T is low, so the sense amplifier drives it low.

[0107] Fig.11 A memory system according to an embodiment of the present disclosure is described. Fig.11 Generally describe the combination of Figure 4 6. Related embodiments and Figure 7 to 1 0 related embodiments. That is, two degrees of randomness or pseudo-randomness are combined to achieve highly random initialization of the counter memory cells, making it difficult for malicious users to exploit the memory system for row hammering, waterfall, or cascade attacks. In some examples, the VtC sense amplifier 1105 may include the VtC sense amplifier 800.

[0108] For brevity, Figure 4 To 6 and Figure 7 to 1 0 will not be described in detail. Typically, the VtC sense amplifier 1105 senses the residual charge on the complementary memory cells 1120-a and 1120-b coupled to the corresponding digit lines 1122-a and 1122-b when the word lines 1125-a and 1125-b are activated, and amplifies the charges depending on which charge is larger. In some embodiments of the present disclosure, the memory cells 1120-a and 1120-b may be counter memory cells. Which residual charge will be larger is essentially random.

[0109] Additionally, the VtC sense amplifier 1105 receives a pulse width signal from a VtC pulse width generator 1110. The VtC pulse width generator 1110 generates the pulse width signal based on a pseudo-random generator, such as a LFSR circuit 1115. This adds a second layer of randomness to the generation of random values ​​for the counter memory cells 1120-a and 1120-b.

[0110] Figures 12a to 12c 1200-a, 1200-b, and 1200-c are described with respect to certain steps (e.g., as described in blocks 1210 to 1215, 1220 to 1225, and 1230 to 1235), it will be appreciated that more or fewer steps may be used in other embodiments, or that those steps may be repeated and / or performed in a different order.

[0111] refer to Fig.12a , block 1210 depicts powering up the memory device. In some cases, the memory cells (eg, 510-a, 510-b, 1120-a, 1120-b) may include capacitors that store residual charge (eg, prior to powering up or startup).

[0112] Block 1215 describes initializing a counter memory cell of the memory device with a value based at least in part on a residual charge of a memory cell (e.g., the counter memory cell and / or another memory cell). In some examples, block 1215 may include amplifying the residual charge (e.g., using a sense amplifier such as sense amplifier 505 or 800) and writing a state of the amplified residual charge to the counter memory cell. In some examples, the first residual charge may be from before starting the volatile memory device.

[0113] refer to Figure 12b, block 1220 describes powering on the memory device. Block 1225 may include modifying the threshold voltage compensation pulse width. The resulting state of the memory cell (e.g., the counter memory cell and / or another memory cell) determined by the sense amplifier operation (including the modified threshold voltage compensation pulse width) may be written to the counter memory cell. In some embodiments, the VtC compensation pulse width may be based at least in part on a pseudo-random generator circuit (e.g., a LFSR).

[0114] refer to Fig.12c , block 1230 describes powering on the memory device. Block 1235 describes initializing a counter memory cell of the memory device with a value based at least in part on a combination of a residual charge of a memory cell (e.g., a counter memory cell and / or another memory cell) and a threshold voltage compensation pulse width. The resulting state and modified threshold voltage compensation pulse width determined by sense amplifier operation dependent on the residual charge of the memory cell (and / or another memory cell) may be written to the counter memory cell.

[0115] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes according to the present systems, devices, and methods, or separated and / or performed in a separate device or device portion.

[0116] Finally, the above discussion is intended only to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that one of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: First number line; First word line; and A first memory cell is coupled to the first digit line and the first word line, wherein the first memory cell is configured to store a first value, and wherein the first value is generated based at least in part on a first residual charge in the first memory cell.

2. The device of claim 1, wherein the first residual charge is from before starting the device.

3. The apparatus of claim 1, wherein the first value represents, at least in part, an initial count value of access operations performed on a row of memory cells.

4. The apparatus according to claim 1, further comprising: A sense amplifier is provided, wherein the first value is generated based at least in part on operation of the sense amplifier on the first residual charge.

5. The apparatus of claim 4, wherein the sense amplifier comprises a threshold voltage compensated sense amplifier, the apparatus further comprising: a pseudo-random generator circuit configured to generate a value having a plurality of bits; and a threshold voltage compensated pulse width generator circuit configured to generate a pulse width signal based at least in part on the value from the pseudo-random generator circuit and configured to provide the pulse width signal to the sense amplifier, wherein a duration of a threshold voltage compensation phase of the sense amplifier is based at least in part on the pulse width signal.

6. The apparatus of claim 5, wherein the pseudo-random generator circuit comprises a linear feedback shift register.

7. The apparatus of claim 4, further comprising: a second digital line coupled to the sense amplifier; Second word line; A second memory cell is coupled to the second digit line and the second word line, wherein the second memory cell is configured to store a second value, wherein the second value is complementary to the first value.

8. The apparatus of claim 7, wherein the sense amplifier is configured to compare the first residual charge to a second residual charge on the second memory cell.

9. A device comprising: First number line; First word line; a threshold voltage compensated sense amplifier coupled to the first digit line; and A first memory cell is coupled to the first digit line and the first word line, wherein the first memory cell is configured to store a first value based at least in part on a random or pseudo-random threshold voltage compensated pulse width.

10. The apparatus of claim 9, wherein the first value represents, at least in part, a count of access operations performed on a row of memory cells.

11. The apparatus of claim 9, wherein the first value is generated based at least in part on a first residual charge in the first memory cell.

12. The device of claim 11, wherein the first residual charge is from before starting the device.

13. The apparatus of claim 11, further comprising: Second digital line; a second word line, wherein the sense amplifier is coupled to the second digit line; A second memory cell is coupled to the second digit line and the second word line, wherein the second memory cell is configured to store a second value, wherein the second value is complementary to the first value.

14. The apparatus of claim 13, wherein the threshold voltage compensation sense amplifier is configured to compare the first residual charge to a second residual charge on the second memory cell.

15. The apparatus according to claim 9, further comprising: a pseudo-random generator circuit configured to generate a value having a plurality of bits; and a threshold voltage compensation pulse width generator circuit configured to generate a pulse width signal indicative of the threshold voltage compensation pulse width based at least in part on the value, and configured to provide the pulse width signal to the threshold voltage compensation sense amplifier, wherein a duration of a threshold voltage compensation phase of the threshold voltage compensation sense amplifier is based at least in part on the pulse width signal.

16. The apparatus of claim 15, wherein the pseudo-random generator circuit comprises a linear feedback shift register.

17. A method for initializing a counter memory cell of a memory device, comprising: Powering on the memory device; and The counter memory cell is initialized with a value based at least in part on a residual charge of the counter memory cell of the memory device.

18. The method according to claim 17, further comprising: The residual charge is amplified and the amplified residual charge is written to the counter memory cell.

19. A method for initializing a counter memory cell of a memory device, comprising: Powering on the memory device; and The counter memory cell of the memory device is initialized with a value based at least in part on a random or pseudo-random threshold voltage compensation pulse width of a threshold voltage compensation sense amplifier.

20. The method of claim 19, further comprising: The threshold voltage compensated pulse width is modified based at least in part on a pseudo-random generator circuit.

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