A method, device, medium and equipment for screening an abnormal flash chip

Abstract

The application provides a screening method, device, medium and equipment for an abnormal Flash chip. The method comprises the following steps: performing data abnormal voltage criticality test on a to-be-tested chip to determine a critical voltage value of the to-be-tested chip, wherein the to-be-tested chip is a to-be-tested Flash chip; determining whether the critical voltage value is greater than a voltage threshold value, wherein the voltage threshold value corresponds to a target gear of a negative bias voltage of the to-be-tested chip; and determining that the negative bias voltage of the to-be-tested chip is abnormal if the critical voltage value is greater than the voltage threshold value. In the case that the negative bias voltage cannot be directly measured, the safety of the negative bias voltage of the to-be-tested chip is evaluated from the side through the critical voltage value of the to-be-tested chip, so that the screening of the abnormal Flash chip is realized, and the accuracy of the screening result is ensured.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a method, apparatus, medium, and device for screening abnormal Flash chips. Background Technology

[0002] NOR Flash (also known as NOR flash memory) and NAND Flash (also known as NAND flash memory) involve several operations: erase, write, and read. These operations are actually implemented by applying different bias voltages to the storage cells. The bias voltage is the voltage applied to ensure that the circuit or electronic device functions properly. This voltage is used to ensure that the device or circuit operates in the appropriate operating region to achieve the required performance.

[0003] Typically, this voltage is boosted by a charge pump to a higher voltage than the chip's maximum operating VCC supply voltage. Since each memory cell can only withstand a limited number of programming / erase cycles, measuring this bias voltage is crucial. To prevent excessive voltage from damaging the memory devices and reducing the reliability of the Flash chip, the bias voltages VPP / VNN need to be measured to filter out chips with abnormal programming voltages. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, medium, and device for screening abnormal Flash chips, so as to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a method for screening abnormal Flash chips, the method comprising:

[0007] A critical voltage test for abnormal data is performed on the chip under test to determine the critical voltage value of the chip under test, wherein the chip under test is the Flash chip under test;

[0008] Determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target level of the negative bias voltage of the chip under test;

[0009] If the voltage exceeds the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal.

[0010] Secondly, embodiments of the present invention provide a screening device for abnormal Flash chips, the device comprising:

[0011] The first processing unit performs a data anomaly voltage critical test on the chip under test to determine the critical voltage value of the chip under test, wherein the chip under test is the Flash chip under test;

[0012] The second processing unit is used to determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal.

[0013] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0014] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.

[0015] Compared to existing technologies, the present invention provides a method, apparatus, medium, and device for screening abnormal Flash chips. This method performs a critical voltage test on the chip under test (the Flash chip in question) to determine its critical voltage value. The critical voltage value is then determined to be greater than a voltage threshold, which corresponds to a target level of the negative bias voltage of the chip under test. If the critical voltage value is greater than the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal. In the method for screening abnormal Flash chips provided by this invention, when the negative bias voltage cannot be directly measured, the critical voltage value of the chip under test is used to indirectly assess the safety of its negative bias voltage, thereby achieving the screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The circuit reference diagram provided for an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0020] Figure 3This is one of the flowcharts illustrating the method for screening abnormal Flash chips provided in an embodiment of the present invention.

[0021] Figure 4 This is the second flowchart illustrating the method for screening abnormal Flash chips provided in this embodiment of the invention.

[0022] Figure 5 This is the third flowchart illustrating the method for screening abnormal Flash chips provided in this embodiment of the invention.

[0023] Figure 6 The fourth flowchart illustrates the method for screening abnormal Flash chips provided in this embodiment of the invention.

[0024] Figure 7 This is a schematic diagram of a unit for screening abnormal Flash chips provided in an embodiment of the present invention.

[0025] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 501-First processing unit; 502-Second processing unit. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0031] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] During the high-voltage and high-voltage discharge phases of the transmission gate channel from the negative bias voltage (VNN) of the Flash chip to ground, a momentary high impedance occurs. If the clock interval read / write state coincides with this situation, VNN will be abruptly coupled, causing the electrostatic discharge (ESD) transistor containing the clock to conduct / parasitic transistors to turn on. The high clock level will be pulled low by a large leakage current, resulting in glitches and potentially leading to 100% write / erase failure. To solve this problem, VNN needs to be disconnected from I / O and grounded. However, this results in VNN becoming untestable, which severely impacts product reliability.

[0034] Please refer to Figure 1 , Figure 1 This is a circuit reference diagram provided for an embodiment of the present invention. In the diagram, CG represents ControlGate, SG represents Select Gate, BL represents Bit Line, Pwell represents P-type well region, VPP represents positive bias voltage, and VNN represents negative bias voltage.

[0035] Please refer to Tables 1 and 2 below. Table 1 corresponds to the traditional design process, and Table 2 corresponds to the current design process. In these tables, VNEG represents the negative supply voltage, VPOS represents the positive supply voltage, program represents write, Operation represents operation, and program-biasvoltage represents the bias voltage applied during write.

[0036] Table 1

[0037] Operation SG CG BL Pwell program VNEG VPOS VNEG VNEG program-bias voltage VNN VPP VNN VNN Traditional design and craftsmanship Measurable Measurable Measurable Measurable

[0038] Table 2

[0039] Operation SG CG BL Pwell program VNEG VPOS VNEG VNEG program-bias voltage VNN VPP VNN VNN Current design process Immeasurable Measurable Immeasurable Immeasurable

[0040] It should be understood that the program principle is as follows: under the action of an applied electric field, electrons in the substrate tunnel and accumulate to the trapping layer. Since electrons exist within the trapping layer, an additional voltage is required to cause inversion at the channel surface. The implementation principle of the abnormal Flash chip screening method provided in this embodiment of the invention is as follows: FN tunneling occurs through the electric field effect of the rated voltage between CG (VPP) and Pwell (VNN), changing the number of electrons stored in the trapping layer. That is, when data needs to be stored, the positive voltage of CG makes it easier for electrons to move from the trapping layer (Channel) to the floating gate, forming a positive charge; conversely, when data needs to be erased, the negative voltage of Pwell drives electrons from the floating gate back to the trapping layer, restoring the original state.

[0041] This invention provides an electronic device, which can be a test bench or a test server communicatively connected to the test bench. Please refer to... Figure 2 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.

[0042] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the faulty Flash chip screening method can be completed through integrated logic circuits in the hardware of processor 10 or through software instructions. The aforementioned processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0043] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device.

[0044] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 2 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.

[0045] The memory 11 is used to store programs, such as programs corresponding to a faulty flash chip screening device. The faulty flash chip screening device includes at least one software function module that can be stored in the memory 11 as software or firmware, or embedded in the operating system (OS) of the electronic device. Upon receiving an execution instruction, the processor 10 executes the program to implement the faulty flash chip screening method.

[0046] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0047] It should be understood that, Figure 2The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 2 The more or fewer components shown, or having the same Figure 2 The different configurations shown. Figure 2 The components shown can be implemented using hardware, software, or a combination thereof.

[0048] The method for screening abnormal Flash chips provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 2 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 3 The methods for screening abnormal Flash chips include S18, S19, S20 and S21, which are described in detail below.

[0049] S18 performs a critical voltage test on the chip under test to determine the critical voltage value of the chip under test.

[0050] The chip under test is the Flash chip.

[0051] When process design conditions prevent direct measurement of the negative bias voltage VNN of a Flash chip, a critical voltage test (VTP voltage) can be performed on the chip under test to determine its critical voltage value. Then, step S19 is executed to indirectly assess the safety of the negative bias voltage of the chip under test using its critical voltage value (VTP voltage).

[0052] In one alternative implementation, a data anomaly voltage threshold test is performed on the chip under test, and the highest VT threshold of the smallest storage unit in the chip under test, i.e., the storage cell, is taken as the critical voltage value of the chip under test.

[0053] S19, determine whether the critical voltage value is greater than the voltage threshold. If yes, proceed to S20; otherwise, proceed to S21.

[0054] The voltage threshold corresponds to the target level of the negative bias voltage of the chip under test, and this voltage threshold can be set in advance.

[0055] S20, confirm that the negative bias voltage of the chip under test is abnormal.

[0056] S21, confirm that the negative bias voltage of the chip under test is normal.

[0057] In the abnormal Flash chip screening method provided in this embodiment of the invention, when the negative bias voltage cannot be directly measured, the negative bias voltage of the chip under test is assessed from the side by using the critical voltage value of the chip under test, thereby achieving the screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0058] Building upon the preceding text, regarding the content of S18, how to accurately obtain the critical voltage value of the chip under test to ensure the accuracy of the screening results for abnormal Flash chips, this embodiment of the invention also provides an optional implementation method, please refer to the following text. S18, the step of performing a data abnormality voltage critical test on the chip under test and determining the critical voltage value of the chip under test, includes: S181, S182, S183, and S184, which are specifically described below.

[0059] S181 applies a test voltage to the control gate terminal of the chip under test.

[0060] Optionally, a stress positive voltage is applied to the control gate terminal of the chip under test. The initial test voltage is a preset fixed value.

[0061] S182: Read the data from the target page in the chip under test and determine whether the read result meets expectations. If it meets expectations, proceed to S183; otherwise, proceed to S184.

[0062] It should be understood that if the read result matches the pre-written result, it is considered to meet expectations. For example, if the pre-written data in the target page is 0, and the read result of the target page is also 0, then it meets expectations.

[0063] S183, reduce the test voltage according to the preset amplitude.

[0064] After S183, S181 is repeated to apply a test voltage to the control gate of the chip under test. By gradually decreasing the test voltage, an unexpected test voltage is found.

[0065] S184 uses the previous test voltage as the critical voltage value of the chip under test.

[0066] Building upon the preceding text, this invention provides an optional implementation method for determining the voltage threshold to ensure the accuracy of screening for abnormal Flash chips. Please refer to [link / reference needed]. Figure 4 The screening methods for abnormal Flash chips also include S13, S15, S16 and S17, which are described in detail below.

[0067] S13, determine the DAC output value distribution data of the sample chip based on the product identifier of the chip under test.

[0068] The sample chip is a Flash chip with the same manufacturing process as the chip under test (DUT) and capable of directly measuring negative bias voltage. The product identifier of the DUT can be, but is not limited to, a product ID or part number. The DAC is an analog signal; the negative bias voltage of each chip corresponds to a trimmed analog signal level. Since there are several chips on the wafer, the same target negative bias voltage value for different chips will correspond to different analog signal levels, thus presenting a distribution of analog signal levels.

[0069] It should be understood that the chip under test (DUT) and a Flash chip capable of directly measuring negative bias voltage can be associated through product identification. When their product identifications match, it indicates that they have the same manufacturing process, and the Flash chip capable of directly measuring negative bias voltage can be used as the sample chip corresponding to the DUT. Sample chips with the same manufacturing process as the DUT can be directly measured to obtain their corresponding DAC output values. The number of these sample chips is greater than a preset number, and the DAC output values ​​of multiple sample chips constitute the DAC output value distribution data of the sample chips.

[0070] It should be noted that the DAC output value distribution data of the sample chip can be obtained through database queries or directly entered by staff.

[0071] S15 determines the initial level based on the DAC output value distribution data.

[0072] The primary level is the level corresponding to the upper limit voltage of the absolute value distribution data of the DAC output value.

[0073] S16 reduces the preset downshift amount based on the initial gear to obtain the target gear.

[0074] The reduction range can be, but is not limited to, four DAC units.

[0075] S17, determine the voltage threshold based on the target level of the negative bias voltage of the chip under test.

[0076] Optionally, the voltage threshold can be determined based on the target range of the negative bias voltage of the chip under test, taking into account the mapping relationship between the target range and the voltage threshold.

[0077] Building upon the preceding text, this invention also provides an optional implementation method for determining how to set the reduction amount to improve the accuracy of the screening results for abnormal Flash chips. Please refer to [link / reference needed]. Figure 5 In S13, after determining the DAC output value distribution data of the sample chip based on the product identifier of the chip under test, the screening method for abnormal Flash chips also includes: S14, as follows.

[0078] S14. Based on the first and second conditions, determine the reduction amount corresponding to the DAC output value distribution data.

[0079] The distribution range of the DAC output value distribution data is a 6sigma distribution range.

[0080] The first condition indicates that the DAC output value distribution data is adjusted according to the reduction amount, and the maximum value in the adjusted DAC output value distribution data (within the positive distribution) does not exceed the maximum value in the DAC output value distribution data before adjustment.

[0081] The second condition indicates that the DAC output value distribution data is adjusted according to the reduction amount, and the difference between the maximum value in the adjusted DAC output value distribution data and the target value in the unadjusted DAC output value distribution data is less than a preset value. This target value can be the maximum value in the unadjusted DAC output value distribution data.

[0082] It should be understood that for Flash chips that cannot directly measure negative bias voltage, the distribution of their DAC values ​​has the following characteristics: the data is positively distributed but relatively dispersed, with a large sigma and outliers; for Flash chips that can directly measure negative bias voltage, the distribution of their DAC values ​​has the following characteristics: the data distribution is extremely convergent, with a small sigma, small positive and negative deviations, and all values ​​are within the expected distribution range.

[0083] In one alternative implementation, for Flash chips where the negative bias voltage cannot be directly measured, there is still a Die whose DAC output value corresponds to a voltage of -1.875V, which exceeds the main median of -1.7V and the maximum target value for Flash chips where the negative bias voltage can be directly measured. Therefore, the bias voltage of this Die is abnormal.

[0084] Analysis of Flash chips capable of directly measuring negative bias voltage revealed that each DAC unit corresponds to approximately 3% of the actual voltage change. For Flash chips where negative bias voltage cannot be directly measured, if the expected safe voltage is -1.72V, the voltage threshold, which would normally be set at the -1.7V level, now needs to be reduced to correspond to the target level, for example, to -1.6V (1.72V - 4 × 0.03V), to ensure safety. It's important to note that this reduction is numerical, regardless of whether the voltage is positive or negative.

[0085] The present invention also provides an optional implementation method, S16, which further includes S30, after reducing the preset downshift amount based on the initial gear to obtain the target gear, and the method for screening abnormal Flash chips.

[0086] S30, the bias voltage of the target test item is increased according to the reduction amount, wherein the target test item is the test item with a bias voltage that can be precisely adjusted.

[0087] It should be understood that the increase in the bias voltage of the target test item corresponds to the reduction in the voltage level.

[0088] For test items where the bias voltage can be precisely adjusted, the effect of the decrease in negative bias voltage can be offset by increasing the bias voltage of the target test item.

[0089] To improve screening efficiency, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 6 The screening methods for abnormal Flash chips also include S11 and S12, as detailed below.

[0090] S11. Determine whether the chip under test (DUT) can be directly measured for negative bias voltage based on the chip's product identifier. If yes, proceed to S12; otherwise, proceed to S13.

[0091] Optionally, the product identifier of the chip under test can be determined by checking whether the product identifier of the chip under test is included in the product identifier table that can directly measure negative bias voltage.

[0092] S12 directly measures the negative bias voltage of the chip under test, and determines whether the negative bias voltage of the chip under test is abnormal based on the measurement result.

[0093] S13, determine the DAC output value distribution data of the sample chip based on the product identifier of the chip under test.

[0094] Please see Figure 7 , Figure 7 An abnormal Flash chip screening device is provided as an embodiment of the present invention. Optionally, the abnormal Flash chip screening device is applied to the electronic device described above.

[0095] The abnormal Flash chip screening device includes: a first processing unit 501 and a second processing unit 502.

[0096] The first processing unit performs a critical voltage test on the chip under test to determine the critical voltage value of the chip under test, wherein the chip under test is the Flash chip under test.

[0097] The second processing unit is used to determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal.

[0098] Optionally, the second processing unit 502 may execute S19, S20 and S21 as described above; the first processing unit 501 may execute the other steps described above.

[0099] It should be noted that the abnormal Flash chip screening device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0100] This invention also provides a storage medium storing computer instructions and programs, which, when read and executed, perform the abnormal Flash chip screening method described in the above embodiments. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0101] The following provides an electronic device, which can be a test bench or a test server connected in communication with a test bench. This electronic device, as follows... Figure 2 As shown, the above-described method for screening abnormal Flash chips can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, which, when executed by the processor 10, perform the abnormal Flash chip screening method of the above embodiment.

[0102] In summary, the present invention provides a method, apparatus, medium, and device for screening abnormal Flash chips. This method performs a critical voltage test on the chip under test to determine its critical voltage value. The chip under test is the Flash chip being screened. It determines whether the critical voltage value is greater than a voltage threshold, which corresponds to a target level of the negative bias voltage of the chip under test. If the critical voltage value is greater than the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal. In the method for screening abnormal Flash chips provided by the present invention, when the negative bias voltage cannot be directly measured, the critical voltage value of the chip under test is used to indirectly assess the safety of the negative bias voltage, thereby achieving the screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0103] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0104] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for screening abnormal Flash chips, characterized in that, The method includes: The DAC output value distribution data of the sample chip is determined based on the product identification of the chip under test; wherein, the sample chip is a Flash chip with the same process as the chip under test and capable of directly measuring the negative bias voltage. Based on the first condition and the second condition, the reduction amount corresponding to the DAC output value distribution data is determined; the first condition indicates that the DAC output value distribution data is adjusted according to the reduction amount, and the maximum value in the adjusted DAC output value distribution data does not exceed the maximum value in the DAC output value distribution data before adjustment; the second condition indicates that the difference between the maximum value in the adjusted DAC output value distribution data and the target value in the DAC output value distribution data before adjustment is less than a preset value. The initial gear level is determined based on the DAC output value distribution data, wherein the initial gear level is the gear level corresponding to the upper limit voltage of the absolute value of the DAC output value distribution data; Based on the initial gear position, the downshift amount is reduced to obtain the target gear position; A critical voltage test for abnormal data is performed on the chip under test to determine the critical voltage value of the chip under test, wherein the chip under test is the Flash chip under test; Determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target level of the negative bias voltage of the chip under test; If the voltage exceeds the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal.

2. The method for screening abnormal Flash chips as described in claim 1, characterized in that, The step of performing a data anomaly voltage threshold test on the chip under test and determining the threshold voltage value of the chip under test includes: Apply a test voltage to the control gate terminal of the chip under test; Read the data from the target page in the chip under test and determine whether the reading result meets expectations; If the expected result is met, the test voltage is reduced by a preset amount, and the preset test voltage is repeatedly applied to the control gate terminal of the chip under test. If it does not meet expectations, the previous test voltage will be used as the critical voltage value of the chip under test.

3. The method for screening abnormal Flash chips as described in claim 1, characterized in that, After reducing the preset downshift amount based on the initial gear position to obtain the target gear position, the method further includes: The bias voltage of the target test item is increased according to the reduction amount, wherein the target test item is a test item whose bias voltage can be precisely adjusted.

4. The method for screening abnormal Flash chips as described in claim 1, characterized in that, After reducing the preset downshift amount based on the initial gear position to obtain the target gear position, the method further includes: The voltage threshold is determined based on the target level of the negative bias voltage of the chip under test.

5. The method for screening abnormal Flash chips as described in claim 1, characterized in that, The method further includes: Determine whether the chip under test can be directly measured for negative bias voltage based on the product identification of the chip under test; If so, the negative bias voltage of the chip under test is measured directly, and the negative bias voltage of the chip under test is determined to be abnormal based on the measurement result.

6. A screening device for abnormal Flash chips, characterized in that, The device includes: A first processing unit is configured to determine the DAC output value distribution data of a sample chip based on the product identifier of the chip under test (DUT); wherein the sample chip is a Flash chip with the same process as the DUT and capable of directly measuring negative bias voltage; determine the reduction amount corresponding to the DAC output value distribution data based on a first condition and a second condition; the first condition indicates that the maximum value in the adjusted DAC output value distribution data does not exceed the maximum value in the unadjusted DAC output value distribution data after adjustment, and the second condition indicates that the difference between the maximum value in the adjusted DAC output value distribution data and the target value in the unadjusted DAC output value distribution data is less than a preset value; determine an initial range based on the DAC output value distribution data, wherein the initial range is the range corresponding to the upper limit voltage of the absolute value of the DAC output value distribution data; reduce the reduction amount based on the initial range to obtain the target range; and perform a critical voltage test on the DUT to determine the critical voltage value of the DUT, wherein the DUT is the Flash chip under test. The second processing unit is used to determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, the negative bias voltage of the chip under test is determined to be abnormal.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.

8. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-5 is implemented.

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