Packaging method and packaging structure of GaN HEMT chip
By preparing a waterproof insulating film layer in the packaging structure of GaN HEMT chip and using epoxy resin or silicone as packaging colloids, the problem that traditional packaging methods cannot meet the moisture-proof and insulation performance requirements of high-end application scenarios is solved, and higher airtightness and moisture-proof performance are achieved, and the reliability and stability of the chip are enhanced.
Patent Information
- Application Number
- CN202510056185.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-04-22
AI Technical Summary
The traditional GaN HEMT chip packaging method cannot meet the needs of higher moisture resistance and insulation performance in high-end application scenarios, especially in environments such as automotive motors and data centers.
A new packaging method is adopted, including preparing a waterproof insulating film layer on the lead regions of the chip, bonding wire and frame, and using epoxy resin or silicone as packaging colloids to cover the lead regions of the chip, bonding wire and frame by molding packaging.
It significantly improves the moisture-proof and insulation performance of GaN HEMT chips, improves airtightness and moisture-proof performance, can meet the needs of high-end application scenarios, and enhances the reliability and stability of the chip.
Smart Images
Figure CN119864284A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip packaging technology, and in particular to a packaging method and packaging structure of a GaN HEMT chip. Background Art
[0002] As GaN HEMT chips are increasingly used in high-performance electronic systems, the requirements for packaging technology are becoming more stringent. Although traditional packaging methods can meet the moisture-proof and insulation requirements to a certain extent, their moisture-proof and insulation performance are already insufficient for higher-end application scenarios, such as automotive motors and data centers. Therefore, developing a new packaging solution to improve the moisture-proof and insulation performance of GaN HEMT chips has become an urgent problem to be solved. Summary of the invention
[0003] The purpose of the present application is to provide a packaging method and packaging structure of a GaN HEMT chip, which can improve the moisture resistance and insulation performance of the GaN HEMT chip.
[0004] In order to achieve the above object, the present application provides a packaging method for a GaN HEMT chip, comprising the following steps:
[0005] S1, providing a chip and a frame, wherein the upper surface of the frame is provided with a functional area and a lead area;
[0006] S2, die-bonding the chip to the functional area of the frame;
[0007] S3, setting a bonding wire connected between the chip and the lead area of the frame;
[0008] S4, preparing a waterproof insulating film layer on the surface of the chip, the surface of the bonding wire and the lead area of the frame;
[0009] S5, preparing a packaging colloid covering the chip, the bonding wires and the lead area of the frame.
[0010] Optionally, the chip is die-bonded to the functional area of the frame by means of a thermally conductive adhesive.
[0011] Optionally, the waterproof insulating film layer is a polyparaxylene nano-coating layer.
[0012] Optionally, in step S4, the assembly to be coated is placed in a coating device, and the polyparaxylene nano-coating layer is prepared on the surface of the chip, the surface of the bonding wire and the lead area of the frame by using vacuum chemical vapor deposition technology.
[0013] Optionally, the packaging colloid is epoxy resin or silicone.
[0014] Optionally, in step S5, the coated assembly is placed in a molding machine, and the packaging colloid covering the chip, the bonding wires and the lead area of the frame is prepared by molding packaging.
[0015] In order to achieve the above-mentioned purpose, the present application also provides a packaging structure of a GaN HEMT chip, the packaging structure comprising a frame, a chip and a packaging colloid, the upper surface of the frame is provided with a functional area and a lead area, the chip is die-bonded in the functional area of the frame, a bonding wire is connected between the chip and the lead area of the frame, the surface of the chip, the surface of the bonding wire and the lead area of the frame are covered with a waterproof insulating film layer, and the packaging colloid covers the chip, the bonding wire and the lead area of the frame.
[0016] Optionally, the chip is die-bonded to the functional area of the frame by means of a thermally conductive adhesive.
[0017] Optionally, the waterproof insulating film layer is a polyparaxylene nano-coating layer.
[0018] Optionally, the packaging colloid is epoxy resin or silicone.
[0019] In the embodiment of the present application, a waterproof insulating film layer is formed on the surface of the chip, the surface of the bonding wire and the lead area of the frame. That is, compared with the traditional packaging method of the GaN HEMT chip, the packaging structure of the GaN HEMT chip in the embodiment of the present application is newly provided with a waterproof insulating film layer, thereby improving the moisture resistance and insulation performance of the GaN HEMT device, which is beneficial to improving the failure problem caused by water vapor intrusion. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a flow chart of a packaging method of a GaN HEMT chip according to an embodiment of the present application.
[0021] Figure 2 It is a schematic diagram of the framework of the embodiment of the present application.
[0022] Figure 3 It is a schematic diagram of assembling the chip to the frame according to an embodiment of the present application.
[0023] Figure 4 It is a schematic diagram of a chip in an embodiment of the present application connected to a lead region of a frame via bonding wires.
[0024] Figure 5 It is a schematic diagram of a waterproof insulating film layer formed on the surface of the chip, the surface of the bonding wire and the lead area in the embodiment of the present application.
[0025] Figure 6 Schematic diagram of the packaging structure of the GaN HEMT chip according to an embodiment of the present application.
[0026] Figure 7 This is a performance comparison table of Parylene, epoxy resin, silicone resin, polyurethane and polyacrylate. DETAILED DESCRIPTION
[0027] In order to explain the technical content, structural features, and achieved effects of the present application in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.
[0028] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0029] Given that GaN HEMT (high electron mobility transistor) devices need to withstand large currents and high voltages in applications, their packaging requirements are extremely high, and airtightness must be ensured to prevent water vapor intrusion and cause failure. The traditional packaging method uses MSL (moisture sensitivity level) to evaluate the moisture resistance of GaN HEMT devices. The current MSL level of GaN HEMT devices does not exceed the MSL-3 level, but the MSL-3 level has gradually failed to meet the needs of high-end application scenarios such as automotive motors and data centers. Similarly, when facing high-end application scenarios such as automotive motors and data centers, better requirements are also put forward for the insulation performance of GaN HEMT devices. Therefore, it is necessary to provide an improved packaging solution to improve the moisture resistance and insulation performance of GaN HEMT devices.
[0030] Embodiment 1
[0031] See also Figures 1 to 6 The present application discloses a packaging method for a GaN HEMT chip, comprising the following steps:
[0032] S1 , providing a chip 10 and a frame 20 , wherein the upper surface of the frame 20 is provided with a functional area 21 and a lead area 22 .
[0033] Specifically, the frame 20 has a bowl and cup position (not shown), and the functional area 21 is located at the bowl and cup position. Of course, it is not limited to this.
[0034] S2 , die-bonding the chip 10 to the functional area 21 of the frame 20 .
[0035] Specifically, the chip 10 is die-bonded to the functional area 21 of the frame 20 by means of the thermal conductive adhesive 30. In order to ensure a good heat dissipation effect, a thermal conductive adhesive 30 with high thermal conductivity can be selected to die-bond the chip 10 to the frame 20.
[0036] S3 , setting a bonding wire 40 connecting the chip 10 and the lead region 22 of the frame 20 .
[0037] By adopting advanced wire bonding technology, the electrodes on the chip 10 can be accurately connected to the external circuit to ensure the stability and reliability of the circuit.
[0038] S4 , preparing a waterproof insulating film layer 50 on the surface of the chip 10 , the surface of the bonding wire 40 and the lead area 22 of the frame 20 .
[0039] In some embodiments, the waterproof insulating film layer 50 is a Parylene nano-coating layer. Compared with general coatings (which have problems such as voids and incomplete coating), the Parylene nano-coating layer can be fully coated, has excellent moisture resistance and insulation resistance, and is conducive to achieving all-round waterproof and insulation resistance protection. In addition, the Parylene nano-coating layer has good thermal stability and chemical stability, and can adapt to harsh working environments.
[0040] Specifically, the polyparaxylene nano-coating layer is uniformly coated on the surface of the chip 10 , the surface of the bonding wire 40 and the lead area 22 of the frame 20 .
[0041] Specifically, when preparing the polyparaxylene nano-coating layer, the assembly to be coated is placed in a coating device, and the polyparaxylene nano-coating layer is prepared on the surface of the chip 10, the surface of the bonding wire 40 and the lead area 22 of the frame 20 using vacuum chemical vapor deposition technology.
[0042] Since the polyparaxylene nano-coating layer is deposited by vacuum chemical vapor deposition technology to form nano-scale organic polymer stacks, and the gas diffusion flow field is used to control the penetration into every tiny gap of the plated object for coating, the polyparaxylene nano-coating layer can have excellent moisture-proof performance and insulation resistance, which is helpful to prevent water vapor intrusion.
[0043] In order to reflect the performance advantages of polyparaxylene nano-coating layer, the following Figure 7 The table shows a brief comparison of the performance of Parylene with epoxy resin, silicone resin, polyurethane and polyacrylate. Figure 7 It can be seen that Parylene's water vapor isolation performance exceeds that of epoxy resin, silicone resin, polyurethane and polyacrylate, and its comprehensive performance is also far superior to epoxy resin, silicone resin, polyurethane and polyacrylate.
[0044] S5 , preparing a packaging resin 60 covering the chip 10 , the bonding wires 40 and the lead region 22 of the frame 20 .
[0045] After the polyparaxylene nano-coating layer is prepared, the encapsulation colloid 60 can be prepared to complete the encapsulation.
[0046] Specifically, the packaging colloid 60 is epoxy resin or silica gel, but it is not limited thereto.
[0047] Specifically, the coated assembly is placed in a molding machine, and a packaging colloid 60 covering the chip 10, the bonding wires 40 and the lead area 22 of the frame 20 is prepared by molding packaging.
[0048] In the embodiment of the present application, a waterproof insulating film layer 50 is prepared on the surface of the chip 10, the surface of the bonding wire 40, and the lead area 22 of the frame 20. That is, compared with the traditional packaging method of the GaN HEMT chip 10, the packaging structure of the GaN HEMT chip 10 in the embodiment of the present application is newly added with a waterproof insulating film layer 50, which can improve the moisture resistance and insulation performance of the GaN HEMT device, and is conducive to improving the failure problem caused by water vapor intrusion. Since the waterproof insulating film layer 50 adopts a polyparaxylene nano-coating layer, it can ensure that the waterproof insulating film layer 50 has excellent moisture resistance and insulation impedance, and specifically can increase the MSL level of the GaN HEMT device from MSL-3 to MSL-2 or above, significantly improve the airtightness and moisture resistance of the GaN HEMT device, and enhance the reliability and stability of the GaN HEMT device. It can meet the needs of high-end application scenarios.
[0049] Embodiment 2
[0050] Please combine Figures 4 to 6 The present application discloses a packaging structure of a GaN HEMT chip. The packaging structure includes a frame 20, a chip 10 and a packaging colloid 60. The upper surface of the frame 20 is provided with a functional area 21 and a lead area 22. The chip 10 is solid-die-bonded in the functional area 21 of the frame 20. A bonding wire 40 is connected between the chip 10 and the lead area 22 of the frame 20. The surface of the chip 10, the surface of the bonding wire 40 and the lead area 22 of the frame 20 are covered with a waterproof insulating film layer 50. The packaging colloid 60 covers the chip 10, the bonding wire 40 and the lead area 22 of the frame 20.
[0051] Specifically, the chip 10 is die-bonded to the functional area 21 of the frame 20 by means of the thermal conductive adhesive 30. In order to ensure a good heat dissipation effect, a thermal conductive adhesive 30 with high thermal conductivity can be selected to die-bond the chip 10 to the frame 20.
[0052] In some embodiments, the waterproof insulating film layer 50 is a Parylene nano-coating layer. Compared with general coatings (which have problems such as voids and incomplete coating), the Parylene nano-coating layer can be fully coated, has excellent moisture resistance and insulation resistance, and is conducive to achieving all-round waterproof and insulation resistance protection. In addition, the Parylene nano-coating layer has good thermal stability and chemical stability, and can adapt to harsh working environments.
[0053] Specifically, the polyparaxylene nano-coating layer is uniformly coated on the surface of the chip 10 , the surface of the bonding wire 40 and the lead area 22 of the frame 20 .
[0054] Specifically, a polyparaxylene nano-coating layer is prepared on the surface of the chip 10 , the surface of the bonding wire 40 , and the lead area 22 of the frame 20 by using vacuum chemical vapor deposition technology.
[0055] Since the polyparaxylene nano-coating layer is deposited by vacuum chemical vapor deposition technology to form nano-scale organic polymer stacks, and the gas diffusion flow field is used to control the penetration into every tiny gap of the plated object for coating, the polyparaxylene nano-coating layer can have excellent moisture-proof performance and insulation resistance, which is helpful to prevent water vapor intrusion.
[0056] Specifically, the packaging colloid 60 is epoxy resin or silica gel, but it is not limited thereto.
[0057] In the embodiment of the present application, a waterproof insulating film layer 50 is formed on the surface of the chip 10, the surface of the bonding wire 40, and the lead area 22 of the frame 20. That is, compared with the traditional packaging method of the GaN HEMT chip 10, the packaging structure of the GaN HEMT chip 10 in the embodiment of the present application is newly added with a waterproof insulating film layer 50, which can improve the moisture resistance and insulation performance of the GaN HEMT device, and is conducive to improving the failure problem caused by water vapor intrusion. Since the waterproof insulating film layer 50 adopts a polyparaxylene nano-coating layer, it can ensure that the waterproof insulating film layer 50 has excellent moisture resistance and insulation impedance, and specifically can improve the MSL level of the GaN HEMT device from MSL-3 to MSL-2 or above, significantly improve the airtightness and moisture resistance of the GaN HEMT device, and enhance the reliability and stability of the GaN HEMT device. It can meet the needs of high-end application scenarios.
[0058] The above disclosure is only a preferred example of the present application, and its role is to facilitate the technical personnel in this field to understand and implement it. Of course, it cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the scope of the patent application of the present application still fall within the scope covered by the present application.
Claims
1. A packaging method for a GaN HEMT chip, characterized in that: The steps include: S1, providing a chip and a frame, wherein the upper surface of the frame is provided with a functional area and a lead area; S2, die-bonding the chip to the functional area of the frame; S3, setting a bonding wire connected between the chip and the lead area of the frame; S4, preparing a waterproof insulating film layer on the surface of the chip, the surface of the bonding wire and the lead area of the frame; S5, preparing a packaging colloid covering the chip, the bonding wires and the lead area of the frame.
2. The packaging method of the GaN HEMT chip according to claim 1, characterized in that: The chip is die-bonded to the functional area of the frame by means of heat-conducting glue.
3. The packaging method of the GaN HEMT chip according to claim 1, characterized in that: The waterproof insulating film layer is a polyparaxylene nano-coating layer.
4. The packaging method of the GaN HEMT chip according to claim 3, characterized in that: In step S4, the assembly to be coated is placed in a coating device, and the polyparaxylene nano-coating layer is prepared on the surface of the chip, the surface of the bonding wire and the lead area of the frame by using vacuum chemical vapor deposition technology.
5. The packaging method of the GaN HEMT chip according to claim 1, characterized in that: The packaging colloid is epoxy resin or silica gel.
6. The packaging method of the GaN HEMT chip according to claim 1, characterized in that: In step S5, the coated assembly is placed in a molding machine, and the packaging colloid covering the chip, the bonding wires and the lead area of the frame is prepared by molding packaging.
7. A packaging structure of a GaN HEMT chip, characterized in that: The packaging structure includes a frame, a chip and a packaging colloid. The upper surface of the frame is provided with a functional area and a lead area. The chip is die-bonded in the functional area of the frame. A bonding wire is connected between the chip and the lead area of the frame. The surface of the chip, the surface of the bonding wire and the lead area of the frame are covered with a waterproof insulating film layer. The packaging colloid covers the chip, the bonding wire and the lead area of the frame.
8. The packaging structure of the GaN HEMT chip according to claim 7, characterized in that: The chip is die-bonded to the functional area of the frame by means of heat-conducting glue.
9. The packaging structure of the GaN HEMT chip according to claim 7, characterized in that: The waterproof insulating film layer is a polyparaxylene nano-coating layer.
10. The packaging structure of the GaN HEMT chip according to claim 7, characterized in that: The packaging colloid is epoxy resin or silica gel.