Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure, and specifically relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, on which a pad oxide layer and a pad nitride layer are sequentially formed, and a shallow trench is formed in the substrate; forming a first liner oxide layer on the inner wall of the shallow trench; selectively atomic layer depositing a barrier layer on the first liner oxide layer; performing a push-back treatment on the pad nitride layer and the pad oxide layer along the notch of the shallow trench, so that the pad nitride layer and the pad oxide layer are pushed back to both sides compared with the notch edge of the shallow trench; in-situ growing a second liner oxide layer on the barrier layer; filling an insulating oxide layer in the shallow trench to form a shallow trench isolation structure. The manufacturing method of the present invention can effectively improve the problem of unstable threshold voltage of narrow-width devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] A Metal Oxide Semiconductor Field Effect Transistor (MOSFET for short) is one of the most common components in integrated circuits. As integrated circuits develop towards high density and integration, the size of transistors continues to shrink. For narrow-channel devices with a process node below 65 nm, there is a problem that as the channel width becomes smaller, the threshold voltage Vt drops sharply (steep drop).

[0003] The threshold voltage Vt is an important electrical parameter of semiconductor devices and also an important control parameter in the manufacturing process. The stability of the threshold voltage is one of the important indicators for evaluating the performance of transistors. The smaller the drift of the threshold voltage with the change of physical conditions, the more reliable the performance of semiconductor devices. Obviously, the problem of the sharp drop of the threshold voltage Vt of semiconductor devices as the channel width becomes smaller will affect the reliability of the devices.

[0004] Therefore, there is an urgent need to provide a method to improve the sharp drop of the threshold voltage of devices as the channel width becomes smaller. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure to improve the problem of unstable threshold voltage of narrow-width devices.

[0006] To achieve the above object and other related objects, the present invention provides a manufacturing method of a semiconductor structure, including the following steps:

[0007] Provide a substrate, on which a pad oxide layer and a pad nitride layer are sequentially formed, and a shallow trench is formed in the substrate;

[0008] Form a first liner oxide layer on the inner wall of the shallow trench;

[0009] Selectively atomic layer deposit a barrier layer on the first liner oxide layer;

[0010] Perform a push-back treatment on the pad nitride layer and the pad oxide layer along the notch of the shallow trench, so that the pad nitride layer and the pad oxide layer are pushed back to both sides compared with the notch edge of the shallow trench;

[0011] In-situ grow a second liner oxide layer on the barrier layer;

[0012] An insulating oxide layer is filled in the shallow trench to form a shallow trench isolation structure.

[0013] In an embodiment of the present invention, the step of selectively depositing a barrier layer on the first liner oxide layer by atomic layer deposition includes:

[0014] Adsorbing a silicon-containing precursor on the surface of the first liner oxide layer to form a silicon-based compound, and the silicon-containing precursor has a directional adsorption property with respect to the first liner oxide layer;

[0015] Introducing a nitrogen-containing precursor on the surface of the silicon-based compound to react the nitrogen-containing precursor with the silicon-based compound to form a silicon nitride barrier layer.

[0016] In an embodiment of the present invention, the silicon-containing precursor includes chlorosilane, and the nitrogen-containing precursor includes ammonia.

[0017] In an embodiment of the present invention, the step of adsorbing a silicon-containing precursor on the surface of the first liner oxide layer includes: exposing the first liner oxide layer to a reaction chamber, injecting the silicon-containing precursor into the reaction chamber, and performing a preheating treatment at 60°C to 80°C so that the silicon-containing precursor is adsorbed on the surface of the first liner oxide layer.

[0018] In an embodiment of the present invention, the thickness of the barrier layer deposited by selective atomic layer deposition is greater than the recess amount of the pad nitride layer, where the recess amount represents the dimension by which the pad nitride layer is recessed toward one side compared to the notch edge of the shallow trench.

[0019] In an embodiment of the present invention, the recess amount of the pad oxide layer is less than or equal to the recess amount of the pad nitride layer.

[0020] In an embodiment of the present invention, the step of recessing the pad nitride layer and the pad oxide layer along the notch of the shallow trench includes: wet etching the pad nitride layer with hot phosphoric acid; wet etching the pad oxide layer with hydrofluoric acid.

[0021] In an embodiment of the present invention, the process of in-situ growing a second liner oxide layer on the barrier layer includes an in-situ vapor growth process; the process of filling an insulating oxide layer in the trench includes a high aspect ratio deposition process.

[0022] In an embodiment of the present invention, the method for manufacturing the semiconductor structure further includes: implanting boron ions into the substrate on at least one side of the shallow trench isolation structure to form a P-type well region;

[0023] Forming a gate structure on the surface of the P-type well region;

[0024] Forming source and drain regions in the P-type well regions on both sides of the gate structure respectively.

[0025] On the other hand, the present invention provides a semiconductor structure, which includes:

[0026] A substrate, in which a shallow trench is formed. A pad oxide layer and a pad nitride layer are sequentially formed on the substrate, and the pad oxide layer and the pad nitride layer are pushed back to both sides compared with the notch edge of the shallow trench.

[0027] A first liner oxide layer, formed on the inner wall of the shallow trench;

[0028] A barrier layer, selectively atomic layer deposited on the first liner oxide layer;

[0029] A second liner oxide layer, in-situ grown on the barrier layer;

[0030] An insulating oxide layer, filled in the shallow trench, and filled with the second liner oxide layer, the barrier layer and the first liner oxide layer to fill the shallow trench, forming a shallow trench isolation structure.

[0031] In an embodiment of the present invention, the material of the barrier layer includes silicon nitride, the material of the first liner oxide layer includes silicon oxide, and the material of the second liner oxide layer includes silicon oxide.

[0032] In an embodiment of the present invention, the thickness of the barrier layer is greater than the push-back amount of the pad nitride layer, and the ratio a of the push-back amount of the pad nitride layer to the thickness of the barrier layer satisfies 0.5 ≤ a < 1.

[0033] In summary, for the manufacturing method of the semiconductor structure of the present invention, a first liner oxide layer is first formed on the inner wall of the shallow trench, a barrier layer is formed on the first liner oxide layer by selective atomic layer deposition, then the pad nitride layer and the pad oxide layer are subjected to a push-back treatment and a second liner oxide layer is in-situ formed on the barrier layer, and then an insulating oxide layer is filled to form a shallow trench isolation structure. The unexpected effects are as follows: The selectively atomic layer deposited barrier layer can better prevent the doping ions in the well region from diffusing into the shallow trench isolation structure, and the barrier layer can protect the edge of the shallow trench during the push-back treatment of the pad nitride layer; The push-back treatment increases the arc of the edge corner of the shallow trench isolation structure, and the threshold voltage Vt has an increasing trend, thereby improving the problem that the narrow-width device steeply drops as the channel width becomes smaller, making the threshold voltage of the narrow-width device more stable; The second liner oxide layer in-situ grown on the barrier layer can make the filling of the insulating oxide layer more dense and have stronger gap filling ability, thereby making the insulation of the shallow trench isolation structure better.

[0034] The shallow trench isolation structure composed of the first liner oxide layer, the selectively atomic layer deposited barrier layer, the second liner oxide layer and the insulating oxide layer makes the performance of the narrow-width semiconductor device more stable.

[0035] Furthermore, when selectively atomic layer depositing the barrier layer, a silicon-containing precursor having specific adsorption to the first liner oxide is selected, so that the barrier layer grows along the sidewalls of the shallow trenches, thereby forming a silicon nitride barrier layer at the edges of the shallow trench isolation structure, which has a better blocking effect on the doped ions in the well region. Further, chlorosilane is selected as the silicon-containing precursor, and preheating treatment is carried out at 60°C to 80°C, which can enhance the adsorption of chlorosilane to the first liner oxide layer.

[0036] Of course, it is not necessary for any product implementing the present invention to achieve all of the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 It is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment of the present invention;

[0039] Figure 2 It is a schematic structural diagram of a substrate according to an embodiment of the present invention;

[0040] Figure 3 It is a schematic structural diagram of forming a first liner oxide layer according to an embodiment of the present invention;

[0041] Figure 4 It is a schematic structural diagram of selectively atomic layer depositing a barrier layer on the first liner oxide layer according to an embodiment of the present invention;

[0042] Figure 5 It is a schematic principle diagram of selectively atomic layer depositing a barrier layer according to an embodiment of the present invention;

[0043] Figure 6 It is a schematic structural diagram of a backtracking process according to an embodiment of the present invention;

[0044] Figure 7 It is a schematic structural diagram of a backtracking process according to another embodiment of the present invention;

[0045] Figure 8 It is a schematic structural diagram of in-situ growing a second liner oxide layer on the barrier layer according to an embodiment of the present invention;

[0046] Figure 9 It is a photo of a local transmission electron microscope (TEM) of a wafer after the in-situ growth is completed according to an embodiment of the present invention;

[0047] Figure 10 is Figure 9 the TEM-EDX energy spectrum elemental analysis diagram of;

[0048] Figure 11 This is the structural schematic diagram of filling an insulating oxide layer in a shallow trench in an embodiment of the present invention.

[0049] Label description:

[0050] 100, substrate; 101, shallow trench; 110, pad oxide layer; 111, pad nitride layer; 120, first liner oxide layer; 130, barrier layer; 140, second liner oxide layer; 150, insulating oxide layer. Specific embodiments

[0051] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] In the present invention, when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and differentiating purposes and cannot be understood as indicating or implying relative importance.

[0054] Shallow Trench Isolation (STI) has excellent isolation performance, a flat surface shape, good anti-latch-up performance, almost zero field erosion, small leakage current and junction capacitance, etc., and has now become the mainstream isolation technology in the semiconductor device manufacturing process.

[0055] Under normal circumstances, the threshold voltage Vt of a MOS device increases as the channel width narrows, i.e., the narrow width effect; however, in the Shallow Trench Isolation (STI) process, the threshold voltage Vt of the device drops steeply as the channel width narrows, which is called the reverse narrow width effect. The inventors found in their research that the main reason for the reverse narrow width effect is that the doped ions implanted in the well region diffuse into the STI through the interface between the STI and the active region or the process window is insufficient, and the reverse narrow width effect of the N-type field effect transistor (NMOS) is the most significant.

[0056] To improve the above problems, the present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. By selectively atomic layer deposition, a barrier layer is formed at the edge of the shallow trench isolation structure to prevent the well region doped ions from diffusing into the shallow trench isolation structure. At the same time, by a push-back process, the top rounded corner of the shallow trench isolation structure is enlarged, thereby improving the stability of the threshold voltage.

[0057] Please refer to Figure 1 , the present invention provides a manufacturing method of a semiconductor structure, including the following steps:

[0058] S1. Provide a substrate 100, on which a pad oxide layer 110 and a pad nitride layer 111 are sequentially formed, and a shallow trench 101 is formed in the substrate 100 (see Figure 2 );

[0059] S2. Form a first liner oxide layer 120 on the inner wall of the shallow trench 101 (see Figure 3 );

[0060] S3. Selectively atomic layer deposit a barrier layer 130 on the first liner oxide layer 120 (see Figure 4 );

[0061] S4. Perform a push-back process on the pad nitride layer 111 and the pad oxide layer 110 along the notch of the shallow trench 101, so that the pad oxide layer 110 and the pad nitride layer 111 are pushed back to both sides compared with the notch edge of the shallow trench 101 (see Figure 6 );

[0062] S5. In-situ grow a second liner oxide layer 140 on the barrier layer 130 (see Figure 8 );

[0063] S6. Fill the shallow trench 101 with an insulating oxide layer 150 to form a shallow trench isolation structure (see Figure 11 ).

[0064] Taking an NMOS transistor as an example, the following will introduce in detail each step of the manufacturing method of the semiconductor structure in combination with Figures 2 to 11 Please refer to

[0065] In step S1, the substrate 100 can be any material suitable for forming a semiconductor structure. For example, it can be silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI for short), a silicon / germanium / silicon stacked substrate, etc. The type of the substrate 100 can be selected according to actual production. It can use a P-type semiconductor substrate or an N-type semiconductor substrate. Among them, the P-type semiconductor substrate is formed by doping trivalent ions such as boron, aluminum, gallium, etc. in an intrinsic semiconductor; the N-type semiconductor substrate is formed by doping pentavalent ions such as phosphorus, arsenic, antimony, etc. in an intrinsic semiconductor. In one embodiment, the substrate 100 selects a P-type silicon substrate. Figure 2

[0066] The shallow trench 101 formed in the substrate 100 is used to fill an insulating material to form a shallow trench isolation structure. The substrate 100 outside the shallow trench 101 serves as the active region of the corresponding semiconductor device, and the subsequent formed shallow trench isolation structure insulates and separates the active regions on the substrate 100. The number of the shallow trenches 101 is not limited here and can be set according to actual production needs. The shallow trench 101 can be formed by using conventional technical means in the art.

[0067] ​Since the formation of the shallow trench 101 involves an etching process, in order to prevent the active region of the substrate 100 from being damaged by etching, a pad oxide layer 110 and a pad nitride layer 111 are sequentially formed on the surface of the substrate 100 before the formation of the shallow trench 101. In a specific embodiment, the formation process of the shallow trench 101 is as follows: First, a pad oxide layer 110 is formed on the substrate 100. The pad oxide layer 110 can serve as a buffer layer to improve the stress between the substrate 100 and the subsequently formed pad nitride layer 111. The pad oxide layer 110 is, for example, a dense silicon dioxide material. The pad oxide layer 110 can be formed by thermal oxidation methods, such as dry oxidation, wet oxidation, or in-situ steam generation (ISSG). Then, a pad nitride layer 111 is formed on the pad oxide layer 110. The pad nitride layer 111 is, for example, silicon nitride (Si3N4). The pad nitride layer 111 can serve as a hard mask during the etching of the shallow trench 101 to protect the active region of the substrate 100 from damage. The pad nitride layer 111 can be formed by processes such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). Then, a patterned photoresist layer (not shown in the figure) is formed on the pad nitride layer 111. For example, a photoresist is spin-coated on the pad nitride layer 111 to cover the upper surface of the pad nitride layer 111. After exposure and development, a plurality of openings exposing the pad nitride layer 111 are formed in the photoresist. The number of openings is the same as the number of shallow trenches 101 to be formed. Then, using the patterned photoresist layer as a mask, the pad nitride layer 111, the pad oxide layer 110, and a part of the substrate 100 are etched downward in sequence to form the shallow trench 101. In this embodiment, for example, the shallow trench 101 is formed by dry etching and / or wet etching processes. After that, the photoresist is removed by ashing or wet cleaning processes.

[0068] Please refer to Figure 3 , then step S2 is executed to form a first liner oxide layer 120 on the inner wall (sidewall and bottom wall) of the shallow trench 101. The material of the first liner oxide layer 120 is, for example, silicon dioxide. It can deposit silicon dioxide into the shallow trench 101 by chemical vapor deposition to form the first liner oxide layer 120; it can also use thermal oxidation to oxidize the silicon material of the substrate 100 in the shallow trench 101 to form the first liner oxide layer 120 covering the inner wall of the shallow trench 101. The formation of the first liner oxide layer 120 can reduce the etching damage caused during the etching process of the shallow trench 101 and make the corners of the shallow trench 101 smoother. In this embodiment, the first liner oxide layer 120 is formed by a thermal oxidation process, and the thickness of the formed first liner oxide layer 120 is not limited and can be set according to actual production. As an example, the thickness of the first liner oxide layer 120 is 10 angstroms to 50 angstroms, and can be, for example, 10 angstroms, 30 angstroms, 50 angstroms, etc.

[0069] Please refer toFigure 4 Next, step S3 is executed to selectively atomic layer deposit (S-ALD for short) a barrier layer 130 on the first liner oxide layer 120. Further, the material of the barrier layer 130 includes silicon nitride (Si3N4). The dielectric constant of silicon dioxide (SiO2) is 3.9, and the dielectric constant of silicon nitride (Si3N4) reaches 7.0, which is much larger than that of silicon dioxide. Therefore, silicon nitride is an ideal barrier layer that can effectively block the diffusion of impurities such as boron and phosphorus and metals. In other embodiments, the barrier layer 130 can also be made of other materials with the same effect as silicon nitride, such as silicon oxynitride. Selective atomic layer deposition can form the barrier layer 130 in a specific area as needed. In this embodiment, it is necessary to form the barrier layer 130 on the edge of the shallow trench isolation structure, that is, on the first liner oxide layer 120 on the inner wall of the shallow trench 101. Therefore, a silicon-containing precursor with good adsorption to the first liner oxide layer 120 is selected as the precursor for selective atomic layer deposition to ensure that the barrier layer 130 is formed on the first liner oxide layer 120.

[0070] Please refer to Figure 4 and Figure 5 , in an embodiment, the material of the barrier layer 130 is silicon nitride, and the formation process of the silicon nitride barrier layer includes:

[0071] Adsorb a silicon-containing precursor on the surface of the first liner oxide layer 120 to form a silicon-based compound.

[0072] Specifically, after the growth of the first liner oxide layer 120 is completed, the substrate 100 is placed in the reaction chamber of the atomic layer deposition equipment, and a silicon-containing precursor is introduced into the reaction chamber. Using the chemisorption between the silicon-containing precursor and the first liner oxide layer 120, a monolayer of silicon-based compound is formed on the first liner oxide layer 120. Among them, the introduced silicon-containing precursor has directional adsorption to the first liner oxide layer 120. Further, the silicon-containing precursor is selected from chlorosilanes, such as dichlorosilane, trichlorosilane, etc. Furthermore, the silicon-containing precursor is preheated at 60°C to 80°C to further improve the adsorption of chloride ions in the chlorosilane to silicon dioxide in the first liner oxide layer 120. The temperature of the preheating treatment is, for example, 60°C, 70°C, or 80°C, etc. The time of the preheating treatment is controlled within 1 min to 2 min, for example, 1 min, 1.5 min, or 2 min, etc. After the preheating treatment is completed, an inert gas, such as nitrogen or argon, is introduced into the reaction chamber to flush the first liner oxide layer 120 to remove the unreacted silicon-containing precursor and by-products.

[0073] Introduce a nitrogen-containing precursor on the surface of the silicon-based compound to react the nitrogen-containing precursor with the silicon-based compound to form the barrier layer 130.

[0074] Specifically, a nitrogen-containing precursor is introduced into the reaction chamber, so that the nitrogen-containing precursor reacts chemically with the silicon-based compound on the surface of the first liner oxide layer 120 to form a barrier layer 130. The nitrogen-containing precursor is, for example, ammonia (NH3). The temperature for the chemical reaction between ammonia and chlorosilane is 50°C to 350°C. Further, the reaction temperature is 100°C to 200°C. More specifically, the reaction temperature is 150°C. After the reaction is completed, an inert gas is used again for rinsing to remove excess reaction gases and by-products, completing one ALD cycle. The number of ALD cycles depends on the thickness of the grown barrier layer 130. In this embodiment, the thickness of the barrier layer 130 is 10 to 20 nm. As an example, the thickness of the barrier layer 130 can be 10 nm, 15 nm, 20 nm, etc. The selective atomic layer deposition process employed in this application can achieve uniform deposition of a silicon nitride film on the first liner oxide layer 120, effectively preventing the diffusion of doped ions in the active region into the shallow trench isolation structure.

[0075] Please refer to Figure 6 , perform step S4, and perform a pullback process on the pad nitride layer 111 and the pad oxide layer 110 along the notch of the shallow trench 101 to enlarge the fillet at the edge of the notch of the shallow trench 101.

[0076] In one embodiment, the steps of the pullback process include: using an etching process to process the pad nitride layer 111 and the pad oxide layer 110 on both sides of the notch edge of the shallow trench 101 to remove part of the pad nitride layer 111 and the pad oxide layer 110. The etching method can be dry etching or wet etching. In this embodiment, a wet etching process is used to etch the pad nitride layer 111 and the pad oxide layer 110. Specifically, when performing the pullback process on the pad oxide layer 110, hydrofluoric acid is used to wet-etch the pad oxide layer 110, and when performing the pullback process on the pad nitride layer 111, hot phosphoric acid is used to wet-etch the pad nitride layer 111. Further, the pullback amount of the pad nitride layer 111 is less than the thickness of the barrier layer 130 deposited by selective atomic layer deposition, so as to avoid damage to the shallow trench 101 caused by hot phosphoric acid. More specifically, the ratio a of the pullback amount of the pad nitride layer 111 to the thickness of the barrier layer 130 satisfies 0.5 ≤ a < 1. Exemplarily, a can be 0.5, 0.8, 0.9, etc. The pullback amount here refers to the minimum distance between the opening sidewall of the pad nitride layer 111 / pad oxide layer 110 and the notch edge of the shallow trench 101 in the direction parallel to the surface of the substrate 100. Refer to Figure 6 and Figure 7 d1 and d2 in. The pullback amount d1 of the pad oxide layer 110 can be equal to the pullback amount d2 of the pad nitride layer 111 (the sidewalls of the pad oxide layer 110 and the pad nitride layer 111 are flush. Refer to Figure 6), the etch-back amount d1 of the pad oxide layer 110 can also be less than the etch-back amount d2 of the pad nitride layer 111 (the sidewall of the pad oxide layer 110 protrudes from the sidewall of the pad nitride layer 111, see Figure 7 ), and it can be specifically selected according to the requirements of actual production devices. The inventors found in the research that by expanding the STI edge corner rounding, that is, the etch-back process, the threshold voltage Vt has an increasing trend. This is because through the etch-back process, the process window of the STI can be increased, thereby reducing the feature size of the active region, and thus increasing the threshold voltage of the semiconductor device.

[0077] Please refer to Figure 8 , perform step S5 to in-situ grow a second liner oxide layer 140 on the barrier layer 130. The material of the second liner oxide layer 140 includes silicon dioxide. In one embodiment, the material of the barrier layer 130 is silicon nitride, and the process of forming the second liner oxide layer 140 includes an In-Situ Steam Generation (ISSG) process. The in-situ steam generation process is a process of growing an oxide layer through a high-temperature water vapor atmosphere. The growth rate of the oxide layer is relatively fast, and the thickness of the grown oxide layer is relatively uniform. The thickness of the oxide layer grown by the in-situ steam generation method can be precisely controlled. The principle of in-situ growing the second liner oxide layer 140 on the barrier layer 130 in this application is: Si3N4 + H2O → SiO2 + N2 + H2, that is, at high temperature, the silicon nitride in the barrier layer 130 reacts with water vapor to generate silicon dioxide, so as to in-situ form the second liner oxide layer 140 on the surface of the barrier layer 130. The reaction temperature under these process conditions is controlled at 900 °C to 1200 °C, for example, 900 °C, 1000 °C or 1200 °C, etc.; the reaction time is determined according to the thickness of the second liner oxide layer 140. In this embodiment, the thickness of the formed second liner oxide layer 140 is 10 nm to 20 nm, for example, 10 nm, 15 nm or 20 nm, etc. The second liner oxide layer 140 in-situ grown on the surface of the barrier layer 130 makes the subsequent insulation oxide layer 150 of the STI fill more densely. It should be noted that when in-situ growing the second liner oxide layer 140, since the pad nitride layer 111 and the silicon substrate exposed in the etch-back treatment area are also exposed to the reaction environment, therefore, an oxide layer will also be formed on the surface of the pad nitride layer 111 and the silicon substrate surface exposed by the etch-back treatment, which will not have an adverse effect on the subsequent process.

[0078] Moreover, since the formation of the second liner oxide layer 140 uses the silicon nitride in the barrier layer 130 as a reactant, that is to say, the formation of the second liner oxide layer 140 consumes part of the barrier layer 130. Therefore, after the formation of the second liner oxide layer 140, the thickness of the barrier layer 130 is thinner than that of the previously selectively atomic layer deposited one, but it is not thinned in a 1:1 ratio (completely consumed), only the silicon nitride on the surface of the barrier layer 130 is consumed. Therefore, even if the thickness of the second liner oxide layer 140 is the same as that of the barrier layer 130 selectively atomic layer deposited in step S3, there will still be a barrier layer 130. Further, the thickness of the barrier layer 130 selectively atomic layer deposited in step S3 is greater than that of the second liner oxide layer 140 to ensure that the finally remaining barrier layer 130 plays a role in blocking the ion diffusion in the active region.

[0079] From Figure 9 and Figure 10 The characterization results show that the second liner oxide layer 140 is formed on the surface of the barrier layer 130, which indicates that the in-situ water vapor growth method realizes the in-situ growth of the second liner oxide layer 140 on the barrier layer 130.

[0080] Please refer to Figure 11 , then perform step S6, fill the shallow trench 101 formed with the second liner oxide layer 140 with an insulating material used in shallow trench isolation to obtain an insulating oxide layer 150 that fills the shallow trench 101. For example, the insulating material is silicon dioxide, and the filling is performed by a High Aspect Ratio Process (HARP) deposition process. In other embodiments, a high density plasma chemical vapor deposition (HDPCVD) process may also be used to fill the insulating material into the shallow trench. Then, the insulating oxide layer 150 is planarized to the top of the pad nitride layer 111 by Chemical Mechanical Polishing (CMP) to form a shallow trench isolation structure.

[0081] In one embodiment, after forming the shallow trench isolation structure, the manufacturing method of the semiconductor structure further includes:

[0082] Inject boron ions into the substrate 100 on at least one side of the shallow trench isolation structure to form a P-type well region (not shown in the figure).

[0083] The P-type well region serves as the formation region of the electrode structure of the NMOS device, and it can be formed by referring to the conventional ion implantation method in the art, which will not be elaborated here.

[0084] Form a gate structure (not shown in the figure) on the surface of the P-type well region.

[0085] The gate structure includes a gate oxide layer, a gate, and sidewalls. The gate oxide layer is formed on the upper surface of the P-type well region and can be formed by thermal oxidation methods such as dry oxidation and wet oxidation. The gate oxide layer serves as an insulating layer between the gate and the substrate 100 to prevent current from directly flowing from the gate to the substrate 100. The gate is formed on the surface of the gate oxide layer and can be polysilicon or a metal material. The gate can be formed by processes such as atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD). The gate, as the control terminal of the transistor, controls the formation and disappearance of the channel through the gate voltage, thereby controlling the current between the source and the drain. The sidewalls are formed on both sides of the gate and can be insulating materials such as silicon dioxide and silicon nitride. The sidewalls can protect the gate and the gate oxide layer from damage during subsequent process steps (such as ion implantation) and can also act as a mask during ion implantation in the source-drain region.

[0086] Source and drain regions (not shown in the figure) are respectively formed in the P-type well regions on both sides of the gate structure.

[0087] Using the sidewalls as a mask, N-type ions are respectively implanted into the well regions on both sides of the gate structure to form the source and drain regions, thereby forming an NMOS device. The N-type ions are selected from pentavalent ions such as phosphorus, arsenic, and antimony.

[0088] In the manufacturing method of the semiconductor structure of the present invention, a blocking layer is directionally formed on the first liner oxide layer by using a selective atomic layer deposition process, which can better prevent the diffusion of well region doping ions into the shallow trench isolation structure; the back-pushing treatment of the pad nitride layer and the pad oxide layer enlarges the rounded corners at the edges of the shallow trenches, making the threshold voltage Vt of the device tend to increase, thereby improving the problem of unstable threshold voltage of the device; the second liner oxide layer grown in-situ on the blocking layer can make the filling of the insulating oxide layer more dense and improve the insulation of the shallow trench isolation structure.

[0089] Please refer to Figure 11 , based on the same inventive concept, the present invention also provides a semiconductor structure, which is prepared by using the above preparation method.

[0090] The semiconductor structure includes: a substrate 100 and a shallow trench isolation structure formed in the substrate 100.

[0091] The substrate 100 is made of any material suitable for forming semiconductor devices. For example, it can be silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), a silicon / germanium / silicon stacked substrate, etc. The substrate 100 can be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0092] A shallow trench 101 is formed in the substrate 100 for filling an insulating oxide layer 150 to form a shallow trench isolation structure. And before forming the shallow trench 101, a pad oxide layer 110 and a pad nitride layer 111 are also formed on the substrate 100. The pad oxide layer 110 is formed on the substrate 100, and the pad nitride layer 111 is formed on the pad oxide layer 110. The pad oxide layer 110, as a buffer layer, can improve the stress between the substrate 100 and the subsequently formed pad nitride layer 111. The material of the pad oxide layer 110 is, for example, silicon dioxide. The pad nitride layer 111 can be used as a hard mask during the etching of the shallow trench 101 to protect the active region of the substrate 100 from damage. The material of the pad nitride layer 111 is, for example, silicon nitride. Further, the pad oxide layer 110 and the pad nitride layer 111 are pushed back laterally compared to the notch edge of the shallow trench 101.

[0093] The shallow trench isolation structure includes a first liner oxide layer 120, a barrier layer 130, a second liner oxide layer 140, and an insulating oxide layer 150. Among them, the material of the first liner oxide layer 120 is, for example, silicon dioxide, and its thickness can be, for example, 10 to 50 angstroms. The first liner oxide layer 120 can reduce the etching damage caused during the etching of the shallow trench 101 and make the corners of the shallow trench 101 smoother.

[0094] The barrier layer 130 is formed on the surface of the first liner oxide layer 120 by selective atomic layer deposition. In one embodiment, the material of the barrier layer 130 is silicon nitride, which is formed by reacting a silicon-containing precursor such as chlorosilane having a directional adsorption property for the first liner oxide layer 120 with a nitrogen-containing precursor such as ammonia. This process can form the barrier layer 130 in a specific area and can effectively prevent the diffusion of well region ions into the shallow trench isolation structure. Among them, the thickness of the barrier layer 130 is greater than the push-back amount of the pad nitride layer 111, and the push-back amount of the pad oxide layer 110 is less than or equal to the push-back amount of the pad nitride layer 111. Further, the ratio a of the push-back amount of the pad nitride layer 111 to the thickness of the barrier layer 130 satisfies 0.5 ≤ a < 1. For example, a can be 0.5, 0.8, or 0.9, etc.

[0095] The second liner oxide layer 140 is formed on the surface of the barrier layer 130 by an in-situ water vapor generation process, making the subsequent filling of the insulating oxide layer 150 of the STI more dense.

[0096] The insulating oxide layer 150 is filled in the shallow trench, and together with the second liner oxide layer 140, the barrier layer 130, and the first liner oxide layer 120, fills the shallow trench 101 to form a shallow trench isolation structure. This shallow trench isolation structure with a sandwich structure makes the performance of the narrow-width semiconductor structure more stable.

[0097] In one embodiment, the semiconductor structure further includes a gate structure and source and drain regions. The gate structure is formed on the substrate 100 on at least one side of the shallow trench isolation structure, and a P-well region is formed in the semiconductor on this side. The gate structure includes a gate oxide layer, a gate, and sidewalls. The gate oxide layer is formed on the substrate 100, the gate is formed on the gate oxide layer, and the sidewalls are formed on both sides of the gate and the gate oxide layer. The gate oxide layer serves as an insulating layer between the gate and the substrate 100 to prevent current from directly flowing from the gate to the substrate 100. The material of the gate can be polysilicon or a metal material; the sidewalls can be insulating materials such as silicon dioxide and silicon nitride. The sidewalls can protect the gate and the gate oxide layer from damage in subsequent process steps (such as ion implantation), and can also act as a mask during ion implantation in the source and drain regions. The source and drain regions are formed in the substrate on both sides of the gate structure. When a sufficient voltage is applied to the gate, it forms a conductive channel in the substrate 100 region between the source region and the drain region, and this channel allows current to flow from the source to the drain.

[0098] It should be noted that the structures and processes not detailed above in the present invention can all be obtained by conventional technical means in the art.

[0099] The manufacturing method of the semiconductor structure of the present invention first forms a first liner oxide layer on the inner wall of the shallow trench, forms a barrier layer on the first liner oxide layer by selective atomic layer deposition, then performs a push-back treatment on the pad nitride layer and the pad oxide layer and in-situ forms a second liner oxide layer on the surface of the barrier layer, and then fills the insulating oxide layer to form an isolation structure. Using selective atomic layer deposition to directionally form a barrier layer on the first liner oxide layer can better prevent the diffusion of well region doping ions into the shallow trench isolation structure; the push-back treatment of the pad nitride layer and the pad oxide layer expands the rounded corners at the edges of the shallow trench, making the threshold voltage Vt of the device tend to increase, thereby improving the problem of unstable threshold voltage of the device. The second liner oxide layer grown in-situ on the barrier layer can make the filling of the insulating oxide layer more dense and improve the insulation of the shallow trench isolation structure. The semiconductor structure obtained by using the manufacturing method of the present invention can improve the anti-narrow-width effect of narrow-width semiconductor devices and improve the stability of the threshold voltage. Therefore, the present invention effectively overcomes some practical problems in the prior art and thus has high utilization value and practical significance.

[0100] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, on which a pad oxide layer and a pad nitride layer are sequentially formed, and a shallow trench is formed in the substrate; forming a first liner oxide layer on the inner wall of the shallow trench; selectively atomically layer depositing a barrier layer on the first liner oxide layer; Pushing back the pad nitride layer and the pad oxide layer along the notch of the shallow trench, so that the pad nitride layer and the pad oxide layer are pushed back to both sides compared with the notch edge of the shallow trench; In-situ growing a second liner oxide layer on the barrier layer; Filling an insulating oxide layer in the shallow trench to form a shallow trench isolation structure; Wherein, in the step of selectively atomically depositing a barrier layer on the first liner oxide layer, a silicon-containing precursor having good adsorption to the first liner oxide layer is selected as a precursor for selective atomic layer deposition; The thickness of the barrier layer of the selective atomic layer deposition is greater than the push-back amount of the pad nitride layer, where the push-back amount refers to the dimension of the pad nitride layer pushed back to one side compared to the notch edge of the shallow trench.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of selectively atomically depositing a barrier layer on the first liner oxide layer comprises: Adsorbing a silicon-containing precursor on the surface of the first liner oxide layer to form a silicon-based compound, wherein the silicon-containing precursor has directional adsorption to the first liner oxide layer; A nitrogen-containing precursor is introduced onto the surface of the silicon-based compound, and the nitrogen-containing precursor is reacted with the silicon-based compound to form a silicon nitride barrier layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The silicon-containing precursor includes chlorosilane, and the nitrogen-containing precursor includes ammonia.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The step of adsorbing a silicon-containing precursor on the surface of the first liner oxide layer includes: exposing the first liner oxide layer to a reaction chamber, injecting a silicon-containing precursor into the reaction chamber, and preheating at 60° C. to 80° C. so that the silicon-containing precursor is adsorbed on the surface of the first liner oxide layer.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The push-back amount of the pad oxide layer is less than or equal to the push-back amount of the pad nitride layer.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of pushing back the pad nitride layer and the pad oxide layer along the notch of the shallow trench comprises: Wet etching the pad nitride layer using hot phosphoric acid; The pad oxide layer is wet-etched using hydrofluoric acid.

7. A semiconductor structure, characterized in that: include: A substrate, wherein a shallow trench is formed in the substrate, and a pad oxide layer and a pad nitride layer are sequentially formed on the substrate, and the pad oxide layer and the pad nitride layer are pushed back to both sides compared to the notch edge of the shallow trench; A first liner oxide layer is formed on the inner wall of the shallow trench; a barrier layer, selectively atomically deposited on the first liner oxide layer; a second liner oxide layer, in-situ grown on the barrier layer; An insulating oxide layer is filled in the shallow trench, and together with the second liner oxide layer, the barrier layer and the first liner oxide layer, fills the shallow trench to form a shallow trench isolation structure; Wherein, the barrier layer uses a silicon-containing precursor having good adsorption to the first liner oxide layer as a precursor for selective atomic layer deposition; The thickness of the barrier layer is greater than the push-back amount of the pad nitride layer.

8. The semiconductor structure according to claim 7, characterized in that: The material of the barrier layer includes silicon nitride, the material of the first liner oxide layer includes silicon oxide, and the material of the second liner oxide layer includes silicon oxide.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The ratio a of the push-back amount of the pad nitride layer to the thickness of the barrier layer satisfies 0.5≤a<1.

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