Metal Damascus integrated etching method and chip
By adjusting the RF power of the plasma etching hard mask in integrated metal Damascus etching to form a curved side wall, the problem of excessive line width after etching is solved, and key dimensional deviation and product quality are optimized.
Patent Information
- Application Number
- CN202311359990.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-19
- Publication Date
- 2025-04-22
AI Technical Summary
In the prior art, the morphology of the side wall of the titanium nitride after integrated etching of metal Damascus is too perpendicular, resulting in the line width of the grooves being too large after the Damascus integrated etching pattern is transferred, affecting the product electrical parameters and wafer yield.
By etching the hard mask when plasma etching the hard mask, using a target source RF power higher than the standard source RF power, and using a target bias RF power lower than the standard bias RF power, the hard mask forms a curved sidewall with a bottom width smaller than the middle width.
The side wall morphology of the etching groove is optimized, the line width at the bottom of the etching groove is reduced, and the line width difference between the hard mask and Damascus integrated etching is reduced, thereby optimizing the key dimensional deviation of the integrated process of metal Damascus, and improving product quality and yield.
Smart Images
Figure CN119864320A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of chip preparation, and in particular to a metal Damascus integrated etching method and a chip. Background Art
[0002] In the back-end process of logic device manufacturing, titanium nitride hard masks are currently usually used to replace traditional silicon nitride or oxide layer masks for metal Damascus integrated etching processes.
[0003] However, in the prior art, the sidewall morphology of titanium nitride after etching is too vertical, which makes the line width of the groove too large after the Damascus integrated etching pattern is transferred. In order to protect the line width of Damascus integrated etching, the line width of the titanium nitride hard mask layer groove needs to be increased under the same CD bias (critical dimension deviation), that is, in the existing process, under the same critical dimension deviation conditions, the line width (final CD) in the hard mask needs to be increased to ensure the line width in the final product. This will cause abnormal electrical parameters of subsequent products and reduce wafer yield. Therefore, how to optimize the critical dimension deviation of the metal Damascus integrated process is a technical problem that technicians in this field urgently need to solve. Summary of the invention
[0004] The purpose of the present invention is to provide a metal Damascus integrated etching method, which can optimize the critical dimension deviation of the metal Damascus integrated process; another purpose of the present invention is to provide a chip with a higher yield rate.
[0005] In order to solve the above technical problems, the present invention provides a metal Damascus integrated etching method, comprising:
[0006] When etching the hard mask based on plasma, the hard mask is etched using a target source RF power higher than the standard source RF power and a target bias RF power lower than the standard bias RF power, so that the sidewalls of the etched grooves formed by etching the hard mask are curved sidewalls with a bottom width smaller than a middle width; and the sidewalls of the etched grooves formed based on the standard source RF power and the standard bias RF power are vertical sidewalls;
[0007] A damascene structure with a target line width is etched in a target film layer based on the hard mask with the curved sidewalls.
[0008] Optionally, etching the hard mask using a target source RF power higher than a standard source RF power and using a target bias RF power lower than a standard bias RF power comprises:
[0009] In the main etching process, the hard mask is etched using a first target source RF power higher than a first standard source RF power and a first target bias RF power lower than a first standard bias RF power;
[0010] In the over-etching process, the hard mask is over-etched using a second target source RF power higher than a second standard source RF power and a second target bias RF power lower than a second standard bias RF power.
[0011] Optionally, a difference between the first target source RF power and the first standard source RF power is greater than a difference between the second target source RF power and the second standard source RF power;
[0012] A difference between the first standard bias RF power and the first target bias RF power is smaller than a difference between the second standard bias RF power and the second target bias RF power.
[0013] Optionally, the first target source RF power is equal to the second target source RF power, and the first target bias RF power is equal to the second target bias RF power.
[0014] Optionally, the radio frequency power of the first standard source ranges from 500w to 700w, including endpoint values;
[0015] The first standard bias RF power has a value range of 35W to 45W, including endpoint values;
[0016] The value range of the radio frequency power of the second standard source is 620W to 720W, including the endpoint values;
[0017] The second standard bias RF power has a value range of 40W to 55W, including the endpoint values.
[0018] Optionally, the value range of the first target source radio frequency power is 800w to 1000w, including endpoint values;
[0019] The first target bias RF power has a value range of 30W to 40W, including endpoint values.
[0020] Optionally, the value range of the second target source radio frequency power is 800w to 1000w, including endpoint values;
[0021] The second target bias RF power has a value range of 25W to 40W, including endpoint values.
[0022] Optionally, in the etched groove having the curved sidewall, the bottom width is smaller than the middle width in a value range of 2 nm to 5 nm, including the endpoint values.
[0023] Optionally, before etching the hard mask based on plasma, the method further includes:
[0024] etching the anti-reflective layer based on the patterned photoresist to pattern the anti-reflective layer;
[0025] etching the oxide layer based on the patterned anti-reflective layer to pattern the oxide layer;
[0026] Etching the hard mask includes:
[0027] Based on the patterned oxide layer, the hard mask is etched by plasma.
[0028] The present invention also provides a chip, which is a chip prepared by the metal Damascus integrated etching method provided by any one of the above items.
[0029] The present invention provides a metal Damascus integrated etching method, comprising: when etching a hard mask based on plasma, using a target source RF power higher than a standard source RF power, and using a target bias RF power lower than a standard bias RF power to etch the hard mask, so that the side wall of the etched groove formed by etching the hard mask is a curved side wall with a bottom width less than a middle width; the side wall of the etched groove formed based on the standard source RF power and the standard bias RF power is a vertical side wall; based on the hard mask with a curved side wall, a Damascus structure with a target line width is etched in a target film layer.
[0030] By optimizing the hard mask morphology, an etching groove with curved sidewalls is etched during etching, thereby reducing the line width at the bottom of the etching groove and reducing the difference between the line width in the hard mask and the line width after Damascus integrated etching, thereby optimizing and improving the critical dimensional deviation of the metal Damascus integrated process, so that the critical dimensional deviation is within the normal adjustable range of etching line width, thereby ensuring product quality.
[0031] The present invention also provides a chip, which also has the above-mentioned beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0033] Figure 1 A flow chart of a metal Damascus integrated etching method provided by an embodiment of the present invention;
[0034] Figures 2 to 7 A process flow chart of a specific metal Damascus integrated etching method provided in an embodiment of the present invention.
[0035] In the figure: 1. target film layer, 2. hard mask, 3. oxide layer, 4. anti-reflective layer, 5. photoresist. DETAILED DESCRIPTION
[0036] The core of the present invention is to provide a metal Damascus integrated etching method. In the prior art, the sidewall morphology of titanium nitride after etching is too vertical, which makes the line width of the groove too large after the Damascus integrated etching pattern is transferred. In order to protect the line width of Damascus integrated etching, the line width of the titanium nitride hard mask layer groove needs to be increased under the same CD bias, which will cause abnormal electrical parameters of subsequent products and reduce the wafer yield.
[0037] The present invention provides a metal Damascus integrated etching method, comprising: when etching a hard mask based on plasma, using a target source RF power higher than a standard source RF power, and using a target bias RF power lower than a standard bias RF power to etch the hard mask, so that the sidewalls of the etched grooves formed by etching the hard mask are curved sidewalls with a bottom width less than a middle width; the sidewalls of the etched grooves formed based on the standard source RF power and the standard bias RF power are vertical sidewalls; and etching a Damascus structure with a target line width in a target film layer based on the hard mask with curved sidewalls.
[0038] By optimizing the hard mask morphology, an etching groove with curved sidewalls is etched during etching, thereby reducing the line width at the bottom of the etching groove and reducing the difference between the line width in the hard mask and the line width after Damascus integrated etching, thereby optimizing and improving the critical dimensional deviation of the metal Damascus integrated process, so that the critical dimensional deviation is within the normal adjustable range of etching line width, thereby ensuring product quality.
[0039] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0040] Please refer to Figure 1 , Figure 1 A flow chart of a metal Damascus integrated etching method provided in an embodiment of the present invention.
[0041] See also Figure 1 In an embodiment of the present invention, the metal Damascus integrated etching method includes:
[0042] S101: When etching a hard mask based on plasma, the hard mask is etched using a target source RF power higher than a standard source RF power, and a target bias RF power lower than a standard bias RF power, so that the sidewalls of the etched grooves formed by etching the hard mask are curved sidewalls with a bottom width less than a middle width.
[0043] In an embodiment of the present invention, the sidewalls of the etching groove formed based on the standard source RF power and the standard bias RF power are vertical sidewalls.
[0044] In this embodiment, the hard mask 2 may be a titanium nitride hard mask 2. This embodiment focuses on improving the process of plasma etching the hard mask 2. Before the plasma etching of the hard mask 2, it is usually necessary to transfer the etching pattern through other processes. The specific content will be described in detail in the following invention embodiments and will not be repeated here.
[0045] In this step, the parameters in the process of plasma etching the hard mask 2 are specifically adjusted to adjust the morphology of the etched grooves finally etched. The above-mentioned standard source RF power and standard bias RF power are power parameters set in the prior art. In the prior art, based on the standard source RF power and standard bias RF power, the sidewalls of the etched grooves formed after the hard mask 2 is etched using plasma are vertical sidewalls, that is, the sidewalls do not have a curvature, and specifically present a vertical downward sidewall structure.
[0046] In this step, the hard mask 2 is etched using a target source RF power and a target bias RF power, wherein the target source RF power is higher than the standard source RF power, and the target bias RF power is lower than the standard bias RF power. In the plasma etching process, the source RF power mainly affects the chemical reaction in the etching, and the chemical reaction is isotropic etching; and the bias RF power mainly affects the physical bombardment in the etching, and the physical bombardment is anisotropic etching. Therefore, in this embodiment, based on a target source RF power higher than the standard source RF power and a target bias RF power lower than the standard bias RF power, the isotropic chemical reactions in the etching can be enhanced, and the anisotropic physical bombardment in the etching process can be weakened. A more curved sidewall morphology is obtained under more chemical reactions and less physical bombardment, so that the sidewall of the etched groove finally formed in this step is a curved sidewall with a bottom width less than the middle width.
[0047] A reasonable explanation is that, since isotropic etching is enhanced and anisotropic etching is weakened in this step, in the first half of etching to form the etched groove, the bottom width of the etching will be greater than the top width, thereby forming a protrusion extending toward the center at the etching groove mouth. In the second half of etching to form the etched groove, the protrusion will play a shielding role, blocking part of the plasma from etching the bottom of the etched groove. On this basis, when the target film layer 1 is etched, a curved sidewall with a bottom width less than the middle width can be formed in the formed etched groove. It should be noted that the curved sidewall formed in this embodiment does not require that the sidewall is an arc surface everywhere, but the width of the bottom of the etched groove formed by it needs to be less than the width of the middle part, and there is a protrusion extending toward the center at the etching groove mouth, so that the sidewall as a whole is approximately a curved arc surface.
[0048] S102: etching a damascene structure having a target line width in a target film layer based on the hard mask having the curved sidewalls.
[0049] In this step, the target film layer 1 is etched based on the hard mask 2 with curved sidewalls to etch a damascene structure with a target line width in the target film layer 1. For details on transferring the pattern in the hard mask 2 to the target film layer 1 and etching the target film layer 1 based on the hard mask 2, reference can be made to the prior art, and no further description will be given here.
[0050] A metal Damascus integrated etching method provided in an embodiment of the present invention optimizes the morphology of a hard mask 2 and etches an etching groove with a curved sidewall during etching, thereby reducing the line width at the bottom of the etching groove and reducing the difference between the line width in the hard mask 2 and the line width after Damascus integrated etching, thereby optimizing and improving the critical dimensional deviation of the metal Damascus integrated process, so that the critical dimensional deviation is within the adjustable range of the normal etching line width, thereby ensuring product quality.
[0051] The specific contents of the metal Damascus integrated etching method provided by the present invention will be described in detail in the following invention embodiments.
[0052] Please refer to Figures 2 to 7 , Figures 2 to 7 A process flow chart of a specific metal Damascus integrated etching method provided in an embodiment of the present invention.
[0053] See also Figure 2 In an embodiment of the present invention, the metal Damascus integrated etching method includes:
[0054] S201: etching the anti-reflection layer based on the patterned photoresist to pattern the anti-reflection layer.
[0055] See also Figure 3 as well as Figure 4 Before this step, an oxide layer 3 is specifically set on the surface of the hard mask 2, an anti-reflection layer 4 is set on the surface of the oxide layer 3, and a photoresist 5 is set on the surface of the anti-reflection layer 4. In this embodiment, the anti-reflection layer 4, the oxide layer 3, and the hard mask 2 are etched in sequence, and finally the pattern is transferred to the target film layer 1. In this step, the photoresist 5 is first patterned, and the anti-reflection layer 4 is etched based on the patterned photoresist 5 to achieve patterning of the anti-reflection layer 4. This process can refer to the prior art, and the specific pattern needs to be set according to the actual situation, and is not specifically limited here.
[0056] S202: etching the oxide layer based on the patterned anti-reflective layer to pattern the oxide layer.
[0057] See also Figure 5 In this step, the oxide layer 3 is etched based on the patterned anti-reflection layer 4 to achieve patterning of the oxide layer 3. This process can refer to the prior art and is not specifically limited here.
[0058] Correspondingly, the subsequent process of etching the hard mask 2 includes: etching the hard mask 2 by plasma based on the patterned oxide layer 3 .
[0059] S203: In the main etching process, a first target source RF power higher than a first standard source RF power and a first target bias RF power lower than a first standard bias RF power are used to etch the hard mask.
[0060] See also Figure 6 , usually, the process of plasma etching the hard mask 2 can be specifically divided into a main etching process and an over-etching process, wherein the main etching process is mainly used to form etching grooves, and the over-etching process is mainly to ensure that the above-mentioned etching grooves can be formed at various positions, that is, over-etching is to ensure that the etching grooves in the most subtle (weak) places of the etching pattern can also be completely etched. This step is specifically for the main etching process, in which the hard mask 2 will be etched with a first target source RF power and a first target bias RF power, wherein the first target source RF power is higher than the above-mentioned first standard source RF power, and the first target bias RF power is lower than the first standard bias RF power. The first standard source RF power and the first standard bias RF power are power parameters set when etching an etching groove with vertical sidewalls during the main etching process in the prior art. In this step, the main etching is performed based on a first target source RF power higher than the first standard source RF power and a first target bias RF power lower than the first standard bias RF power in the main etching process. This can enhance various isotropic chemical reactions in the main etching and weaken various anisotropic physical bombardment effects during the main etching process, so that the sidewalls of the etching grooves finally formed in this step are curved sidewalls with a bottom width less than a middle width.
[0061] S204: in the over-etching process, the hard mask 2 is over-etched by using a second target source RF power higher than the second standard source RF power and a second target bias RF power lower than the second standard bias RF power.
[0062] This step is specifically aimed at the over-etching process, in which the hard mask 2 will be over-etched with the second target source RF power and the second target bias RF power, wherein the second target source RF power is higher than the second standard source RF power, and the second target bias RF power is lower than the second standard bias RF power. The second standard source RF power and the second standard bias RF power are power parameters set when etching an etched groove with vertical sidewalls during the over-etching process in the prior art, and this step will be based on the second target source RF power higher than the second standard source RF power and the second target bias RF power lower than the second standard bias RF power in the over-etching process. The over-etching can be enhanced by various isotropic chemical reactions in the over-etching and weaken various anisotropic physical bombardment effects in the over-etching process, so that this step ensures that the sidewalls of the etched groove formed are curved sidewalls with a bottom width less than the middle width.
[0063] In this embodiment, in order to ensure that the side walls of the formed etching grooves are curved side walls with a bottom width less than the middle width after the main etching process and the over-etching process, in this embodiment, the difference between the first target source RF power and the first standard source RF power can be set to be greater than the difference between the second target source RF power and the second standard source RF power, that is, the change in source RF power in the main etching process of the present application will be greater than the change in source RF power in the over-etching process.
[0064] And the difference between the first standard bias RF power and the first target bias RF power is smaller than the difference between the second standard bias RF power and the second target bias RF power. That is, the change in bias RF power in the main etching process of the present application will be smaller than the change in bias RF power in the over-etching process.
[0065] Specifically, in this embodiment, the first target source RF power can be set equal to the second target source RF power, and the first target bias RF power can be set equal to the second target bias RF power, so as to simplify the parameter adjustment process during the entire etching process, while ensuring that the side wall of the formed etching groove is a curved side wall with a bottom width less than the middle width.
[0066] Specifically, in this embodiment, the first standard source RF power has a value range of 500w to 700w, including the endpoint value; the first standard bias RF power has a value range of 35w to 45w, including the endpoint value; the second standard source RF power has a value range of 620w to 720w, including the endpoint value; the second standard bias RF power has a value range of 40w to 55w, including the endpoint value. That is, in order to form an etched groove with a vertical sidewall in the prior art, the source RF power at each stage and the bias RF power at each stage need to meet the above range.
[0067] In this embodiment, the first target source RF power has a value range of 800w to 1000w, including the endpoint value; the first target bias RF power has a value range of 30w to 40w, including the endpoint value. The second target source RF power has a value range of 800w to 1000w, including the endpoint value; the second target bias RF power has a value range of 25w to 40w, including the endpoint value. That is, in this embodiment, in order to form the etched groove with the above-mentioned curved sidewall, the source RF power at each stage and the bias RF power at each stage need to meet the above-mentioned range.
[0068] Preferably, in this embodiment, compared with the prior art, the source RF power of the main etching step is adjusted from 600 W to 800 W, and the bias RF power is adjusted from 35 W to 30 W, that is, the first standard source RF power can be 600 W, the first target source RF power can be 800 W, the first standard bias RF power can be 35 W, and the first target bias RF power can be 30 W.
[0069] Correspondingly, compared with the prior art, in this embodiment, the source RF power of the over-etching step is adjusted from 720W to 800W, and the bias RF power is adjusted from 45W to 30W, that is, the second standard source RF power can be 720W, the second target source RF power can be 800W, the second standard bias RF power can be 45W, and the second target bias RF power can be 30W.
[0070] Based on the adjustment of the above-mentioned RF powers, in the etching groove with the curved sidewall in this embodiment, the bottom width is smaller than the value range of the middle width of 2nm to 5nm, including the end value. That is, in this embodiment, the bottom line width of the etching groove can be reduced by 2nm to 5nm to ensure the optimization and improvement of the critical dimension deviation of the metal Damascus integrated process, so that the critical dimension deviation is within the normal etching line width adjustable range to ensure product quality.
[0071] S205: etching a damascene structure having a target line width in a target film layer based on the hard mask having the curved sidewalls.
[0072] See also Figure 7 In this step, a Damascus structure with a target line width can be obtained. This step is basically the same as S102 in the above invention embodiment. For details, please refer to the above invention embodiment, and no further description will be given here.
[0073] A metal Damascus integrated etching method provided in an embodiment of the present invention optimizes the morphology of a hard mask 2 and etches an etching groove with a curved sidewall during etching, thereby reducing the line width at the bottom of the etching groove and reducing the difference between the line width in the hard mask 2 and the line width after Damascus integrated etching, thereby optimizing and improving the critical dimensional deviation of the metal Damascus integrated process, so that the critical dimensional deviation is within the adjustable range of the normal etching line width, thereby ensuring product quality.
[0074] The present invention also provides a chip, which is a chip prepared by a metal Damascus integrated etching method provided by any of the above embodiments. Since the chip provided by this embodiment is prepared by the above-mentioned metal Damascus integrated etching method, and the above-mentioned etching method can effectively ensure product quality and increase product yield. Correspondingly, a chip provided by this embodiment can have higher product quality and higher yield. The specific structure of a chip provided by this embodiment can be set according to actual conditions, and is not specifically limited here.
[0075] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
[0076] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0077] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0078] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0079] The above is a detailed introduction to a metal Damascus integrated etching method and a chip provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A metal Damascus integrated etching method, characterized in that: include: When etching the hard mask based on plasma, the hard mask is etched using a target source RF power higher than a standard source RF power and a target bias RF power lower than a standard bias RF power, so that the sidewall of the etched groove formed by etching the hard mask is a curved sidewall with a bottom width smaller than a middle width; The sidewalls of the etching groove formed based on the standard source RF power and the standard bias RF power are vertical sidewalls; A damascene structure with a target line width is etched in a target film layer based on the hard mask with the curved sidewalls.
2. The method according to claim 1, characterized in that The etching of the hard mask using a target source RF power higher than a standard source RF power and a target bias RF power lower than a standard bias RF power comprises: In the main etching process, the hard mask is etched using a first target source RF power higher than a first standard source RF power and a first target bias RF power lower than a first standard bias RF power; In the over-etching process, the hard mask is over-etched using a second target source RF power higher than a second standard source RF power and a second target bias RF power lower than a second standard bias RF power.
3. The method according to claim 2, characterized in that The difference between the first target source RF power and the first standard source RF power is greater than the difference between the second target source RF power and the second standard source RF power; A difference between the first standard bias RF power and the first target bias RF power is smaller than a difference between the second standard bias RF power and the second target bias RF power.
4. The method according to claim 3, characterized in that The first target source RF power is equal to the second target source RF power, and the first target bias RF power is equal to the second target bias RF power.
5. The method according to claim 2, characterized in that: The radio frequency power of the first standard source has a value range of 500w to 700w, including the endpoint values; The first standard bias RF power has a value range of 35W to 45W, including endpoint values; The value range of the radio frequency power of the second standard source is 620W to 720W, including the endpoint values; The second standard bias RF power has a value range of 40W to 55W, including the endpoint values.
6. The method according to claim 5, characterized in that The value range of the first target source radio frequency power is 800w to 1000w, including the endpoint value; The first target bias RF power has a value range of 30W to 40W, including endpoint values.
7. The method according to claim 5, characterized in that The value range of the second target source radio frequency power is 800w to 1000w, including the endpoint value; The second target bias RF power has a value range of 25W to 40W, including endpoint values.
8. The method according to claim 1, characterized in that In the etching groove with the curved sidewall, the bottom width is smaller than the middle width in the range of 2nm to 5nm, including the endpoint values.
9. The method according to claim 1, characterized in that: Prior to plasma-based hard mask etching, it also includes: etching the anti-reflective layer based on the patterned photoresist to pattern the anti-reflective layer; etching the oxide layer based on the patterned anti-reflective layer to pattern the oxide layer; Etching the hard mask includes: Based on the patterned oxide layer, the hard mask is etched by plasma.
10. A chip, characterized in that: A chip prepared by a metal Damascus integrated etching method provided by any one of claims 1 to 9.