Method for manufacturing an interconnect structure and semiconductor device

Abstract

The present application discloses a manufacturing method of an interconnect structure and a semiconductor device. The method includes: sequentially forming an etch stop layer and a second oxide layer on a first oxide layer, wherein the first oxide layer includes a first connection structure; forming a first contact hole penetrating through the second oxide layer and the etch stop layer; detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure; performing lateral etching on the bottom of the first contact hole so that the surface of the corresponding first connection structure is exposed via the bottom of a second contact hole; filling a conductive material in the second contact hole to form a second connection structure. The manufacturing method of the interconnect structure and the semiconductor device provided by the present application aims to increase the lateral dimension of the bottom surface of the second connection structure, so as to achieve connection between the second connection structure and the first connection structure that could not be connected originally, and improve the yield of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a manufacturing method of an interconnect structure and a semiconductor device. Background Art

[0002] A semiconductor chip includes multiple layers of overlapping circuits, and each layer of the circuit is formed by a lithography process. The lithography process is a process of developing the pattern on a mask plate onto a mask layer and then transferring it from the mask layer to a wafer. To ensure the performance of the semiconductor chip, it is necessary to ensure the alignment of each front layer and the subsequent layer in overlay alignment. As shown in Figure 1 , however, affected by marking, measurement, etching, etc., the semiconductor chip cannot be aligned layer by layer with 100% accuracy.

[0003] To ensure high overlay accuracy between each front layer and the subsequent layer of the semiconductor chip, after-develop inspection (ADI) is required after the development of the lithography process, and after-etch inspection (AEI) is required after the etching.

[0004] However, as the device size decreases, in semiconductor devices, the alignment between the conductive structure of the subsequent layer and the conductive structure of the front layer becomes more challenging. There are often errors in overlay alignment, resulting in the inability to connect between the conductive structure of the subsequent layer and the conductive structure of the front layer. As shown in Figure 2 and Figure 3 , which causes a loss in the yield of semiconductor devices. Summary of the Invention

[0005] In view of the above problems, the present application provides a manufacturing method of an interconnect structure and a semiconductor device, aiming to increase the lateral dimension of the bottom surface of the second connection structure, so as to achieve connection between the originally unconnected second connection structure and the first connection structure, and improve the yield of semiconductor devices.

[0006] According to a first aspect of the present invention, there is provided a manufacturing method of an interconnect structure, including: sequentially forming an etch stop layer and a second oxide layer on a first oxide layer, wherein the first oxide layer includes a first connection structure; forming a first contact hole penetrating through the second oxide layer and the etch stop layer; detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure; performing lateral etching on the bottom of the first contact hole, so that the surface of the corresponding first connection structure is exposed through the bottom of the second contact hole, and the bottom of the first contact hole forms the second contact hole after lateral etching; filling a conductive material in the second contact hole to form a second connection structure, wherein the lateral etching dimension of the bottom of the first contact hole is not less than the error value.

[0007] Optionally, the step of laterally etching the bottom of the first contact hole includes: laterally expanding the bottom of the first contact hole by an etching process to form the second contact hole; detecting whether the bottom of the second contact hole exposes the upper surface of the first connection structure; if the bottom of the second contact hole does not expose the upper surface of the first connection structure, repeating the aforementioned steps of lateral expansion and detection; if the bottom of the second contact hole exposes the upper surface of the first connection structure, completing the lateral expansion of the bottom of the first contact hole.

[0008] Optionally, after laterally etching the bottom of the first contact hole, the lateral dimension of the first contact hole in the etch stop layer is enlarged, and the bottom radius of the second contact hole increases by a third distance compared to the bottom radius of the first contact hole, and the third distance is not less than the error value.

[0009] Optionally, the cross-section of the first contact hole is an inverted trapezoid that is wider at the top and narrower at the bottom.

[0010] Optionally, the bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole.

[0011] Optionally, the bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes.

[0012] Optionally, during the etching of the etch stop layer, the etchant is a phosphoric acid solution or a bias-free sulfur hexafluoride gas.

[0013] Optionally, between the step of forming the first contact hole that penetrates the second oxide layer and the etch stop layer and the step of detecting the error value between the bottom of the first contact hole and the top of the corresponding first connection structure, it further includes: detecting whether the bottom of the first contact hole exposes the upper surface of the first connection structure; if the bottom of the first contact hole does not expose the upper surface of the first connection structure, detecting the error value between the bottom of the first contact hole and the top of the corresponding first connection structure.

[0014] Optionally, before the step of sequentially forming the etch stop layer and the second oxide layer on the first oxide layer, it further includes: forming a first oxide layer on the semiconductor structure; forming a first connection structure in the first oxide layer, where the number of the first connection structures is at least one.

[0015] According to another aspect of the present invention, there is provided a semiconductor device, comprising: a first oxide layer; a first connection structure located in the first oxide layer, the upper surface of the first oxide layer exposing the upper surface of the first connection structure; an etch stop layer located on the first oxide layer; a second oxide layer located on the etch stop layer; a second connection structure penetrating through the second oxide layer and the etch stop layer, the bottom of the second connection structure being connected to the upper surface of the first connection structure; wherein, the diameter of the portion of the second connection structure located in the etch stop layer is greater than the bottom diameter of the portion of the second connection structure located in the second oxide layer.

[0016] For the manufacturing method of an interconnect structure and a semiconductor device according to an embodiment of the present invention, a first connection structure is formed in a first oxide layer, and then an etch stop layer and a second oxide layer are formed on the first oxide layer. After forming a first contact hole penetrating through the second oxide layer and the etch stop layer, a post-etch inspection method is used to determine whether the upper surface of the corresponding first connection structure is exposed by the first contact hole. If not, what is the detection error value? According to the detected error value, lateral etching is performed on the bottom of the first contact hole located in the etch stop layer to increase the lateral dimension of the bottom of the first contact hole, so that the second contact hole with an enlarged bottom lateral dimension can expose a part of the surface of the first connection structure, and thus the conductive material deposited in the second contact hole can contact the first connection structure subsequently to achieve electrical connection between the first connection structure and the second connection structure. The method of enlarging the bottom lateral dimension of the first contact hole after forming the first contact hole enables an originally open-circuited semiconductor device to also achieve electrical connection, thereby improving the yield of the device.

[0017] Furthermore, for the manufacturing method of an interconnect structure and a semiconductor device according to an embodiment of the present invention, during the process of performing lateral etching on the bottom of the first contact hole, anisotropic etching is used, such that this etching process only occurs in the etch stop layer. For the entire contact hole, only the lateral dimension of the bottom of the contact hole changes, while the dimension of the contact hole located in the second oxide layer does not change, thereby reducing the probability of unnecessary connection between adjacent second connection structures.

[0018] Furthermore, for the manufacturing method of an interconnect structure and a semiconductor device according to an embodiment of the present invention, during the process of performing lateral etching on the bottom of the contact hole using anisotropic etching, the etching distance is, for example, greater than the error value, but the bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole, which can avoid the problem of connection between adjacent contact holes caused by the enlarged bottom lateral dimension. In another embodiment, the bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes, thereby avoiding the problem of connection between adjacent contact holes caused by the enlarged bottom lateral dimension.

[0019] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device according to the embodiments of the present invention, during the process of laterally etching the bottom of the first contact hole, a step-by-step etching plus detection method is adopted. After each etching, the contact hole is detected. On the one hand, it is confirmed whether the bottom of the second contact hole after etching exposes the upper surface of the first connection structure. On the other hand, the etching size can be well controlled, the probability of communication between adjacent second contact holes is reduced, and the reliability of the device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Through the following description of the embodiments of the present application with reference to the accompanying drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0021] Figure 1 A schematic structural diagram of the interconnect structure of an ideal semiconductor device is shown;

[0022] Figure 2 A schematic structural diagram of an error occurring in the interconnect structure of a semiconductor device in the prior art is shown;

[0023] Figure 3 A schematic electron microscope structural diagram of an error occurring in the interconnect structure of a semiconductor device in the prior art is shown;

[0024] Figure 4 A flowchart of the manufacturing method of the interconnect structure according to the embodiments of the present invention is shown;

[0025] Figures 5 to 8 Cross-sectional views of semiconductor devices at various stages in the manufacturing method of the interconnect structure according to the first embodiment of the present invention are shown;

[0026] Figure 9 A schematic structural diagram of the interconnect structure according to the second embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0029] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present application described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there may also be intermediate elements. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0031] The present application will be described in more detail below with reference to the drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. The present application can be presented in various forms, and some examples will be described below.

[0032] The present application can be presented in various forms, and some examples will be described below.

[0033] Figure 4 A flowchart showing a method for manufacturing an interconnect structure according to an embodiment of the present invention is shown; Figures 5 to 8 A cross-sectional view of a semiconductor device at each stage in a method for manufacturing an interconnect structure according to a first embodiment of the present invention is shown.

[0034] An interconnect structure refers to a structure that connects different devices, circuits, and functional modules together. These connections are usually achieved through materials such as metal wires, multi-layer metal layers, and multi-layer insulating layers to achieve signal transmission and electrical connection between various parts inside the device. The interconnect structure plays a crucial role in an integrated circuit, which determines the performance, power consumption, and reliability of the device. A reasonably designed interconnect structure can improve the performance and reliability of the device, while reducing power consumption and cost.

[0035] In the present application, an interconnect structure is, for example, a connection structure between a conductive channel and other conductive channels, different devices, circuits, functional modules, etc. Of course, it can also be a connection between a conductive channel and other structures commonly used in the art. That is, the interconnect structure generally represents a connection between two structures. In the present application, for example, one of the two structures is a conductive channel, and the other structure is not limited and can be any structure that needs to be electrically connected to other structures.

[0036] In this embodiment, a semiconductor device refers to an electronic device made of semiconductor materials, which is used to control the transmission of current, voltage, and signals. Specifically, the semiconductor device includes a first connection structure and a second connection structure that need to achieve electrical connection. Specifically, the semiconductor device includes, for example, diodes, transistors, field effect transistors, integrated circuits, etc.

[0037] Reference Figures 4 to 8 , the manufacturing method of the interconnect structure of the present application includes the following steps:

[0038] Step S201: Form a first oxide layer and form a first connection structure in the first oxide layer.

[0039] In this step, reference Figure 5 , a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to deposit an oxide on a semiconductor structure (not shown in the figure) to form a first oxide layer 110.

[0040] Then, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, etc., is used to etch the first oxide layer 110 through a mask to form a through hole in the first oxide layer 110.

[0041] Furthermore, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to form a first connection structure 140 in the through hole of the first oxide layer 110.

[0042] In this embodiment, the semiconductor structure can be a substrate or a semiconductor on which some device structures have been formed. If the semiconductor structure is a substrate, the first connection structure can be, for example, an active area (AA), a conductive channel, etc.

[0043] In other embodiments, the first oxide layer 110 can also be replaced with a substrate. That is Figure 5 110 in is the substrate, and 140 can be an active area or other device structures in the substrate.

[0044] Step S202: Sequentially form an etch stop layer and a second oxide layer on the first oxide layer.

[0045] In this step, referenceFigure 5 Using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., a nitride is deposited on the first oxide layer 110 to form an etch stop layer 120. Further, using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., an oxide material is deposited on the etch stop layer 120 to form a second oxide layer 130.

[0046] In this embodiment, the material of the etch stop layer 120 is, for example, silicon nitride. The etch stop layer 120 can improve the selectivity of etching in subsequent steps, enabling etching to occur only in the second oxide layer 130 on the etch stop layer, avoiding over-etching, and protecting the first oxide layer 110 below the etch stop layer 120 from damage.

[0047] Step S203: Form a first contact hole penetrating the etch stop layer and the second oxide layer.

[0048] In this step, referring to Figure 5 , using an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or gas-phase etching, etc., the second oxide layer 130 and the etch stop layer 120 are etched through a mask to form a first contact hole 101 in the second oxide layer 130 and the etch stop layer 120.

[0049] In this embodiment, the cross-sectional shape of the first contact hole 101 is, for example, an inverted trapezoid, which has a cross-sectional dimension that is wider at the top and narrower at the bottom. Specifically, the diameter of the first contact hole 101 at the upper surface of the second oxide layer 130 is a first distance D1, and the diameter at the upper surface of the first oxide layer 110 is a second distance D2, and the first distance D1 is greater than the second distance D2.

[0050] In a good device, the first contact hole 101 needs to correspond to the position of the first connection structure in the first oxide layer 110 such that the bottom surface of the first contact hole 101 exposes the upper surface of the first connection structure 140.

[0051] Step S204: Detect the error value between the bottom of the contact hole and the top of the corresponding first connection structure.

[0052] In this step, referring to Figure 6 , the overlay offset between the first contact hole 101 and the first connection structure 140 is detected and measured via the method of After etch Inspection (AEI) to obtain an error value D3.

[0053] After etch Inspection (AEI) is a process that checks the critical dimensions of a product during the etching process to ensure the quality and accuracy of the etching process.

[0054] In this embodiment, when the bottom of the first contact hole 101 does not expose a part of the upper surface of the corresponding first connection structure 140, it means that an electrical connection between the conductive material and the first connection structure 140 cannot be achieved after filling the conductive material in the first contact hole 101. Therefore, there is an error between the first contact hole 101 and the first connection structure.

[0055] The error value D3 in this embodiment, for example, refers to the minimum distance between the bottom surface of the first contact hole 101 and the upper surface of the first connection structure 140, that is, in the upper surface of the first oxide layer 110, the distance between the closest edge of the first connection structure 140 and the first contact hole 101, as Figure 6 shown.

[0056] Step S205: Perform lateral etching on the bottom of the first contact hole so that the surface of the corresponding first connection structure is exposed through the bottom of the second contact hole.

[0057] In this step, referring to Figure 7 , a non-isotropic etching method with a high selectivity ratio is used to perform lateral etching on the bottom of the first contact hole 101 located in the etch stop layer 120, so as to expand the lateral dimension of the first contact hole 101 located in the etch stop layer 120. Specifically, the bottom radius of the first contact hole 101 increases by a third distance D4, and the third distance D4 is not less than the error value D3, that is, the lateral etching size of the bottom of the first contact hole 101 is not less than the error value D3. For the convenience of describing the contact hole before and after the bottom lateral etching, the contact hole after the lateral etching is called the second contact hole 102. The part of the second contact hole 102 located in the second oxide layer 130 is called the upper part of the second contact hole 102, and the part of the second contact hole 102 located in the etch stop layer 120 is called the lower part of the second contact hole 102.

[0058] In this embodiment, the non-isotropic etching, for example, uses wet etching, and the solution for wet etching uses phosphoric acid solution H3PO4. Gas-phase etching can also be used, and the reaction gas in gas-phase etching, for example, uses unbiased sulfur hexafluoride SF6 gas. This is because the phosphoric acid solution H3PO4 and sulfur hexafluoride SF6 gas have a high selectivity ratio for the etch stop layer of silicon nitride SiN material. When laterally expanding the bottom surface of the contact hole, the phosphoric acid solution H3PO4 and sulfur hexafluoride SF6 gas are not likely to react with the oxide layer, but are likely to react with the silicon nitride SiN material, so the influence on the part of the contact hole located in the second oxide layer 130 during the etching process of expanding the bottom surface size of the contact hole is very small.

[0059] The third distance D4 increased during the lateral etching of the lower part of the second contact hole 102 is greater than the error value D3 measured between the first contact hole 101 and the first connection structure 140 in the previous step. Therefore, the bottom surface of the second contact hole 102 can expose the upper surface of the first connection structure. As shown in the virtual circle A in Figure 7 .

[0060] Among them, during the process of lateral etching to form the lower part of the second contact hole 102, a step-by-step etching method can be adopted to gradually laterally expand the size of the lower part of the second contact hole 102, thereby avoiding excessive lateral expansion of the size of the lower part of the second contact hole 102. During the step-by-step etching process, first, the lateral size of the lower part of the second contact hole 102 is first expanded through an etching process, and then it is detected whether the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102; if not exposed, the lateral size of the lower part of the second contact hole 102 is secondarily expanded through an etching process, and then it is detected whether the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102; the steps of expansion and detection are repeated multiple times until the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102, and the exposed size is not less than a preset value.

[0061] Among them, in the steps of step-by-step etching, detection processes commonly used in semiconductor manufacturing processes such as scanning electron microscopy (SEM) and post-etch inspection (AEI) are used to detect the semiconductor structure after each etching to determine whether the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102, and to detect whether there is any residue during the etching process.

[0062] In this way, by using the method of step-by-step etching plus detection to expand the lateral size of the lower part of the second contact hole 102, the lateral size of the lower part of the second contact hole 102 can be more accurately controlled, and the problem of connection between the lower parts of adjacent second contact holes 102 can be reduced. In addition, the monitoring step after each etching can also be used to determine whether there is any residue in the etching.

[0063] Furthermore, the lower diameter of the second contact hole 102 located on the upper surface of the first oxide layer 101 is the fourth distance (D2 + 2D4), and the top diameter of the second contact hole 102 located on the upper surface of the second oxide layer 130 is the same as the top diameter of the first contact hole 101, both being the first distance D1. And in order to ensure that there is no short circuit between the lower parts of adjacent contact holes in the second oxide layer 130, in a preferred embodiment, it is restricted that the bottom diameter of the second contact hole 102, the fourth distance (D2 + 2D4) ≤ the top diameter of the second contact hole 102, the first distance D1.

[0064] Step S206: Fill the second contact hole with a conductive material.

[0065] In this step, with reference to Figure 8 , a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is adopted to fill the second contact hole 102 with a conductive material and perform surface planarization treatment, so as to form a second connection structure 250 in the second contact hole 102.

[0066] Since the diameter of the part of the second connection structure 250 located in the etch stop layer 120 is laterally enlarged, the first connection structure 140 and the second connection structure 250 that could not be connected originally can be connected, that is, remedies can be made even in the case of errors, improving the yield of the device.

[0067] Furthermore, between step S203 and step S204 of this embodiment, it may further include:

[0068] Step S2031: Detect whether the bottom of the first contact hole exposes the upper surface of the first connection structure.

[0069] Although there is an offset during the etching process, the offset amount also has different magnitudes. In the case of no offset, the bottom of the first contact hole 101 exposes the upper surface of the first connection structure 140; in the case of a small offset amount, the bottom of the first contact hole 101 exposes, for example, part of the upper surface of the first connection structure 140 and part of the upper surface of the first oxide layer 110; in the case of a large offset amount, the bottom of the first contact hole 101 exposes, for example, the upper surface of the first oxide layer 110.

[0070] Therefore, in this step, it is determined whether to execute step S204 by detecting whether the bottom of the first contact hole 101 exposes the upper surface of the first connection structure 140. Specifically, in the case where the bottom of the first contact hole 101 exposes, for example, the upper surface of the first oxide layer 110, that is, does not expose the upper surface of the first connection structure 140, step S204 is executed.

[0071] Figure 9 FIG. shows a schematic structural diagram of an interconnect structure according to a second embodiment of the present invention.

[0072] With reference to Figure 9 , in this embodiment, in order to increase the contact area between the second connection structure 250 and the first connection structure 140, when determining the distance between adjacent first contact holes 101 on the upper surface of the second oxide layer 130, the third distance D4 for lateral etching of the etch stop layer 120 can be appropriately increased.

[0073] Specifically, in one embodiment, the distance between adjacent first contact holes 101 on the upper surface of the second oxide layer 130 refers to, for example, the distance between the centers of two adjacent contact holes. The fifth distance D5 refers to, for example, half of the distance between the centers of two adjacent contact holes. It can be considered that as long as the bottom radius of the second contact hole, the fourth distance (1 / 2D2 + D4) ≤ the fifth distance D5, there will be no short - circuit problem between adjacent second connection structures. At this time, the bottom radius of the second contact hole, the fourth distance (1 / 2D2 + D4) is greater than the top surface radius of the second contact hole, the first distance D1.

[0074] Of course, during the process of laterally etching the part of the contact hole located in the etch - stop layer 120, it is also necessary to ensure the corresponding relationship between the contact hole and the corresponding first connection structure 140 to avoid the problem that one contact hole exposes the upper surface of the first connection structure 140 corresponding to its adjacent contact hole.

[0075] The present application also provides a semiconductor device, including an interconnect structure formed by using the manufacturing method of the foregoing interconnect structure. Specifically, the semiconductor device includes: a first oxide layer 110; a first connection structure 140 located in the first oxide layer 110, and the upper surface of the first oxide layer 110 exposes the upper surface of the first connection structure 140; an etch - stop layer 120 located on the first oxide layer 110; a second oxide layer 130 located on the etch - stop layer 120; a second connection structure 250 penetrating through the second oxide layer 130 and the etch - stop layer 120, and the bottom of the second connection structure 250 is connected to the upper surface of the first connection structure 140; wherein, the diameter of the part of the second connection structure 250 located in the etch - stop layer 120 is greater than the bottom diameter of the part of the second connection structure 250 located in the second oxide layer 130.

[0076] According to the manufacturing method of the interconnect structure and the semiconductor device of the embodiments of the present invention, a first connection structure is formed in the first oxide layer, then an etch - stop layer and a second oxide layer are formed on the first oxide layer. After forming the first contact hole penetrating through the second oxide layer and the etch - stop layer, the method of post - etching inspection is used to determine whether the first contact hole exposes the upper surface of the corresponding first connection structure. If not, what is the detection error value? According to the detected error value, the bottom of the first contact hole located in the etch - stop layer is laterally etched to increase the lateral dimension of the bottom of the first contact hole, so that the second contact hole with an enlarged bottom lateral dimension can expose part of the surface of the first connection structure, so that the conductive material deposited in the second contact hole can contact the first connection structure later to realize the electrical connection between the first connection structure and the second connection structure. The method of enlarging the bottom lateral dimension of the first contact hole after forming the first contact hole enables the originally open - circuit semiconductor device to also achieve electrical connection, thereby improving the yield of the device.

[0077] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device according to the embodiment of the present invention, during the process of laterally etching the bottom of the first contact hole, an anisotropic etching is adopted, so that the etching process only occurs in the etch stop layer. For the entire contact hole, only the lateral dimension of the bottom of the contact hole changes, while the dimension of the contact hole located in the second oxide layer does not change, thereby reducing the probability of unnecessary connection between adjacent second connection structures.

[0078] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device according to the embodiment of the present invention, during the process of laterally etching the bottom of the contact hole by using anisotropic etching, the etching distance is, for example, greater than the error value, but the bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole, so as to avoid the connection problem between adjacent contact holes caused by the expansion of the lateral dimension at the bottom. In another embodiment, the bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes, thereby avoiding the connection problem between adjacent contact holes caused by the expansion of the lateral dimension at the bottom.

[0079] As described above in accordance with the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, according to the above description, many modifications and variations can be made. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A manufacturing method of an interconnect structure, comprising: sequentially forming an etch stop layer and a second oxide layer on a first oxide layer, wherein the first oxide layer includes a first connection structure; forming a first contact hole penetrating through the second oxide layer and the etch stop layer; detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure; performing lateral etching on the bottom of the first contact hole such that the surface of the corresponding first connection structure is exposed via the bottom of a second contact hole, and the bottom of the first contact hole forms the second contact hole after lateral etching; filling a conductive material in the second contact hole to form a second connection structure, wherein the size of the lateral etching of the bottom of the first contact hole is not less than the error value; the step of performing lateral etching on the bottom of the first contact hole includes: using an etching process to laterally expand the bottom of the first contact hole to form the second contact hole; detecting whether the bottom of the second contact hole exposes the upper surface of the first connection structure; if the bottom of the second contact hole does not expose the upper surface of the first connection structure, repeating the aforementioned steps of lateral expansion and detection; if the bottom of the second contact hole exposes the upper surface of the first connection structure, completing the lateral expansion of the bottom of the first contact hole.

2. The manufacturing method of the interconnect structure according to claim 1, wherein, After performing lateral etching on the bottom of the first contact hole, the lateral dimension of the first contact hole in the etch stop layer expands, and the bottom radius of the second contact hole increases by a third distance compared to the bottom radius of the first contact hole, and the third distance is not less than the error value.

3. The manufacturing method of the interconnect structure according to claim 2, wherein, The cross-section of the first contact hole is an inverted trapezoid that is wider at the top and narrower at the bottom.

4. The manufacturing method of the interconnect structure according to claim 3, wherein, The bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole.

5. The manufacturing method of the interconnect structure according to claim 3, wherein, The bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes.

6. The manufacturing method of the interconnect structure according to claim 1, wherein, During the etching of the etch stop layer, the etchant uses a phosphoric acid solution or a sulfur hexafluoride gas without bias voltage.

7. The manufacturing method of the interconnect structure according to claim 1, wherein, Between the step of forming a first contact hole penetrating through the second oxide layer and the etch stop layer and the step of detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure, it further includes: detecting whether the bottom of the first contact hole exposes the upper surface of the first connection structure; if the bottom of the first contact hole does not expose the upper surface of the first connection structure, detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure.

8. The manufacturing method of the interconnect structure according to claim 1, wherein, Before the step of sequentially forming an etch stop layer and a second oxide layer on the first oxide layer, it further includes: forming a first oxide layer on a semiconductor structure; forming a first connection structure in the first oxide layer, wherein the number of the first connection structures is at least one.

9. A semiconductor device formed by using the manufacturing method according to any one of claims 1-8, comprising: a first oxide layer; a first connection structure located in the first oxide layer, and the upper surface of the first oxide layer exposes the upper surface of the first connection structure; an etch stop layer located on the first oxide layer; a second oxide layer located on the etch stop layer; The second connection structure penetrates through the second oxide layer and the etch stop layer, and the bottom of the second connection structure is connected to the upper surface of the first connection structure; Wherein, the diameter of the part of the second connection structure located in the etch stop layer is larger than the bottom surface diameter of the part of the second connection structure located in the second oxide layer.

Images