Signal transmission circuit and power conversion device

Abstract

The invention relates to a signal transmission circuit and a power conversion device. The purpose of the present invention is to appropriately transmit signals. The signal transmission circuit includes a first circuit, a transformer, and a second circuit. The first circuit receives a first signal, generates a transmission signal corresponding to a change in a logic value of the first signal, and operates with a first potential as a reference. The transformer has a first coil to which the transmission signal is input from the first circuit, and a second coil inductively coupled to the first coil and outputting a pair of reception signals. The second circuit receives a pair of reception signals from the second coil, generates a second signal by comparing the potential difference between the pair of reception signals with a hysteresis, and uses a second potential as a reference for operation. The second circuit includes: a detection circuit that compares and outputs a detection result of whether or not the potential difference exceeds a predetermined range as a second signal; and a reset circuit that resets the operation of the detection circuit when the logic value of the second signal is maintained for a preset period.

Description

Technical Field

[0001] The invention relates to a signal transmission circuit and a power conversion device. Background Art

[0002] The signal transmission circuit disclosed in Patent Document 1 includes: a transformer including a first coil and a second coil; a first circuit connected to the first coil; and a second circuit connected to the second coil. A first signal is input to the first circuit, and a second signal is output from the second circuit.

[0003] The second circuit includes a detection circuit, two rectifier circuits, a control circuit, and two output resistors. The detection circuit detects voltage signals generated at both ends of the second coil, generates and outputs a second signal based on the voltage signals. The control circuit controls the control voltages given to the two rectifier circuits, and controls the bias voltages transmitted to the two rectifier circuits via the output resistors.

[0004] The power conversion device disclosed in Patent Document 1 has two signal transmission circuits, two switching elements, and two driving units. The second circuit of each signal transmission circuit is connected to the input terminal of each driving unit. The output terminal of each driving unit is connected to the input terminal of each switching element.

[0005] Patent Document 1: International Publication No. 2018 / 066165

[0006] The voltage across the second coil varies, for example, depending on the on / off operation of the switch element. Suppressing the variation in the voltage across the second coil contributes to suppressing malfunction of the detection circuit connected to the second coil and malfunction of the on / off operation of the switch element.

[0007] In order to suppress the change of the voltage at both ends of the second coil and even suppress the malfunction of the second circuit, the control voltage and bias voltage given to the two rectifier circuits are controlled. It is assumed that when the amount of change over time of the potential caused by the on-off of the switching element is significant, the on-off of the switching element cannot prevent the malfunction of the second circuit. From the perspective of the second signal reflecting the first signal in the signal transmission circuit and even suppressing the malfunction of the on-off of the switching element in the power conversion device, it is preferable to suppress the occurrence of this situation. Summary of the invention

[0008] The signal transmission circuit according to the present invention aims to appropriately transmit a signal. The power conversion device according to the present invention aims to suppress malfunction of the switching element.

[0009] The signal transmission circuit of the present invention comprises: a first circuit, which receives a first signal as input, generates a transmission signal corresponding to a change in a logic value of the first signal, and uses a first potential as a reference for operation; a transformer, which comprises a first coil and a second coil, wherein the first coil receives the transmission signal from the first circuit, and the second coil is inductively coupled with the first coil to output a pair of reception signals; and a second circuit, which receives the pair of reception signals from the second coil, compares the potential difference of the pair of reception signals with a hysteresis to generate a second signal, and uses the second potential as a reference for operation.

[0010] In the first mode of the signal transmission circuit, the second circuit comprises: a detection circuit, which performs the comparison and outputs the result of detecting whether the potential difference exceeds a predetermined range as the second signal; and a reset circuit, which resets the operation of the detection circuit when the logic value of the second signal is maintained for a predetermined period.

[0011] A second aspect of the signal transmission circuit according to the present invention is that, in the first aspect, the second circuit further comprises a compensation circuit, the compensation circuit generating a pair of third signals obtained by applying a DC voltage based on the second potential as a compensation voltage to the pair of received signals, and the detection circuit generates the second signal by performing the comparison on the potential difference between the pair of third signals generated by the compensation circuit.

[0012] The third mode of the signal transmission circuit involved in the present invention is that in the second mode, the compensation circuit has: a first input terminal, which is input with one of the pair of received signals; a second input terminal, which is input with the other of the pair of received signals; a first output terminal, which is input with one of the pair of third signals; a second output terminal, which is input with the other of the pair of third signals; a first resistor, which has one end connected to the first output terminal and the other end to which the DC voltage is applied; a second resistor, which has one end connected to the second output terminal and the other end to which the DC voltage is applied; a first capacitor, which is connected between the first input terminal and the first output terminal; and a second capacitor, which is connected between the second input terminal and the second output terminal.

[0013] The fourth aspect of the signal transmission circuit according to the present invention is that, in the third aspect, the second circuit further comprises a first clamp circuit and a second clamp circuit, the first clamp circuit and the second clamp circuit being connected in series between the first input terminal and the second input terminal. The first clamp circuit comprises: a first diode; a second diode connected in parallel with the first diode, the forward direction of the second diode being opposite to the forward direction of the first diode; and a first current limiting resistor connected in series with each of the first diode and the second diode. The second clamp circuit comprises: a third diode; a fourth diode connected in parallel with the third diode, the forward direction of the fourth diode being opposite to the forward direction of the third diode; and a second current limiting resistor connected in series with each of the third diode and the fourth diode.

[0014] A fifth aspect of the signal transmission circuit according to the present invention is that, in any of the first to fourth aspects, the first circuit includes: a pulse generating circuit that generates a fourth signal, the fourth signal generating a first pulse train having a plurality of pulses in a portion of a period in which the first signal takes a first logical value, and a second pulse train having a plurality of pulses following the first pulse train in the portion; and an output circuit that generates the transmission signal in accordance with a change in the logical value of the fourth signal. One cycle of the pulses in the second pulse train is longer than one cycle of the pulses in the first pulse train.

[0015] A sixth aspect of the signal transmission circuit according to the present invention is that, in the fifth aspect, the output circuit includes a transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode. The first circuit further includes a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied.

[0016] A seventh aspect of the signal transmission circuit according to the present invention is that, in the fifth aspect, the output circuit includes a first transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode. The first circuit further includes a second transistor in an on state, the second transistor having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied.

[0017] The first mode of the power conversion device according to the present invention comprises: an output line; a first switching element having one end to which a fixed potential is applied and the other end connected to the output line; a second switching element having one end connected to the output line and the other end to which a third potential is applied, the second switching element being exclusively connected to the first switching element; a first signal transmission circuit, which adopts any of the first to fifth modes of the signal transmission circuit according to the present invention; a second signal transmission circuit, which adopts any of the first to fifth modes of the signal transmission circuit according to the present invention; a first latch circuit, which outputs a signal for controlling whether the first switching element is allowed to be turned on, is set by the second signal output by the first signal transmission circuit, and is reset by the second signal output by the second signal transmission circuit. The second potential in the first signal transmission circuit and the second potential in the second signal transmission circuit are both the potential of the output line.

[0018] The second aspect of the power conversion device according to the present invention is that, in the first aspect, the device further comprises: a third signal transmission circuit, which adopts any of the first to fifth aspects of the signal transmission circuit according to the present invention; a fourth signal transmission circuit, which adopts any of the first to fifth aspects of the signal transmission circuit according to the present invention; and a second latch circuit, which outputs a signal for controlling whether the second switching element is allowed to be turned on, is set by the second signal output by the third signal transmission circuit, and is reset by the second signal output by the fourth signal transmission circuit. The second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are both the third potential.

[0019] Effects of the Invention

[0020] According to the first aspect of the signal transmission circuit according to the present invention, a signal is appropriately transmitted.

[0021] According to the second aspect of the signal transmission circuit according to the present invention, the influence of the variation of the second potential is reduced compared to the case where the comparison is performed based on a pair of reception signals.

[0022] According to the third aspect of the signal transmission circuit of the present invention, by setting the impedance of each of the first resistor, the second resistor, the first capacitor, and the second capacitor, the input impedance of the second circuit can be adjusted. By this adjustment, the potential difference between a pair of received signals is increased. By this adjustment, the variation of the DC voltage is suppressed.

[0023] According to the fourth aspect of the signal transmission circuit according to the present invention, the rise and fall of a pair of reception signals are restricted.

[0024] According to the fifth aspect of the signal transmission circuit of the present invention, the first pulse train causes the first signal to be appropriately reflected in the second signal, and the second pulse train reduces current consumption and improves reliability of signal transmission.

[0025] According to the sixth aspect of the signal transmission circuit according to the present invention, the difference between the displacement current flowing through one end of the first coil and the displacement current flowing through the other end of the first coil is reduced, thereby suppressing malfunction caused by the difference.

[0026] According to the seventh aspect of the signal transmission circuit of the present invention, the difference between the displacement current flowing through one end of the first coil and the displacement current flowing through the other end of the first coil is reduced, and malfunction caused by the difference is suppressed in a wide temperature range.

[0027] The advantages of the signal transmission circuit according to the present invention can be obtained by both the first aspect and the second aspect of the power conversion device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a circuit diagram illustrating the configuration of the signal transmission circuit 1000 according to the first embodiment.

[0029] Figure 2 This is a waveform diagram illustrating the temporal changes of each signal according to the first embodiment.

[0030] Figure 3 This is a waveform diagram for explaining the advantage of providing the self-reset circuit 241.

[0031] Figure 4 This is a circuit diagram illustrating the configuration of a power conversion device 2000 according to the second embodiment.

[0032] Figure 5 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 a .

[0033] Figure 6 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 b .

[0034] Figure 7 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 x.

[0035] Figure 8 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000y.

[0036] Fig. 9 1000a and 1000b are waveform diagrams illustrating changes in each signal in the signal transmission circuits 1000a and 1000b over time.

[0037] Fig.10 1000x and 1000y are waveform diagrams illustrating changes in each signal in the signal transmission circuits 1000x and 1000y over time.

[0038] Fig.11 This is a graph illustrating the rectification characteristics of a diode.

[0039] Fig.12 This is a waveform diagram illustrating each signal in the third embodiment.

[0040] Fig.13 This is a circuit diagram illustrating the configuration of a signal transmission circuit 1000 to which the first circuit 100 according to the fourth embodiment is applied.

[0041] Fig.14 : is a circuit diagram showing the path through which the displacement current Idev2 flows.

[0042] Fig.15 : is a circuit diagram showing the path through which the displacement current Idev1 flows.

[0043] Fig.16 This is a waveform diagram illustrating the temporal changes of various signals in the first circuit 100 according to the fourth embodiment.

[0044] Fig.17 This is a circuit diagram illustrating the configuration of a signal transmission circuit 1000 to which the first circuit 100 according to the fifth embodiment is applied. DETAILED DESCRIPTION

[0045] <1. Signal transmission circuit>

[0046] Embodiment 1 of the present invention relates to a signal transmission circuit. Figure 1 This is a circuit diagram illustrating the configuration of the signal transmission circuit 1000 according to the first embodiment.

[0047] The signal transmission circuit 1000 includes an input terminal 50, a first circuit 100, a transformer 10, a second circuit 200, and an output terminal 51. The input terminal 50 may be considered to be included in the first circuit 100. The output terminal 51 may be considered to be included in the second circuit 200.

[0048] <1-1. First Circuit 100>

[0049] The first circuit 100 includes a pulse generating circuit 101 and an output circuit 102. A first signal S1 is input to the first circuit 100 via an input terminal 50. The first signal S1 shows two logical values. The first signal S1 is ideally a rectangular wave, but may also be a waveform with a gentle curve to the extent that the pulse generating circuit 101 can distinguish two logical values.

[0050] <1-2. Pulse Generating Circuit 101>

[0051] The pulse generating circuit 101 outputs a signal J1 corresponding to the change in the value of the first signal S1. Specifically, the pulse generating circuit 101 distinguishes the value of the first signal S1 into two logical values, "H" and "L". The pulse generating circuit 101 outputs a train of multiple pulses (hereinafter, temporarily referred to as a "pulse train") or a single pulse in the signal J1 when the first signal S1 changes from "L" to "H". The following mainly describes the case where a pulse train is generated in the signal J1.

[0052] The pulse generating circuit 101 stops outputting the pulse train in the signal J1 when the first signal S1 changes from "H" to "L." The pulse generating circuit 101 is realized by, for example, a multivibrator.

[0053] The so-called pulse width of the pulse in the signal J1 has a predetermined value, and here, the length of the period during which the pulse takes "H" has a predetermined value. The predetermined value is shorter than the period assumed as the interval between the adjacent transitions of two logic values ​​of the first signal S1 in opposite directions. The pulse train is continued to be generated when the first signal S1 changes from "L" to "H", and the generation of the pulse train is stopped when the first signal S1 changes from "H" to "L".

[0054] <1-3. Output Circuit 102>

[0055] The output circuit 102 receives the signal J1 and outputs a transmission signal VT2 reflecting the signal J1. Since the output circuit 102 and the pulse generating circuit 101 are both components of the first circuit 100, it can be said that the transmission signal VT2 is generated by the first circuit 100 and is a signal corresponding to the waveform of the first signal S1 input to the first circuit 100, specifically, the change in its logic value.

[0056] For example, the output circuit 102 is realized by an inverter having field effect transistors (hereinafter also simply referred to as "transistors") 103 and 104. The transistor 103 is, for example, a P-channel transistor, and the transistor 104 is, for example, an N-channel transistor.

[0057] The transistor 103 has a gate, a source, and a drain. The source and the drain can be said to be a first electrode and a second electrode that are mutually conductive by a signal applied to the gate. The gate can be said to be a third electrode that controls the conduction between the first electrode and the second electrode. The transistor 104 also has a source as the first electrode, a drain as the second electrode, and a gate as the third electrode.

[0058] The signal J1 is applied to both the gate of the transistor 103 and the gate of the transistor 104. The drain of the transistor 103 and the drain of the transistor 104 are connected to each other, and the potentials of these drains are output from the output circuit 102 or the first circuit 100 as the transmission signal VT2. The potentials of these drains are based on the potential G1. Specifically, the potential G1 of the first circuit 100 is applied to the source of the transistor 104, and a fixed potential VCC higher than the potential G1 is applied to the source of the transistor 103. In this way, the operation of the first circuit 100 is based on the potential G1. The potential VT1 of the source of the transistor 103 is output from the output circuit 102 or the first circuit 100.

[0059] The transformer 10 has a first coil 11 and a second coil 12. The first coil 11 and the second coil 12 are inductively coupled. The transformer 10 has a first end P1, a second end P2, a third end P3, and a fourth end P4. One end of the first coil 11 is connected to the first end P1, and the other end is connected to the second end P2. One end of the second coil 12 is connected to the third end P3, and the other end is connected to the fourth end P4. A parasitic capacitance Cp exists between the first end P1 side of the first coil 11 and the third end P3 side of the second coil 12, and between the second end P2 side of the first coil 11 and the fourth end P4 side of the second coil 12.

[0060] The source of the transistor 103 is connected to the first terminal P1, and the potential VT1 is input from the first circuit 100. The drain of the transistor 103 and the drain of the transistor 104 are connected to the second terminal P2, and the transmission signal VT2 is input from the first circuit 100.

[0061] When the pulse in the signal J1 rises, the transistor 103 changes from the on state to the off state, and the transistor 104 changes from the off state to the on state. The potential VT1 is output from the first circuit 100, and the potential G1 is output as the transmission signal VT2. A current flows from the first terminal P1 to the second terminal P2 in the first coil 11. When the current starts to flow, the potential of the third terminal P3 increases and the potential of the fourth terminal P4 decreases in a manner that hinders the increase of the current.

[0062] When the pulse in the signal J1 falls, the transistor 103 changes from the off state to the on state, and the transistor 104 changes from the on state to the off state. The two ends of the first coil 11 are short-circuited via the transistor 103 in the first circuit 100, and the current flowing through the first coil 11 decreases. Due to this decrease, the potential of the third terminal P3 decreases and the potential of the fourth terminal P4 increases in a manner that hinders the decrease.

[0063] The potential of the third terminal P3 is input as a reception signal VR1 to the second circuit 200. The potential of the fourth terminal P4 is input as a reception signal VR2 to the second circuit 200. The second coil 12 outputs a pair of reception signals VR1 and VR2. The potential of the reception signals VR1 and VR2 is based on the potential G2 that serves as the operation reference of the second circuit 200. The potential difference between the potentials G1 and G2 may vary.

[0064] <1-4. Second Circuit 200>

[0065] The second circuit 200 includes a detection circuit 240, a compensation circuit 220, and clamp circuits 205 and 206. The potential serving as an operation reference of the second circuit 200 is the potential G2.

[0066] The compensation circuit 220 has input terminals P5 and P6 and output terminals P7 and P8. A reception signal VR1 is given to the input terminal P5, and a reception signal VR2 is given to the input terminal P6. A signal VRO1 is output from the output terminal P7, and a signal VRO2 is output from the output terminal P8. The compensation circuit 220 gives compensation voltages to the reception signals VR1 and VR2, and generates signals VRO1 and VRO2, respectively.

[0067] <1-5. Detection Circuit 240>

[0068] The detection circuit 240 has input terminals P9 and P10 and an output terminal P11. A signal VRO1 is given to the input terminal P9, and a signal VRO2 is given to the input terminal P10. A second signal S2 is output from the output terminal P11. The second signal S2 is output from the output terminal 51. The detection circuit 240 operates with the potential G2 as a reference.

[0069] The second signal S2 depends on the potential difference between the signals VRO1 and VRO2, specifically, on the value obtained by subtracting the potential of the signal VRO2 from the potential of the signal VRO1 (hereinafter referred to as "subtraction voltage value") ΔV, and takes potentials corresponding to two logical values ​​"H" and "L". Specifically, the detection circuit 240: (i) when the subtraction voltage value ΔV changes from a state less than the positive first threshold to a state greater than or equal to the first threshold, the logic value of the second signal S2 rises from "L" to "H"; (ii) when the subtraction voltage value ΔV changes from a state greater than the negative second threshold to a state less than or equal to the second threshold, the logic value of the second signal S2 drops from "H" to "L"; (iii) even if there is a change in the subtraction voltage value ΔV other than the above (i) and (ii), the state of the logic value of the second signal S2 is maintained; (iv) taking precedence over the above actions (i) to (iii), the logic value of the second signal S2 is set to "L" by resetting.

[0070] In view of this operation, the signals VRO1 and VRO2 can also be considered as a pair of detection signals. The detection circuit 240 compares the pair of reception signals VR1 and VR2 with hysteresis using the first threshold and the second threshold, detects whether the potential difference between the two exceeds a predetermined range, and generates the detection result as the second signal S2.

[0071] For example, the detection circuit 240 is implemented by a hysteresis comparator or a Schmitt trigger circuit. Potentials G2 and VCC are applied to the detection circuit 240, and the potential difference between the two is the operating voltage of the detection circuit 240. The potential VCC applied to the detection circuit 240 is higher than the potential G2. The potential VCC applied to the detection circuit 240 and the potential VCC applied to the output circuit 102 may also be different.

[0072] <1-6. Compensation Circuit 220>

[0073] The compensation circuit 220 includes voltage-dividing resistors 223 and 224, and capacitors 221 and 222. The voltage-dividing resistor 223 and the capacitor 221 implement an RC high-pass filter, which removes the noise and DC components of the low-frequency components of the received signal VR1. The voltage-dividing resistor 224 and the capacitor 222 implement an RC high-pass filter, which removes the noise and DC components of the low-frequency components of the received signal VR2.

[0074] Specifically, the capacitor 221 is connected between the input terminal P5 and the output terminal P7, and the capacitor 222 is connected between the input terminal P6 and the output terminal P8. One end of the voltage-dividing resistor 223 is connected to the output terminal P7. One end of the voltage-dividing resistor 224 is connected to the output terminal P8. The other end of the voltage-dividing resistor 223 is connected to the other end of the voltage-dividing resistor 224, for example, and a DC voltage D1 based on the potential G2 is applied to both of them as a compensation voltage (which can also be regarded as a bias voltage).

[0075] Since the DC voltage D1 is applied as a compensation voltage to both the reception signals VR1 and VR2 to generate the signals VRO1 and VRO2, the subtraction voltage value ΔV can also be considered to be the potential difference between the reception signals VR1 and VR2, specifically, the value obtained by subtracting the potential of the reception signal VR2 from the potential of the reception signal VR1. From this point of view, it can also be considered that the second circuit 200 compares the potential difference between the pair of reception signals VR1 and VR2 with hysteresis and generates the second signal S2 as a result of the comparison.

[0076] Compared with the case where the comparison is performed based on the pair of reception signals VR1 and VR2 , the detection circuit 240 performs the comparison based on the pair of signals VRO1 and VRO2 , which helps to reduce the influence of the variation of the potential G2 and even the influence of the voltage variation Vdif described later.

[0077] For example, the compensation circuit 220 has a DC compensation voltage circuit 225. The DC compensation voltage circuit 225 outputs a DC voltage D1 with the potential G2 as a reference. The DC compensation voltage circuit 225 is implemented by a known DC voltage source, for example. The DC compensation voltage circuit 225 can also be disposed outside the compensation circuit 220.

[0078] The DC voltage D1 is set to the center value of the voltage range of the input terminals P9 and P10 (hereinafter referred to as the "appropriate voltage range") in which the detection circuit 240 can properly perform the above-mentioned operation. The DC voltage D1 can also be set in accordance with the characteristics of the received signals VR1 and VR2 or the performance of the detection circuit 240.

[0079] For example, with the potential G2 as a reference, the appropriate voltage range is 0 to 5 V. When the maximum value of the received signal VR1 is 1 V and the minimum value of the received signal VR2 is -1 V, the DC voltage D1 is 2.5 V. With this adoption, the maximum value of the signal VRO1 is 3.5 V, and the upper limit of the appropriate voltage range has a margin of 1.5 (= 5-3.5) V. With this adoption, the minimum value of the signal VRO2 is 3.5 V, and the lower limit of the appropriate voltage range has a margin of 1.5 (= 1.5-0) V.

[0080] For example, with the potential G2 as the reference, the appropriate voltage range is 0 to 5 V. When the maximum value of the received signal VR1 is 1.2 V and the minimum value of the received signal VR2 is -0.8 V, the DC voltage D1 is 2.3 V. By adopting this, both the upper and lower limits of the appropriate voltage range have a margin of 1.5 V.

[0081] For example, with the potential G2 as the reference, the appropriate voltage range is 1 to 5 V. When the maximum value of the received signal VR1 is 1 V and the minimum value of the received signal VR2 is -1 V, the DC voltage D1 is 3 V. This allows a 1 V margin for both the upper and lower limits of the appropriate voltage range.

[0082] The voltage-dividing resistors 223 and 224 and the transformer 10, more specifically, the voltage-dividing resistors 223 and 224 and the second coil 12 are connected via capacitors 221 and 222. The existence of capacitors 221 and 222 makes it difficult for the received signals VR1 and VR2 to change even if the impedance of the voltage-dividing resistors 223 and 224 is small, and even if the impedance of the voltage-dividing resistors 223 and 224 is large, the change of the DC voltage D1 is suppressed. Therefore, there is a design advantage that the design of the voltage-dividing resistors 223 and 224 is easy.

[0083] The input impedance of the second circuit 200 can be adjusted by setting the compensation circuit 220, specifically, by setting the impedance of each of the voltage-dividing resistors 223 and 224 and the capacitors 221 and 222. This adjustment contributes to increasing the potential difference between the reception signals VR1 and VR2.

[0084] For example, the values ​​of capacitors 221 and 222 can be adjusted to obtain impedance matching between the second circuit 200 and the transformer 10, and the potential difference between the received signals VR1 and VR2 can be adjusted. Impedance matching helps to improve the SN ratio. In this case, the variation of the DC voltage D1 can also be suppressed, which can provide a design advantage.

[0085] Figure 2 It is a waveform diagram that illustrates the change of each signal over time. Figure 2 In FIG. 1 , the waveforms of the logic value of the first signal S1, the logic value of the signal J1, the received signals VR1 and VR2, the signals VRO1 and VRO2, and the logic value of the second signal S2 are illustrated. Figure 2 In FIG. 1 , the waveform of a voltage variation Vdif described later is also illustrated.

[0086] The logic value of the first signal S1 changes from "L" to "H" (rises) at time t_on. The logic value of the first signal S1 changes from "H" to "L" (falls) at time t_off.

[0087] The signal J1 outputs a pulse train during the period when the logic value of the first signal S1 is "H". Figure 2 In FIG. 1 , the case where the signal J1 outputs 4 pulses during the period when the logic value of the first signal S1 is "H" is illustrated. Through the function of the output circuit 102, the logic value of the transmission signal VT2 is opposite to the logic value of the signal J1, and the logic value of the signal J1 is the inverse value of the logic value of the transmission signal VT2. Figure 2 In FIG. 1 , the inversion of the logic value of the transmission signal VT2 is shown together with the signal J1 by adding an overline to the label "VT2".

[0088] The received signals VR1 and VR2 both change with the potential G2 as a reference. At the time point when the pulse in the signal J1 rises, the current from the first end P1 to the second end P2 starts to flow in the first coil 11, so at this time point, the received signal VR1 temporarily rises and the received signal VR2 temporarily drops, and each shows a decaying waveform afterwards. At this time, the current i flowing through the first coil 11 and the mutual inductance L between the first coil 11 and the second coil 12 are introduced, and the value of the received signal VR1 is represented by L·(di / dt), and the value of the received signal VR2 is represented by -L·(di / dt).

[0089] At the time point when the pulse in signal J1 falls, reception signal VR1 temporarily falls and reception signal VR2 temporarily rises, and each shows a decaying waveform thereafter. The value of reception signal VR1 at this time is represented by -L·(di / dt), and the value of reception signal VR2 is represented by L·(di / dt).

[0090] Thus, as for the current i, since the value of its time differential (di / dt) determines the reception signals VR1 and VR2, it functions in the same manner as the transmission signal VT2 in that it corresponds to the change in the logic value of the first signal S1. The first circuit 100 can generate the current i corresponding to the change in the logic value of the first signal S1, and the current i is input from the first circuit 100 to the first coil 11. For example, the transmission signal VT2 may be output from the drain of the transistor 104 as the drain potential of the transistor 104, and the current i may be a transmission signal output from the drain as a current flowing through the drain of the transistor 104.

[0091] The waveform of the received signal VR2 rising and then attenuating at the time point of the pulse rising in the signal J1 during the period when the voltage variation Vdif rises (hereinafter referred to as the "rising period") is shown as an example. The voltage variation Vdif represents the voltage of the potential G1 with respect to the potential G2. Specifically, if the voltage variation per unit time (hereinafter also referred to as "time differential") dv / dt is generated with respect to the potential G1 as the reference in the potential G2, then the voltage determined by the product of a certain time constant and the time differential dv / dt is equivalent to the voltage variation Vdif. The time constant is the product of the electrostatic capacitance value of the parasitic capacitance Cp and the resistance value of the equivalent resistance R ^ of the second circuit 200. The equivalent resistance R ^ includes the resistance components of the clamping circuits 205 and 206 and the wiring resistance of the second circuit 200.

[0092] The voltage variation Vdif is based on the potential G2 and is in the relationship of Vdif=-(dv / dt)·Cp·R^ during the rising period (the symbol Cp represents the electrostatic capacitance value of the parasitic capacitor Cp, and the symbol R^ represents the resistance value of the equivalent resistor R^).

[0093] If the speed at which the potential G2 decreases from the potential G1 increases, the voltage variation Vdif increases. At this time, the parasitic capacitance Cp is charged by the displacement current caused by the voltage variation Vdif. Figure 2, the voltage variation Vdif starts to rise at time t_dvdt, and the state in which the fourth pulse of the signal J1 rises during the rising period is shown. If the signal J1 pulse rises during the rising period, the decrease in the potential G2 is reflected, and the amount by which the received signal VR1 rises from the potential G2 becomes larger. The received signal VR2 does not fall from the potential G2, and the received signal VR1 rises from the potential G2 by an amount smaller than the amount by which it rises. Alternatively, the received signal VR2 falls from the potential G2 by an amount smaller than the state in which the voltage variation Vdif does not rise. After the pulse rise in the signal J1, the current from the first terminal P1 to the second terminal P2 decreases, and the received signals VR1 and VR2 attenuate and return to the potential G2.

[0094] If the voltage time differential dv / dt does not occur in the potential G2, the voltage variation Vdif is in a steady state. Therefore, at the fall of the fourth pulse in the signal J1 after the voltage variation Vdif becomes steady, the reception signals VR1 and VR2 operate in the same manner as at the fall of other pulses.

[0095] exist Figure 2 The example in FIG. 1 illustrates a case where the subtraction voltage value ΔV changes from a state where it is less than the first threshold value to a state where it is greater than or equal to the first threshold value even during the rising period. According to the above action (i), the example illustrates a case where the logic value of the second signal S2 rises from "L" to "H".

[0096] The case where the pulse of the signal J1 falls during the rising period will be described later in “<1-7. Self-reset circuit 241>”.

[0097] The waveforms of signals VRO1 and VRO2 are similar to those of received signals VR1 and VR2, respectively. Signal VRO1 is based on DC voltage D1 and shows the same rise and subsequent attenuation, and fall and subsequent attenuation as received signal VR1, through a high-pass filter and DC compensation voltage circuit 225 obtained by capacitor 221 and voltage-dividing resistor 223. Signal VRO2 is based on DC voltage D1 and shows the same rise and attenuation as received signal VR2, through a high-pass filter and DC compensation voltage circuit 225 obtained by capacitor 222 and voltage-dividing resistor 224.

[0098] Since the detection circuit 240 operates as described above, a pulse train appears in the second signal S2 corresponding to the pulse train generated in the signal J1 based on the first signal S1. The interval between adjacent transitions of the pulse train appearing in the signal J1 is equal to the interval between adjacent transitions of the pulse train appearing in the second signal S2 corresponding to the pulse train.

[0099] <1-7. Self-reset circuit 241>

[0100] The second circuit 200 includes a self-reset circuit 241. The second signal S2 is input to the self-reset circuit 241, and the self-reset circuit 241 outputs a reset signal R1. The reset signal R1 is input to the detection circuit 240, and resets the operation of the detection circuit 240.

[0101] The self-reset circuit 241 suppresses the second signal S2 from being "H" for more than a preset period (hereinafter also temporarily referred to as the "allowed period"). Specifically, the self-reset circuit 241 validates the reset signal R1 after the logic value of the second signal S2 rises and the allowed period has passed. The detection circuit 240 is reset by the validation of the reset signal R1. Through this reset, the logic value of the second signal S2 becomes "L" (refer to (iv) above). The self-reset circuit 241 functions as a reset circuit, which resets the operation of the detection circuit 240 in the signal transmission circuit 1000 itself when the logic value of the second signal S2 is maintained, here "H", for the allowed period.

[0102] The self-reset circuit 241 is implemented by, for example, a timer that is started when the logic value of the second signal S2 rises, and outputs a single-pulse reset signal R1 when the enable period elapses.

[0103] For example, the self-reset circuit 241 is configured to include a capacitor charged with a constant current during a period in which the logic value of the second signal S2 is "H", and outputs a single-pulse reset signal R1 when a voltage charged by the capacitor exceeds a threshold.

[0104] Figure 3 This is a waveform diagram for explaining the advantages of providing the self-reset circuit 241. Figure 3 , the waveforms of the logic value of the first signal S1, the logic value of the signal J1, the received signals VR1, VR2, and the logic value of the second signal S2 are shown. Figure 3 In FIG. 1 , the inversion of the logic value of the transmission signal VT2 is also shown together with the signal J1 by adding an overline to the label "VT2". Figure 3 , the logic value of the first signal S1 rises at time t_on and falls at time t_off.

[0105] The pulse at the end of the pulse train appearing in the signal J1 rises at the instant t_s. Figure 3 2 shows an example in which the falling edge of the last pulse of the pulse train appearing in the signal J1 also falls at the time t_off. However, the falling edge of the last pulse may occur before the time t_off.

[0106] The case where the voltage variation Vdif is 0 V (that is, the potential G1 and the potential G2 are equal) from the time t_on to the time t_dvdt and starts to increase from the time t_dvdt is illustrated.

[0107] exist Figure 3 The reference numerals “…” in the logic value of the intermediate signal J1, the received signals VR1, VR2, and the logic value of the second signal S2 are abbreviations for repeatedly arranging the same waveforms in each of them.

[0108] and Figure 2 On the other hand, before the pulse at the end of the pulse train of the signal J1 falls, the voltage variation Vdif rises from the time t_dvdt. As described above, during the rising period, the potential of the potential G2 is lower than the potential G1. Therefore, corresponding to this fall, the received signal VR1 does not fall but rises. As a result, the potential difference between the received signals VR1 and VR2 is smaller than the potential difference when the pulse in the signal J1 falls when the voltage variation Vdif is stable. As a result, the potential difference between the signals VRO1 and VRO2 is sometimes small (at Figure 3 (not shown in the figure), the above-mentioned action "(ii) taking the change of the subtraction voltage value ΔV from a state greater than the negative second threshold value to a state less than or equal to the second threshold value as an opportunity, causing the logic value of the second signal S2 to drop from "H" to "L"" in the detection circuit 240 is not performed. Due to this malfunction, the logic value of the second signal S2 rises to "H" at time t_s and remains "H" even after time t_off (refer to the dot-dashed line). For convenience, the phenomenon in which the logic value of the second signal S2 is maintained at "H" longer than the "H" of the signal J1 due to such a malfunction is referred to as "high latch".

[0109] The self-reset circuit 241 implements the above-mentioned "(iv) takes precedence over the above-mentioned actions (i) to (iii) of the detection circuit 240, and resets the logic value of the second signal S2 to "L". This action helps to reduce high latching. Figure 3 , the logic value of the second signal S2 changes to "L" at time t_d by resetting. In this case, the time from time t_s to time t_d is equivalent to the allowed period. The reduction of the high latch helps the second signal S2 to properly reflect the signal J1, and even to properly transmit the first signal S1 to the second signal S2.

[0110] It is preferable that the allowed period is longer than the pulse width used by the pulse generated by the signal J1. The reason is that even if there is no action defect, a pulse reflecting the pulse will be generated in the second signal S2. If the allowed period is less than or equal to the pulse width, normal action will not be performed. For example, the allowed period is less than or equal to one cycle of the pulse in the pulse train generated by the signal J1.

[0111] <1-8. Clamp Circuits 205 and 206>

[0112] The clamp circuits 205 and 206 are connected in series between the input terminals P5 and P6. A potential G2 is applied to a connection point between the clamp circuits 205 and 206. The clamp circuit 205 is arranged on the input terminal P5 side relative to the clamp circuit 206.

[0113] Specifically, the clamp circuit 205 includes, for example, diodes 201 and 202 and a resistor 207. In the clamp circuit 205, the diode 201 and the resistor 207 are connected in series. In the clamp circuit 205, the diode 202 and the resistor 207 are connected in series. The diodes 201 and 202 are connected in parallel so that their forward directions are opposite to each other. The diode 202 is connected in parallel with the diode 201, and its forward direction is opposite to that of the diode 201.

[0114] exist Figure 1 2 shows an example in which the forward direction of the diode 201 is from the clamp circuit 206 to the input terminal P5, and the forward direction of the diode 202 is from the input terminal P5 to the clamp circuit 206. For example, the cathode of the diode 201 and the anode of the diode 202 are both connected to the input terminal P5 via the resistor 207, and the potential G2 is applied to the anode of the diode 201 and the cathode of the diode 202.

[0115] The current flowing through the parasitic capacitance Cp between the first end P1 side of the first coil 11 and the third end P3 side of the second coil 12 passes through the clamp circuit 205. The clamp circuit 205 helps to suppress the charging and discharging of the parasitic capacitance Cp. Through this suppression, the rise and fall of the potential of the third end P3 (here, it can also be said that the potential of the received signal VR1) are limited.

[0116] Specifically, the clamp circuit 206 includes, for example, diodes 203 and 204 and a resistor 208. The diode 203 and the resistor 208 are connected in series in the clamp circuit 206. The diode 204 and the resistor 208 are connected in series in the clamp circuit 206. The diodes 203 and 204 are connected in parallel so that their forward directions are opposite to each other. The diode 204 is connected in parallel with the diode 203, and its forward direction is opposite to that of the diode 203.

[0117] exist Figure 1 2 shows a case where the forward direction of the diode 203 is from the clamp circuit 205 to the input terminal P6, and the forward direction of the diode 204 is from the input terminal P6 to the clamp circuit 205. For example, the cathode of the diode 203 and the anode of the diode 204 are both connected to the input terminal P6 via the resistor 208, and the potential G2 is applied to the anode of the diode 203 and the cathode of the diode 204.

[0118] The current flowing through the parasitic capacitance Cp between the second end P2 side of the first coil 11 and the fourth end P4 side of the second coil 12 passes through the clamp circuit 206. The clamp circuit 206 helps to suppress the charging and discharging of the parasitic capacitance Cp. Through this suppression, the rise and fall of the potential of the fourth end P4 (here, it can also be said that the potential of the received signal VR2) are limited.

[0119] Both the clamp circuits 205 and 206 contribute to reducing malfunctions of the detection circuit 240 caused by variations in the potential difference between the potentials G1 and G2 (which can be represented by the above-mentioned time differential dv / dt, for example).

[0120] The setting of the resistors 207 and 208 will be described in <2-6. Setting of Current Limiting Resistor> described later.

[0121] <2. Power conversion device>

[0122] Embodiment 2 of the present invention relates to a power conversion device. Figure 4 This is a circuit diagram illustrating the configuration of a power conversion device 2000 according to the second embodiment.

[0123] The first signal S1a, S1b, S1x, S1y having two logical values ​​is input to the power conversion device 2000. The power conversion device 2000 outputs an output potential OUT to the external load 1 via the output line 7. The output potential OUT is the potential of the output line 7. The external load 1 is driven by the output potential OUT. The external load 1 is, for example, a motor.

[0124] The control circuit 4 receives an input signal IN at its input terminal 8, outputs a first signal S1a at its output terminal 8a, and outputs a first signal S1x at its output terminal 8b. For example, the first signal S1b is obtained by inverting the logic value of the first signal S1a through an inverter. For example, the first signal S1y is obtained by inverting the logic value of the first signal S1x through an inverter.

[0125] The power conversion device 2000 includes an upper arm circuit 2000a and a lower arm circuit 2000b. The upper arm circuit 2000a and the lower arm circuit 2000b are connected via an output line 7. The power conversion device 2000 can also be regarded as including the output line 7.

[0126] <2-1. Upper bridge arm circuit 2000a>

[0127] The upper arm circuit 2000a includes signal transmission circuits 1000a and 1000b, a latch circuit 6a, a logic circuit 5a, a driver 3a, and a switch element 2a. The switch element 2a is, for example, a power semiconductor switch element. The switch element 2a is, for example, a reverse conducting IGBT (IGBT refers to an insulated gate bipolar transistor, the same below) 130.

[0128] The signal transmission circuit 1000a includes an input terminal 50a, a first circuit 100a, a transformer 10a, a second circuit 200a, and an output terminal 51a. The input terminal 50a may be considered to be included in the first circuit 100a. The output terminal 51a may be considered to be included in the second circuit 200a.

[0129] The signal transmission circuit 1000b includes an input terminal 50b, a first circuit 100b, a transformer 10b, a second circuit 200b, and an output terminal 51b. The input terminal 50b may be considered to be included in the first circuit 100b. The output terminal 51b may be considered to be included in the second circuit 200b.

[0130] The first signal S1a is input to the input terminal 50a. The first signal S1b is input to the input terminal 50b. The second signal S2a is output from the output terminal 51a. The second signal S2b is output from the output terminal 51b.

[0131] The latch circuit 6a has a set terminal P100a, a reset terminal P101a, and an output terminal P102a. The latch circuit 6a is set by making the logic value of the signal input to the set terminal P100a take "H", and the signal Qa output from the output terminal P102a takes the logic value "H". The latch circuit 6a is reset by making the logic value of the signal input to the reset terminal P101a take "H", and the signal Qa takes the logic value "L".

[0132] The set end P100a is connected to the output terminal 51a and the second signal S2a is inputted thereto. The reset end P101a is connected to the output terminal 51b and the second signal S2b is inputted thereto.

[0133] The logic circuit 5a has an input terminal P110a and an output terminal P111a. The input terminal P110a is connected to the output terminal P102a.

[0134] The driver 3a has an input terminal P120 and an output terminal P121. The input terminal P120 is connected to the output terminal P111a.

[0135] The gate of the reverse conducting IGBT 130 is connected to the output terminal P121. A fixed potential HV is applied to the collector of the reverse conducting IGBT 130, which is one end of the switching element 2a. The emitter of the reverse conducting IGBT 130, which is the other end of the switching element 2a, is connected to the output line 7. The gate of the reverse conducting IGBT 130 functions as an input terminal for driving the switching element 2a. The potential HV is based on the potential G3. The potential G3 is, for example, a ground potential.

[0136] <2-2. Lower bridge arm circuit 2000b>

[0137] The lower arm circuit 2000b includes signal transmission circuits 1000x and 1000y, a latch circuit 6b, a logic circuit 5b, a driver 3b, and a switch element 2b. The switch element 2b is, for example, a power semiconductor switch element. The switch element 2b is, for example, a reverse conducting IGBT 131. One or both of the switch elements 2a and 2b may be field effect transistors.

[0138] The signal transmission circuit 1000x includes an input terminal 50x, a first circuit 100x, a transformer 10x, a second circuit 200x, and an output terminal 51x. The input terminal 50x can be considered to be included in the first circuit 100x. The output terminal 51x can be considered to be included in the second circuit 200x.

[0139] The signal transmission circuit 1000y includes an input terminal 50y, a first circuit 100y, a transformer 10y, a second circuit 200y, and an output terminal 51y. The input terminal 50y can be considered to be included in the first circuit 100y. The output terminal 51y can be considered to be included in the second circuit 200y.

[0140] The first signal S1x is input to the input terminal 50x. The first signal S1y is input to the input terminal 50y. The second signal S2x is output from the output terminal 51x. The second signal S2y is output from the output terminal 51y.

[0141] The latch circuit 6b has a set terminal P100b, a reset terminal P101b, and an output terminal P102b. The latch circuit 6b is set by making the logic value of the signal input to the set terminal P100b take "H", and the signal Qb output from the output terminal P102b takes the logic value "H". The latch circuit 6b is reset by making the logic value of the signal input to the reset terminal P101b take "H", and the signal Qb takes the logic value "L".

[0142] The set terminal P100b is connected to the output terminal 51x and the second signal S2x is inputted thereto. The reset terminal P101b is connected to the output terminal 51y and the second signal S2y is inputted thereto.

[0143] The logic circuit 5b has an input terminal P110b and an output terminal P111b. The input terminal P110b is connected to the output terminal P102b.

[0144] The driver 3b has an input terminal P123 and an output terminal P124. The input terminal P123 is connected to the output terminal P111b.

[0145] The gate of the reverse conducting IGBT 131 is connected to the output terminal P124. The collector of the reverse conducting IGBT 131, which is one end of the switching element 2b, is connected to the output line 7. The potential G3 is applied to the emitter of the reverse conducting IGBT 131, which is the other end of the switching element 2b. The gate of the reverse conducting IGBT 131 functions as an input terminal for driving the switching element 2b.

[0146] <2-3. Signal Transmission Circuits 1000a, 1000b, 1000x, 1000y>

[0147] The signal transmission circuits 1000a, 1000b, 1000x, and 1000y in the second embodiment each adopt the structure of the signal transmission circuit 1000 in the first embodiment, for example. The power conversion device 2000 in the second embodiment obtains the advantages of the signal transmission circuit 1000.

[0148] Figure 5 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 a . Figure 6 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 b . Figure 7 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000 x. Figure 8 2 is a circuit diagram illustrating the structure of the signal transmission circuit 1000y.

[0149] The structure of the signal transmission circuit 1000a (see Figure 5 ) is similar to the signal transmission circuit 1000 described in Embodiment 1 (see Figure 1Specifically, the first circuit 100, the pulse generating circuit 101, the output circuit 102, the transistors 103 and 104, the transformer 10, the first coil 11, the second coil 12, the input terminal 50, the output terminal 51, the second circuit 200, the diodes 201, 202, 203, 204, the clamping circuits 205 and 206, the resistors 207 and 208, the compensation circuit 220, the capacitors 221 and 222, the voltage dividing resistors 223 and 224, the DC compensation voltage circuit 225, and the detection circuit 240 described in the first embodiment are replaced with the first circuit 100. , self-reset circuit 241, first terminal P1, second terminal P2, third terminal P3, fourth terminal P4, input terminals P5, P6, output terminals P7, P8, input terminals P9, P10, output terminal P11, parasitic capacitance Cp, first signal S1, second signal S2, signal J1, VRO1, VRO2, potential VT1, transmission signal VT2, reception signals VR1, VR2, DC voltage D1, reset signal R1, subtraction voltage value ΔV are respectively renamed as first circuit 100a, pulse generating circuit 101a, output circuit 102 a, transistors 103a, 104a, transformer 10a, first coil 11a, second coil 12a, input terminal 50a, output terminal 51a, second circuit 200a, diodes 201a, 202a, 203a, 204a, clamp circuits 205a, 206a, resistors 207a, 208a, compensation circuit 220a, capacitors 221a, 222a, voltage-dividing resistors 223a, 224a, DC compensation voltage circuit 225a, detection circuit 240a, self-reset circuit 241a, first terminal P1a , the second terminal P2a, the third terminal P3a, the fourth terminal P4a, the input terminals P5a, P6a, the output terminals P7a, P8a, the input terminals P9a, P10a, the output terminal P11a, the parasitic capacitance Cpa, the first signal S1a, the second signal S2a, the signal J1a, VRO1a, VRO2a, the potential VT1a, the transmission signal VT2a, the reception signals VR1a, VR2a, the DC voltage D1a, the reset signal R1a, and the subtraction voltage value ΔVa, the structure and operation of the signal transmission circuit 1000a are described.

[0150] However, in the structure of the signal transmission circuit 1000a, the anodes of the diodes 201a and 203a and the cathodes of the diodes 202a and 204a are connected to the output line 7 and are given the output potential OUT. The DC compensation voltage circuit 225a outputs a DC voltage D1a based on the output potential OUT. The operating voltage of the detection circuit 240a is the potential difference between the potential VCC and the output potential OUT. The output potential OUT is equivalent to the potential G2 mentioned in the first embodiment.

[0151] The structure of the signal transmission circuit 1000b (see Figure 6) and the structure of the signal transmission circuit 1000a (refer to Figure 5 Specifically, the first circuit 100a, the pulse generating circuit 101a, the output circuit 102a, the transistors 103a and 104a, the transformer 10a, the first coil 11a, the second coil 12a, the input terminal 50a, the output terminal 51a, the second circuit 200a, the diodes 201a, 202a, 203a and 204a, the clamping circuit 205a and 206a, the resistors 207a and 208a, the compensation circuit 220a, the capacitors 221a and 222a, the voltage dividing resistors 223a and 224a, and the DC compensation voltage The circuit 225a, the detection circuit 240a, the self-reset circuit 241a, the first terminal P1a, the second terminal P2a, the third terminal P3a, the fourth terminal P4a, the input terminals P5a, P6a, the output terminals P7a, P8a, the input terminals P9a, P10a, the output terminal P11a, the parasitic capacitance Cpa, the first signal S1a, the second signal S2a, the signal J1a, VRO1a, VRO2a, the potential VT1a, the transmission signal VT2a, the reception signal VR1a, VR2a, the DC voltage D1a, the reset signal R1a, and the subtraction voltage value ΔVa are each renamed First circuit 100b, pulse generating circuit 101b, output circuit 102b, transistors 103b and 104b, transformer 10b, first coil 11b, second coil 12b, input terminal 50b, output terminal 51b, second circuit 200b, diodes 201b, 202b, 203b and 204b, clamping circuits 205b and 206b, resistors 207b and 208b, compensation circuit 220b, capacitors 221b and 222b, voltage dividing resistors 223b and 224b, DC compensation voltage circuit 225b, detection circuit 240b, self-replication circuit 241b, The structure and operation of the signal transmission circuit 1000b are described, including the bit circuit 241b, the first end P1b, the second end P2b, the third end P3b, the fourth end P4b, the input terminals P5b, P6b, the output terminals P7b, P8b, the input ends P9b, P10b, the output end P11b, the parasitic capacitance Cpb, the first signal S1b, the second signal S2b, the signal J1b, VRO1b, VRO2b, the potential VT1b, the transmission signal VT2b, the reception signals VR1b, VR2b, the DC voltage D1b, the reset signal R1b, and the subtraction voltage value ΔVb.

[0152] The structure of the signal transmission circuit 1000x (see Figure 7 ) is similar to the signal transmission circuit 1000 described in Embodiment 1 (see Figure 1Specifically, the first circuit 100, the pulse generating circuit 101, the output circuit 102, the transistors 103 and 104, the transformer 10, the first coil 11, the second coil 12, the input terminal 50, the output terminal 51, the second circuit 200, the diodes 201, 202, 203, 204, the clamping circuits 205 and 206, the resistors 207 and 208, the compensation circuit 220, the capacitors 221 and 222, the voltage dividing resistors 223 and 224, the DC compensation voltage circuit 225, the detection circuit 240, the self- The reset circuit 241, the first terminal P1, the second terminal P2, the third terminal P3, the fourth terminal P4, the input terminals P5 and P6, the output terminals P7 and P8, the input terminals P9 and P10, the output terminal P11, the parasitic capacitance Cp, the first signal S1, the second signal S2, the signal J1, VRO1 and VRO2, the potential VT1, the transmission signal VT2, the reception signals VR1 and VR2, the DC voltage D1, the reset signal R1, the subtraction voltage value ΔV, and the potential G2 are respectively renamed as the first circuit 100x, the pulse generating circuit 101x, and the output circuit 10 2x, transistors 103x, 104x, transformer 10x, first coil 11x, second coil 12x, input terminal 50x, output terminal 51x, second circuit 200x, diodes 201x, 202x, 203x, 204x, clamp circuit 205x, 206x, resistors 207x, 208x, compensation circuit 220x, capacitors 221x, 222x, voltage-dividing resistors 223x, 224x, DC compensation voltage circuit 225x, detection circuit 240x, self-reset circuit 241x, first terminal P1x, The second end P2x, the third end P3x, the fourth end P4x, the input terminals P5x, P6x, the output terminals P7x, P8x, the input ends P9x, P10x, the output end P11x, the parasitic capacitance Cpx, the first signal S1x, the second signal S2x, the signal J1x, VRO1x, VRO2x, the potential VT1x, the transmission signal VT2x, the reception signal VR1x, VR2x, the DC voltage D1x, the reset signal R1x, the subtraction voltage value ΔVx, and the potential G3, the structure and operation of the signal transmission circuit 1000x are explained.

[0153] The structure of the signal transmission circuit 1000y (see Figure 8 ) and the structure of the signal transmission circuit 1000x (refer to Figure 7Specifically, the first circuit 100x, the pulse generating circuit 101x, the output circuit 102x, the transistors 103x and 104x, the transformer 10x, the first coil 11x, the second coil 12x, the input terminal 50x, the output terminal 51x, the second circuit 200x, the diodes 201x, 202x, 203x and 204x, the clamping circuit 205x and 206x, the resistors 207x and 208x, the compensation circuit 220x, the capacitors 221x and 222x, the voltage dividing resistors 223x and 224x, the DC compensation voltage The circuit 225x, the detection circuit 240x, the self-reset circuit 241x, the first terminal P1x, the second terminal P2x, the third terminal P3x, the fourth terminal P4x, the input terminals P5x, P6x, the output terminals P7x, P8x, the input terminals P9x, P10x, the output terminal P11x, the parasitic capacitance Cpx, the first signal S1x, the second signal S2x, the signal J1x, VRO1x, VRO2x, the potential VT1x, the transmission signal VT2x, the reception signal VR1x, VR2x, the DC voltage D1x, the reset signal R1x, and the subtraction voltage value ΔVx are each renamed First circuit 100y, pulse generating circuit 101y, output circuit 102y, transistors 103y and 104y, transformer 10y, first coil 11y, second coil 12y, input terminal 50y, output terminal 51y, second circuit 200y, diodes 201y, 202y, 203y and 204y, clamping circuits 205y and 206y, resistors 207y and 208y, compensation circuit 220y, capacitors 221y and 222y, voltage dividing resistors 223y and 224y, DC compensation voltage circuit 225y, detection circuit 240y, self-replication circuit 241y, The structure and operation of the signal transmission circuit 1000y are described, including the bit circuit 241y, the first end P1y, the second end P2y, the third end P3y, the fourth end P4y, the input terminals P5y and P6y, the output terminals P7y and P8y, the input ends P9y and P10y, the output end P11y, the parasitic capacitance Cpy, the first signal S1y, the second signal S2y, the signal J1y, VRO1y, VRO2y, the potential VT1y, the transmission signal VT2y, the reception signals VR1y and VR2y, the DC voltage D1y, the reset signal R1y, and the subtraction voltage value ΔVy.

[0154] The signal transmission circuits 1000a, 1000b, 1000x, and 1000y in Embodiment 2 all operate in the same manner as the signal transmission circuit 1000 in Embodiment 1. However, the potential G2 in the signal transmission circuit 1000 corresponds to the output potential OUT in the signal transmission circuits 1000a and 1000b, and the potential G2 in the signal transmission circuit 1000 corresponds to the potential G3 in the signal transmission circuits 1000x and 1000y.

[0155] When the signal transmission circuit 1000a adopts the signal transmission circuit 1000, the potential G2 is the output potential OUT. When the signal transmission circuit 1000b adopts the signal transmission circuit 1000, the potential G2 is the output potential OUT. When the signal transmission circuit 1000x adopts the signal transmission circuit 1000, the potential G2 is the potential G3. When the signal transmission circuit 1000y adopts the signal transmission circuit 1000, the potential G2 is the potential G3.

[0156] For example, the input signal IN has information for driving the external load 1. The control circuit 4 generates the first signals S1a and S1x based on the input signal IN. For example, the first signals S1a and S1x exclusively take the logical value "H" and are validated. The logical values ​​of the first signals S1b and S1y are respectively in an opposite relationship to the logical values ​​of the first signals S1b and S1x. The following example shows a case where the potential corresponding to the logical value "H" is higher than the potential corresponding to the logical value "L".

[0157] The signal transmission circuit 1000a performs signal transmission via the transformer 10a and outputs the second signal S2a. The signal transmission circuit 1000b performs signal transmission via the transformer 10b and outputs the second signal S2b. The signal transmission circuit 1000x performs signal transmission via the transformer 10x and outputs the second signal S2x. The signal transmission circuit 1000y performs signal transmission via the transformer 10y and outputs the second signal S2y.

[0158] The second signal S2a is input to the set terminal P100a. When the second signal S2a takes the logic value "H", the signal Qa output from the output terminal P102a takes the logic value "H". The second signal S2b is input to the reset terminal P101a. When the second signal S2b takes the logic value "H", the signal Qa takes the logic value "L".

[0159] As described above, the relationship between the signal J1 and the second signal S2 is the same as that described in the first embodiment (see Figure 2 ), the waveform of the logic value of the second signal S2a shows a pulse train that reflects the pulse train of the logic value of the signal J1a. Therefore, the waveform of the logic value of the second signal S2a is not limited to the waveform that reflects the logic value of the first signal S1a. However, through the function of the latch circuit 6a, after the second signal S2a temporarily takes the logic value "H", until the second signal S2b takes the logic value "H", the signal Qa continues to take the logic value "H". Similarly, after the second signal S2b temporarily takes the logic value "H", until the second signal S2a takes the logic value "H", the signal Qa continues to take the logic value "L". Since the logic value of the second signal S2b is in an opposite relationship to the logic value of the second signal S2a, the signal Qa takes a logic value that reflects the logic value of the first signal S1a.

[0160] The signal Qa functions as a drive-on signal for allowing the switch element 2a to be turned on, similarly to the first signal S1a. Similarly, the signal Qa functions as a drive-off signal for prohibiting the switch element 2a from being turned on, similarly to the first signal S1b. The signal Qa controls whether the switch element 2a is allowed to be turned on.

[0161] The second signal S2x is input to the set terminal P100b. When the second signal S2x takes the logic value "H", the signal Qb output from the output terminal P102b takes the logic value "H". The second signal S2y is input to the reset terminal P101b. When the second signal S2y takes the logic value "H", the signal Qb takes the logic value "L".

[0162] By the function of the latch circuit 6b, the signal Qb takes a logic value reflecting the logic value of the first signal S1x. The signal Qb functions as a drive-on signal that allows the switch element 2b to be turned on, similarly to the first signal S1x. Similarly, the signal Qb functions as a drive-off signal that prohibits the switch element 2b from being turned off, similarly to the first signal S1y. The signal Qb controls whether the switch element 2b is allowed to be turned on.

[0163] Signal Qa is input to input terminal P110a. Logic circuit 5a generates signal Ka based on signal Qa and outputs signal Ka from output terminal P111a. Signal Qb is input to input terminal P110b. Logic circuit 5b generates signal Kb based on signal Qb and outputs signal Kb from output terminal P111b. Signal Kb is given to input terminal P123. Signal Ka is given to input terminal P120.

[0164] The driver 3a amplifies the signal Ka with a predetermined gain to drive the switching element 2a. The driver 3b amplifies the signal Kb with a predetermined gain to drive the switching element 2b.

[0165] The signal Qa functions as both a driving on signal and a driving off signal for the switch element 2a. The logic circuit 5a generates a signal Ka by, for example, modulating the signal Qa when the signal Qa takes a logical value "H". Similarly, the logic circuit 5b generates a signal Kb by, for example, modulating the signal Qb when the signal Qb takes a logical value "H". The signal Ka is intermittently effective when the signal Qa takes a logical value "H", and is not effective when the signal Qa takes a logical value "L". The signal Kb is intermittently effective when the signal Qb takes a logical value "H", and is not effective when the signal Qb takes a logical value "L".

[0166] Since the logic values ​​of the first signals S1a and S1x are exclusively "H", and the logic values ​​of the signals Qa and Qb are also exclusively "H", the signals Ka and Kb generated as described above will not turn on the switch elements 2a and 2b at the same time when the second signals S2a, S2b, S2x, and S2y are normally obtained. The switch elements 2a and 2b are turned on exclusively, but are not limited to being turned on complementarily.

[0167] If the on-resistance of the switch element 2a is ignored, the output potential OUT rises toward the potential HV by turning on the switch element 2a when the switch element 2b is off. If the on-resistance of the switch element 2b is ignored, the output potential OUT falls toward the potential G3 by turning on the switch element 2b when the switch element 2a is off.

[0168] The second circuit 200a of the signal transmission circuit 1000a, the second circuit 200b of the signal transmission circuit 1000b, and the driver 3a are all connected to the output line 7, and operate with the output potential OUT as the reference potential. The output potential OUT changes between the potential G3 and the potential HV corresponding to the time of the on state of the switch elements 2a and 2b. The potential difference between the potential G3 and HV is, for example, several hundred to several thousand V.

[0169] The control circuit 4 and the first circuits 100a, 100b, 100x, and 100y are not directly connected to the output line 7. The control circuit 4 is DC-isolated from the drivers 3a and 3b and the switching elements 2a and 2b.

[0170] For example, even if the drivers 3a, 3b and the switching elements 2a, 2b are arranged in a high voltage region considering the potential HV, the control circuit 4 can be arranged in a low voltage region DC-isolated from the high voltage region. Such an arrangement helps prevent malfunction of the control circuit 4 and prevent electric shock.

[0171] <2-4. Output Potential OUT as Potential Reference of Second Circuit>

[0172] Assume the following situation: one or both of the second signals S2a and S2b are generated and used in the first embodiment. Figure 3 The phenomenon is similar to the high latching of the second signal S2 caused by the malfunction of the detection circuit 240 in the second circuit 200 described above. In this case, the second signals S2a and S2b both become "H", and the signal Qa sometimes does not function normally as a drive-on signal like the first signal S1a or a drive-off signal like the first signal S1b. The same is true for the signal Qb.

[0173] Thus, the signals Qa and Qb may not function properly as the drive on signal and the drive off signal, which may cause the switch elements 2a and 2b to be turned on at the same time. To avoid this phenomenon, it is preferred that the second signals S2a, S2b, S2x, and S2y do not generate the same phenomenon as the high latch of the second signal S2.

[0174] Signal transmission circuits 1000a, 1000b, 1000x, and 1000y are used in the power conversion device 2000. In the second circuits 200a, 200b, 200x, and 200y respectively, the same action as the second circuit 200 in the signal transmission circuit 1000 is obtained through the action of the self-reset circuits 241a, 241b, 241x, and 241y, which helps to prevent high latching from occurring in the second signals S2a, S2b, S2x, and S2y.

[0175] Therefore, in the power conversion device 2000 according to the second embodiment, malfunction of the switching elements 2a and 2b is suppressed.

[0176] <2-5. Changes in Potential G2>

[0177] The output potential OUT varies between the potentials G3 and HV by turning on and off the switch elements 2a and 2b. The variation of the potential G2 described using the signal transmission circuit 1000 is caused by, for example, the variation of the output potential OUT when the signal transmission circuit 1000 is used as the signal transmission circuits 1000a and 1000b. The variation of the output potential OUT also causes the time differential dv / dt of the voltage in the same manner as the variation of the potential G2.

[0178] For the sake of simplicity, the following example shows a case where the output potential OUT decreases toward the potential G3 when the switch element 2a is turned off and the switch element 2b is turned off (dv / dt<0). When the switch element 2a is turned off and the switch element 2b is turned on and the output potential OUT increases toward the potential HV, the time differential dv / dt has different positive and negative signs. Since the phenomenon caused by the time differential dv / dt is processed below, the flow direction of the displacement current is interpreted according to the positive and negative differences in the time differential dv / dt, and the following effects are obtained in any case.

[0179] In addition, the case where the potentials G1 and G3 are equal is assumed for explanation. Next, the phenomenon caused by the time differential dv / dt is processed, and it is assumed that the difference in DC voltage does not affect the time differential dv / dt itself, so the following effects can be obtained even when the potentials G1 and G3 are different.

[0180] For example, Figure 2 , Figure 3The rise of the voltage variation Vdif in the illustrated signal transmission circuit 1000 occurs before and after the fall of the illustrated first signal S1. The voltage variation Vdif is caused by, for example, the turning off of the switch element 2b in response to the fall of the first signal S1a when the signal transmission circuit 1000 is used as the signal transmission circuit 1000a.

[0181] in: Figure 2 , Figure 3 The voltage variation Vdif illustrated in FIG. 1 corresponds to a voltage rise caused by turning off the switch element 2b in response to a decrease in the logic value of the first signal S1a supplied to the signal transmission circuit 1000a. Figure 2 , Figure 3 The transition of the logic value of the first signal S1 illustrated in FIG. 1 corresponds to the transition of the logic value of the first signal S1a generated after the first signal S1a has a fall in response to the cutoff.

[0182] The switch element 2b is turned off in response to a drop in the logic value of a first signal S1a, which is delayed from the drop by the operation of the signal transmission circuit 1000a. Since the same delay occurs in the signal transmission circuit 1000, the above correspondence may occur.

[0183] Similar to the voltage variation Vdif in the signal transmission circuit 1000, in the signal transmission circuit 1000a, the potential of the third terminal P3a also rises at -(dv / dt)·Cpa·Ra^. Here, the symbol Cpa represents the electrostatic capacitance value of the parasitic capacitor Cpa, and the symbol Ra^ represents the resistance value of the equivalent resistor of the second circuit 200a. Similarly, in the signal transmission circuit 1000b, the potential of the third terminal P3b also rises at -(dv / dt)·Cpb·Rb^. Here, the symbol Cpb represents the electrostatic capacitance value of the parasitic capacitor Cpb, and the symbol Rb^ represents the resistance value of the equivalent resistor of the second circuit 200b.

[0184] These increases may result in Figure 3 For example, the parasitic capacitance Cpa is charged and discharged with a current represented by the product of the time differential dv / dt and the electrostatic capacitance value of the parasitic capacitance Cpa, and the parasitic capacitance Cpb is charged and discharged with a current represented by the product of the time differential dv / dt and the electrostatic capacitance value of the parasitic capacitance Cpb.

[0185] In the charging and discharging of the parasitic capacitance Cp by the clamp circuits 205 and 206 of the signal transmission circuit 1000 , similarly to the charging and discharging of the parasitic capacitances Cpa and Cpb, a current represented by the product of the time differential dv / dt and the electrostatic capacitance value of the parasitic capacitance Cp flows.

[0186] The parasitic capacitance Cpa is charged and discharged via one or both of the clamp circuits 205a and 206a. The parasitic capacitance Cpb is charged and discharged via one or both of the clamp circuits 205b and 206b. Similar to the clamp circuits 205 and 206 in the signal transmission circuit 1000, the clamp circuits 205a and 206a help suppress the charging and discharging of the parasitic capacitance Cpa, and the clamp circuits 205b and 206b help suppress the charging and discharging of the parasitic capacitance Cpb.

[0187] Fig. 9 1000a and 1000b are waveform diagrams illustrating how each signal in the signal transmission circuits 1000a and 1000b changes over time. Fig. 9 , the logic value of the input signal IN, the logic value of the first signal S1a, S1b, the logic value of the signal J1a, J1b, the received signal VR1a, VR2a, VR1b, VR2b, the signal VRO1a, VRO2a, VRO1b, VRO2b, the second signal S2a, S2b, and the logic value of the output potential OUT are shown as examples. Fig. 9 In FIG. 1 , the waveform of the voltage variation Vdif is also illustrated. Fig. 9 In FIG. 1 , the inversion of the logic value of the transmission signal VT2a is also shown together with the signal J1a by adding an overline to the label "VT2a".

[0188] The logic value of the input signal IN rises from "L" to "H" at time t_on. In response, the logic value of the first signal S1a also rises at time t_on, and the logic value of the first signal S1b falls from "H" to "L" at time t_on.

[0189] The logic value of the input signal IN drops from "H" to "L" at time t_off. In response, the logic value of the first signal S1a also drops at time t_off, and the logic value of the first signal S1b rises from "L" to "H" at time t_off.

[0190] The signal J1a outputs a pulse train during the period when the logic value of the first signal S1a is "H". Fig. 9 2 shows an example in which the signal J1a outputs four pulses during a period in which the logic value of the first signal S1a is "H". The signal J1b outputs a pulse train during a period in which the logic value of the first signal S1b is "H".

[0191] The received signals VR1a, VR2a, VR1b, and VR2b all change based on the output potential OUT. At the time point when the pulse in the signal J1a rises, the received signal VR1a temporarily rises and the received signal VR2a temporarily drops, and each shows a decaying waveform thereafter. The current ia flowing through the first coil 11a and the mutual inductance La between the first coil 11a and the second coil 12a are introduced, and the value of the received signal VR1a is represented by La·(dia / dt), and the value of the received signal VR2a is represented by -La·(dia / dt).

[0192] At the time point when the pulse in signal J1a falls, reception signal VR1a temporarily falls, reception signal VR2a temporarily rises, and each shows a decaying waveform thereafter. The value of reception signal VR1a at this time is represented by -La·(dia / dt), and the value of reception signal VR2a is represented by La·(dia / dt).

[0193] At the time point when the pulse in the signal J1b rises, the reception signal VR1b temporarily rises and the reception signal VR2b temporarily falls, and each shows a decaying waveform thereafter. The current ib flowing through the first coil 11b and the mutual inductance Lb between the first coil 11b and the second coil 12b are introduced, and the value of the reception signal VR1b is represented by Lb·(dib / dt), and the value of the reception signal VR2b is represented by -Lb·(dib / dt).

[0194] At the time point when the pulse in signal J1b falls, reception signal VR1b temporarily falls, reception signal VR2b temporarily rises, and each shows a decaying waveform thereafter. The value of reception signal VR1b at this time is represented by -Lb·(dib / dt), and the value of reception signal VR2b is represented by Lb·(dib / dt).

[0195] and Figure 2 Similarly, the voltage variation Vdif starts to rise from time t_dvdt. The waveform of the reception signal VR2a is shown as an example, in which at the time point when the pulse in the signal J1a rises during the rising period, the reception signal VR2a also rises together with the reception signal VR1a and then decays. Since no pulse train is generated in the signal J1b during the rising period, such an exceptional waveform is not generated in the reception signal VR2b.

[0196] The waveforms of the signals VRO1a, VRO2a, VRO1b, and VRO2b are similar to those of the received signals VR1a, VR2a, VR1b, and VR2b, respectively. Through the high-pass filter and DC compensation voltage circuit 225a obtained by the capacitor 221a and the voltage-dividing resistor 223a, the signal VRO1a shows the same rise and subsequent attenuation, and the fall and subsequent attenuation as the received signal VR1a with the DC voltage D1a as the reference. Through the high-pass filter and DC compensation voltage circuit 225a obtained by the capacitor 222a and the voltage-dividing resistor 224a, the signal VRO2a shows the same rise and attenuation as the received signal VR2a with the DC voltage D1a as the reference. Through the high-pass filter and DC compensation voltage circuit 225b obtained by the capacitor 221b and the voltage-dividing resistor 223b, the signal VRO1b shows the same rise and subsequent attenuation, and the fall and subsequent attenuation as the received signal VR1b with the DC voltage D1b as the reference. Through the high-pass filter obtained by the capacitor 222b and the voltage-dividing resistor 224b and the DC compensation voltage circuit 225b, the signal VRO2b shows the same rise and decay as the reception signal VR2b with reference to the DC voltage D1b.

[0197] exist Fig. 9 , the voltage change Vdif has little influence on the subtraction voltage value ΔVa (the potential difference between the signal VRO1a and the signal VRO2a, specifically, the value obtained by subtracting the potential of the signal VRO2a from the potential of the signal VRO1a) during the rising period, and the subtraction voltage value changes from a state less than the first threshold value to a state greater than or equal to the first threshold value. The example shows the case where the logic value of the second signal S2a rises from "L" to "H" according to the above action (i).

[0198] Fig.10 1000x and 1000y are waveform diagrams illustrating how each signal in the signal transmission circuits 1000x and 1000y changes over time. Fig.10 , the logic value of the input signal IN, the logic value of the first signal S1x, S1y, the logic value of the signal J1x, J1y, the received signals VR1x, VR2x, VR1y, VR2y, the signals VRO1x, VRO2x, VRO1y, VRO2y, the second signal S2x, S2y, and the logic value of the output potential OUT are shown as examples. Fig.10 In FIG. 1 , the inversion of the logic value of the transmission signal VT2x is also shown together with the signal J1x by adding an overline to the label "VT2x".

[0199] For example, since the first signals S1a and S1x exclusively take the logical value "H" and are activated, Fig.10 The waveforms of the logic values ​​of the first signals S1x and S1y in Fig. 9The waveforms of the logic values ​​of the first signals S1b and S1a in the circuit change in the same manner.

[0200] therefore, Fig.10 The waveforms of the logic values ​​of the signals J1x and J1y, the received signals VR1x, VR2x, VR1y, VR2y, the signals VRO1x, VRO2x, VRO1y, VRO2y, and the logic values ​​of the second signals S2x and S2y appear as respectively Fig.10 The waveforms of the logic values ​​of the signals J1b and J1a, the received signals VR1b, VR2b, VR1a, VR2a, the signals VRO1b, VRO2b, VRO1a, VRO2a, and the logic values ​​of the second signals S2b and S2a are the same.

[0201] exist Fig.10 , the voltage change Vdif also has a small influence on the subtraction voltage value ΔVy (the potential difference between the signal VRO1y and the signal VRO2y, specifically, the value obtained by subtracting the potential of the signal VRO2y from the potential of the signal VRO1y) during the rising period, and the subtraction voltage value changes from a state less than the first threshold value to a state greater than or equal to the first threshold value. The example shows the case where the logic value of the second signal S2y rises from "L" to "H" according to the above action (i).

[0202] However, since the signal transmission circuits 1000x and 1000y use the potential G3 as a potential reference, the received signals VR1x, VR2x, VR1y, and VR2y vary based on the potential G3. Since the DC compensation voltage circuit 225x outputs the DC voltage D1x based on the potential G3, the signals VRO1x and VRO2x vary based on the DC voltage D1x. Since the DC compensation voltage circuit 225y outputs the DC voltage D1y based on the potential G3, the signals VRO1y and VRO2y vary based on the DC voltage D1y.

[0203] At time t_on: the logic value of the second signal S2b is "L" (see Fig. 9 ), the logic value of the signal Qa (not shown) changes to "H" by the increase in the logic value of the second signal S2a; the logic value of the second signal S2x changes to "L" (refer to Fig.10 ), through the rise of the logic value of the second signal S2y, the logic value of the signal Qb (not shown) becomes "L"; the logic value of the output potential OUT becomes "H".

[0204] At time t_off: the logic value of the second signal S2a is "L" (see Fig. 9 ), the logic value of the second signal S2b rises, and the signal Qa (not shown) becomes "L"; the logic value of the second signal S2y is "L" (refer to Fig.10), through the rise of the logic value of the second signal S2x, the signal Qb (not shown) becomes "H"; the logic value of the output potential OUT becomes "L".

[0205] In this way, when the subtraction voltage value is less affected by the voltage variation Vdif, the logical value of the input signal IN is reflected in the logical value of the output potential OUT.

[0206] <2-6. Setting of current limiting resistor>

[0207] The resistor 207a of the clamp circuit 205a in the signal transmission circuit 1000a can be said to be a current limiting resistor that limits the magnitude of the current that flows through the diodes 201a and 202a and contributes to the charging and discharging of the parasitic capacitance Cpa. Similarly, the resistor 208a in the clamp circuit 206a can be said to be a current limiting resistor that limits the magnitude of the current that flows through the diodes 203a and 204a and contributes to the charging and discharging of the parasitic capacitance Cpa. Similarly, the resistors 207b and 208b in the signal transmission circuit 1000b, the resistors 207x and 208x in the signal transmission circuit 1000x, the resistors 207y and 208y in the signal transmission circuit 1000y, and the resistors 207 and 208 in the signal transmission circuit 1000 can all be said to be current limiting resistors.

[0208] Fig.11 This is a graph illustrating the rectification characteristics of a diode. The horizontal axis uses forward voltage, and the vertical axis uses forward current. This diode can be used for any of the diodes 201a, 202a, 203a, 204a, 201b, 202b, 203b, 204b, 201x, 202x, 203x, 204x, 201y, 202y, 203y, and 204y. Curve F1 represents the current flowing through the diode when no current limiting resistor is provided, and curve F2 represents the current flowing through the diode when a current limiting resistor is provided.

[0209] When a current limiting resistor is set, when a forward voltage VD is applied to the diode, a forward current iD flows. From the comparison of curves F1 and F2, it can be seen that by setting a current limiting resistor, the forward current is reduced. The current flowing through the clamp circuit 206a is equivalent to both the forward current iD flowing through the diode 201a and the forward current iD flowing through the diode 202a. The current flowing during the charging and discharging of the parasitic capacitor Cpa is the product of the electrostatic capacitance value of the parasitic capacitor Cpa and the time differential (dv / dt). Therefore, setting the resistor 207a corresponding to the assumed value of the time differential (dv / dt) helps to limit the displacement current for charging and discharging the parasitic capacitor Cpa, and even reduces the influence of the voltage variation Vdif on the received signals VR1a and VR2a, thereby suppressing the malfunction of the detection circuit 240a. The same setting for the resistor 208a helps to suppress the malfunction of the detection circuit 240b.

[0210] For example, when the output potential OUT is reduced by the conduction of the switch element 2b, it helps to limit the displacement current that flows through the diode 202a of the clamp circuit 205a and the diode 204a of the clamp circuit 206a to discharge the parasitic capacitance Cpa, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1a and VR2a, and even suppressing the malfunction of the detection circuit 240a. It helps to limit the displacement current that flows through the diode 202b of the clamp circuit 205b and the diode 204b of the clamp circuit 206b to discharge the parasitic capacitance Cpb, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1b and VR2b, and even suppressing the malfunction of the detection circuit 240b.

[0211] Similarly, when the output potential OUT rises due to the conduction of the switch element 2a, the displacement current that flows through the diode 201a of the clamp circuit 205a and the diode 203a of the clamp circuit 206a to charge the parasitic capacitance Cpa is limited, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1a and VR2a, and even suppressing the malfunction of the detection circuit 240a. The displacement current that flows through the diode 201b of the clamp circuit 205b and the diode 203b of the clamp circuit 206b to charge the parasitic capacitance Cpb is limited, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1b and VR2b, and even suppressing the malfunction of the detection circuit 240b.

[0212] Similarly, it helps to limit the displacement current that flows through the diode 201x of the clamp circuit 205x and the diode 203x of the clamp circuit 206x to charge the parasitic capacitance Cpx, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1x and VR2x, and even suppressing the malfunction of the detection circuit 240x. It helps to limit the displacement current that flows through the diode 202x of the clamp circuit 205x and the diode 204x of the clamp circuit 206x to discharge the parasitic capacitance Cpx, thereby reducing the influence of the voltage fluctuation Vdif on the received signals VR1x and VR2x, and even suppressing the malfunction of the detection circuit 240x.

[0213] Similarly, it helps to limit the displacement current that flows through the diode 201y of the clamp circuit 205y and the diode 203y of the clamp circuit 206y to charge the parasitic capacitance Cpy, thereby reducing the influence of the voltage variation Vdif on the received signals VR1y and VR2y, and even suppressing the malfunction of the detection circuit 240y. It helps to limit the displacement current that flows through the diode 202y of the clamp circuit 205y and the diode 204y of the clamp circuit 206y to discharge the parasitic capacitance Cpy, thereby reducing the influence of the voltage variation Vdif on the received signals VR1y and VR2y, and even suppressing the malfunction of the detection circuit 240y.

[0214] The setting of the resistors 207a, 208a, 207b, 208b, 207x, 208x, 207y, and 208y helps to suppress malfunction of the detection circuits 240a, 240b, 240x, and 240y, thereby helping the output potential OUT to appropriately reflect the input signal IN.

[0215] Similarly, in the signal transmission circuit 1000, setting the resistors 207 and 208 in accordance with the assumed value of the time differential (dv / dt) also limits the displacement current for charging and discharging the parasitic capacitance Cp. This limitation helps reduce the influence of the voltage variation Vdif on the received signals VR1 and VR2, and even suppresses the malfunction of the detection circuit 240. This helps the second signal S2 to properly reflect the signal J1, and even to properly transmit the first signal S1 to the second signal S2.

[0216] However, when a time differential (dv / dt) exceeding the expected value occurs, a displacement current caused by the time differential (dv / dt) may become larger than the charge / discharge current flowing as the forward current iD set by the current limiting resistor. In this case, a displacement current may also occur in the signal transmission circuits 1000a, 1000b, 1000x, and 1000y. Figure 3 High latch as described in .

[0217] Similar to how the self-reset circuit 241 in the signal transmission circuit 1000 helps avoid high latching, the self-reset circuits 241a, 241b, 241x, 241y each help avoid high latching in the signal transmission circuits 1000a, 1000b, 1000x, 1000y, thereby helping the output potential OUT to properly reflect the input signal IN.

[0218] In addition, the self-reset circuits 241a, 241b, 241x, and 241y each contribute to avoiding high latching in the detection circuits 240a, 240b, 240x, and 240y, but do not directly affect the waveform of the output potential OUT. The reason is that the second signals S2a and SS2b are input to the latch circuit 6a, and the second signals S2x and S2y are input to the latch circuit 6b, and the logic value of the output potential OUT is based on the logic value of the signal Qa output by the latch circuit 6a and the logic value of the signal Qb output by the latch circuit 6b.

[0219] For example, for the upper arm circuit 2000a, it is assumed that after the logic value of the first signal S1a changes from "H" to "L" and the logic value of the first signal S1b changes from "L" to "H", a high latch of the logic value of the second signal S2a is still maintained at "H" in the detection circuit 240a. At this time, it is possible that both the second signals S2a and S2b take the logic value "H", the logic value of the signal Qa becomes uncertain, and the logic value of the output potential OUT is maintained at "H".

[0220] However, if the logic value of the first signal S1a changes from "L" to "H" and the logic value of the first signal S1b changes from "H" to "L", the signal J1a generates a pulse train again while the logic value of the second signal S2b is "L". Due to the falling of the pulses in the pulse train, the logic value of the second signal S2a becomes "L", and the logic value of the output potential OUT becomes "L". As a result, the influence of the external load 1 on malfunctioning is reduced.

[0221] <3. Deformation of pulse train>

[0222] Embodiment 3 of the present invention relates to the transformation of the pulse train in the signals J1, J1a, J1b, J1x, and J1y. First, the pulse train in the signal J1a will be described below.

[0223] Fig.12 2 is a waveform diagram illustrating each signal in Implementation Example 3. Fig.12 , the logic value of the input signal IN, the logic value of the signal J1a, the received signals VR1a and VR2a, the logic value of the second signal S2a, and the logic value of the output potential OUT are shown as examples. Fig.12, the waveform of the voltage variation Vdif is also illustrated. The logic value of the input signal IN is the same as the logic value of the first signal S1a (see Fig. 9 ),exist Fig.12 The two are shown together in FIG.

[0224] The logic value of the input signal IN rises from "L" to "H" at time t_on, and falls from "H" to "L" at time t_off. The voltage variation Vdif starts to rise at time t_dvdt before time t_on, and is still rising at time t_on. Due to the drop in the logic value of the input signal IN generated before time t_on, the voltage variation Vdif sometimes starts to rise before time t_on as described above.

[0225] In the logic value of the signal J1a, a pulse train is generated during the period when the logic value of the first signal S1a is "H". Fig.12 The initial pulse of the logic value of the signal J1a rises at time t_on. During this rise, if there is no influence of the voltage variation Vdif, the received signal VR1a rises and the received signal VR2a falls. However, Fig.12 2 shows an example in which, at time t_on, due to the influence of the increasing voltage fluctuation Vdif, the reception signal VR2a also increases, and the subtraction voltage value does not exceed the first threshold value.

[0226] Due to the influence of such voltage fluctuation Vdif, the second signal S2a maintains "L" and does not reflect the initial pulse of the signal J1a. Fig.12 The dashed line in FIG. 1 shows a pulse that would be generated in the logic value of the second signal S2a if there were no influence of the voltage variation Vdif.

[0227] The second pulse of the logic value of the signal J1a rises at time t_r. At time t_r, the voltage variation Vdif is in a steady state, and the received signals VR1a and VR2a are not affected by the voltage variation Vdif. At time t_r, the received signal VR1a rises, the received signal VR2a falls, and the logic value of the second signal S2a rises. In the subsequent logic value of the second signal S2a, a pulse of a pulse train reflecting the logic value of the signal J1a is generated.

[0228] The logic value of the output potential OUT rises in response to the rise of the logic value of the second signal S2a. When the logic value of the second signal S2a reflects the initial pulse of the logic value of the signal J1a (see the pulse shown by the dot-dash line), the logic value of the output potential OUT rises at time t_on (see the dot-dash line). The logic value of the output potential OUT rises at time t_r due to the influence of the voltage variation Vdif.

[0229] The logic value of the output potential OUT decreases in response to the increase in the logic value of the second signal S2b (not shown). For example, in the second signal S2b, a pulse train is generated in response to the decrease in the input signal IN (see Fig. 9 ), so in Fig.12 2 shows an example in which the logical value of the output potential OUT drops at time t_off.

[0230] Since it is preferable that the rise of the logic value of the output potential OUT appropriately reflects the rise of the logic value of the input signal IN, when the initial pulse of the pulse train of the logic value of the signal J1a is not reflected in the logic value of the second signal S2a, it is preferable that the pulse generated next reflects the logic value of the second signal S2a. From such a viewpoint, generating a pulse train including a plurality of pulses in the logic value of the signal J1a helps the logic value of the second signal S2a to appropriately reflect the logic value of the signal J1a, and further, the output potential OUT, in particular, appropriately reflects the input signal IN in the rise of the input signal IN.

[0231] If at the time point of the second pulse rising ( Fig.12 For example, if the voltage change Vdif is also rising at time t_r, the pulse may not be reflected in the logic value of the second signal S2a. If the rising period is long, the number of pulses generated during the rising period in the pulse train generated by the logic value of the signal J1a is large. From this point of view, the pulse train can be continuously generated in the logic value of the signal J1a during the period when the logic value of the input signal IN is maintained at "H" and the logic value of the first signal S1a is maintained at "H".

[0232] However, the waveform of the received signal VR2a is distorted by the voltage fluctuation Vdif, and the malfunction that the subtraction voltage value does not exceed the first threshold value is not limited to the occurrence corresponding to all pulses that generate a rise during the rising period. The displacement current derived from the voltage fluctuation Vdif tends to decrease as the rising period is longer. The reason is that if the parasitic capacitance Cpa is small, the total amount of displacement current is small, and the longer the rising period is, the smaller the voltage fluctuation Vdif is.

[0233] Therefore, even if the rising period is assumed to be long, it is not necessary to generate a pulse train throughout the entire rising period. On the other hand, a voltage variation Vdif with a short rising period generates a large displacement current. Therefore, the pulse generating circuit 101a generates a pulse train C1 in the signal J1a from the time t_on when the first signal S1a rises to the time when the assumed value Ta passes. The assumed value Ta is set to the length assumed as the rising period related to the voltage variation Vdif caused by the displacement current having the minimum value that causes malfunction, or is set to be longer than the length.

[0234] Introduce the number N of pulses in the pulse train C1. There is a relationship of (N - 1)·T1 + Th < Ta < N·T1 among the assumed value Ta, the period T1 of a pulse, and the duration Th during which the pulse becomes "H" (in Fig.12 N = 4).

[0235] For example, when the assumed value Ta is assumed to be the potential difference between the potential HV and G3 of 1200V and the time differential (dv / dt) is 100kV / μs, it is set to 1200V / (100kV / μs) = 12ns.

[0236] After the assumed value Ta has elapsed from the time t_on, the pulse generation circuit 101a can also generate a pulse train (hereinafter temporarily referred to as the "second pulse train", and the pulse train from the time t_on to the elapsed assumed value Ta is also temporarily referred to as the "first pulse train") C2 in the signal J1a. From the viewpoint of improving the reliability of signal transmission from the input signal IN to the output potential OUT, it is preferable to generate the second pulse train C2.

[0237] It is possible that the first pulse train C1 has multiple pulses generated in a part of the period during which the logical value of the signal J1a takes "H", and the second pulse train C2 has multiple pulses generated after the first pulse train C1 in this part. The length of this part is the assumed value Ta.

[0238] From the viewpoint of reducing the consumption current, it is preferable not to generate the second pulse train C2. In addition, when generating the second pulse train C2 in the logical value of the signal J1a, a lower generation frequency than that of the first pulse train C1 helps reduce the consumption current. For example, the period T2 of a pulse in the second pulse train C2 is longer than the period T1 of a pulse in the first pulse train C1. In Fig.12 it is illustrated that the pulses of the second pulse train C2 also become "H" with a duration of the length Th.

[0239] Regarding the logical value of the signal J1b, during the period from the moment t_off (refer to Fig. 9 ) when the logical value of the first signal S1b rises to the elapsed assumed value Tb, the pulse generation circuit 101b generates a pulse train. The assumed value Tb is set to the length assumed as the rising period related to the voltage variation Vdif caused by the displacement current having the minimum value that causes malfunction, or set longer than this length.

[0240] Introduce the number M of pulses in this pulse train. There is a relationship of (M - 1)·T1 + Th < Tb < M·T1 among the assumed value Tb, the period T1 of a pulse, and the duration Th during which the pulse becomes "H".

[0241] After the assumed value Tb has passed from the time t_off, similarly to the second pulse train C2, from the viewpoint of improving the reliability of signal transmission from the input signal IN to the output potential OUT, it is preferred that the pulse generating circuit 101b generates a pulse train in the signal J1b. The period of this pulse train is longer than the period of the pulse train generated from the time t_off until the assumed value Tb has passed, which contributes to reducing current consumption.

[0242] The same transformation as the pulse train in the signals J1b and J1a can be applied to the pulse trains in the signals J1x and J1y, respectively. Similarly, the same transformation as the pulse train in the signal J1a can be applied to the signal J1.

[0243] <4. Regarding the First Variation of the First Circuit>

[0244] Embodiment 4 of the present invention relates to a first variation of the first circuit 100, 100a, 100b, 100x, 100y. First, the first variation of the first circuit 100 will be described below.

[0245] Fig.13 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 to which a first variation of the first circuit 100 is applied.

[0246] In the first variation, the first circuit 100 further includes a resistor 105. The resistor 105 includes one end connected to the first end P1 and the other end to which the potential VCC is applied. Figure 1 In the first circuit 100 shown in the example, the source of the transistor 103 is connected to the first terminal P1, but in the first variation, the one end of the resistor 105 is connected to the first terminal P1. The potential VT1 is the potential of the other end of the resistor 105, and is output from the first circuit 100 to the first terminal P1.

[0247] The resistance value of the resistor 105 is a value close to the resistance value of the on-resistance of the transistor 103 (hereinafter referred to as "on-resistance value"). Specifically, for example, a value of 90 to 110% of the on-resistance value is adopted, and preferably a value of 95 to 105% of the on-resistance value is adopted. Under the influence of the voltage variation Vdif, when the potential G2 serving as the reference of the second circuit 200 is higher than the potential G1 serving as the reference of the first circuit 100, a displacement current flows through the first circuit 100.

[0248] The approximation of the resistance value of the resistor 105 to the on-resistance value of the transistor 103 helps to reduce the difference between the displacement current flowing through one end of the first coil 11 and the first end P1 and the displacement current flowing through the other end of the first coil 11 and the second end P2, thereby preventing the malfunction described later caused by the difference. From this point of view, it is preferred that the wiring resistance from the power supply (not shown) that applies the potential VCC to the other end of the resistor 105 to the first end P1 is equal to the wiring resistance from the second end P2 to the power supply (not shown) that applies the potential G1 to the source of the transistor 104.

[0249] Even if the resistance value of the resistor 105 is different from the on-resistance value of the transistor 103, there is a difference in effect determined by the degree of the difference, and the effect of reducing the difference between the two displacement currents can be obtained.

[0250] Fig.14 and Fig.15 1 is a circuit diagram showing elements through which displacement currents Idev1 and Idev2 flow when the potential G2 rises relative to the potential G1 due to the influence of the voltage variation Vdif. Fig.14 A path through which the displacement current Idev2 flows via the transistor 103 is shown. Fig.15 The path of the displacement current Idev1 flowing through the resistor 105 is shown.

[0251] exist Fig.14 In the illustrated path, the displacement current Idev2 flows from the diode 203 and the resistor 208 of the clamp circuit 206 to the transistor 103 via the parasitic capacitance Cp parasitic on the transformer 10 between the second terminal P2 and the fourth terminal P4 .

[0252] exist Fig.15 In the illustrated path, the displacement current Idev1 flows from the diode 201 and the resistor 207 of the clamp circuit 205 to the resistor 105 via the parasitic capacitance Cp parasitic on the transformer 10 between the first terminal P1 and the third terminal P3 .

[0253] Here, the displacement currents Idev1 and Idev2 are generated in the transition period in which the time differential dv / dt is generated. The displacement currents Idev1 and Idev2 do not flow between the first terminal P1 and the second terminal P2 connected to the first coil 11 or between the third terminal P3 and the fourth terminal P4 connected to the second coil 12. This is because the displacement currents Idev1 and Idev2 generated in the transition period have high frequencies and the impedances of both the first coil 11 and the second coil 12 are high.

[0254] In adopting Figure 1In the case of the first circuit 100 illustrated, a potential difference is generated between the first terminal P1 and the second terminal P2 due to the on-resistance of the transistor 103 and the displacement current Idev2. This potential difference reduces the amplitude of the pulse of the signal J1 generated by the pulse generating circuit 101, and even affects the amplitude of the signals VRO1 and VRO2 input to the detection circuit 240, so that correct detection may not be performed, resulting in malfunction. The resistor 105 used in the first variation helps to suppress this potential difference and even helps to suppress this malfunction.

[0255] Fig.16 2 is a waveform diagram illustrating how each signal changes with time in the first variation of the first circuit 100. Specifically, Fig.16 , waveforms of the first signal S1, the signal J1, the potential difference ΔG, the currents I1 and I2, and the transmission signal VT2 are exemplified.

[0256] Current I1 flows through the first terminal P1, and current I2 flows through the second terminal P2. Figure 1 , the currents I1 and I2 are both positive in the direction from the first circuit 100 to the first coil 11. The value H1 of the first signal S1 corresponds to the logical value "H" of the first signal S1. The value L1 of the first signal S1 corresponds to the logical value "L" of the first signal S1. The value H2 of the transmission signal VT2 is based on the potential G1 and corresponds to the logical value "H" of the transmission signal VT2. The potential difference ΔG is the voltage (G1-G2) of the potential G1 based on the potential G2.

[0257] The dotted line waveform indicates Figure 1 The illustrated example shows a case where the first circuit 100 without the resistor 105 is used, and the waveform of the solid line shows a case where the first variation is used.

[0258] exist Fig.16 , the waveform of the voltage variation Vdif is also illustrated. The case where two phenomena occur in the first coil 11 with respect to the second coil 12, that is, the case where the time differential dv / dt increases and the case where it decreases, is illustrated.

[0259] As shown by the dot-dash line, the waveforms of the currents I1 and I2 are greatly different when there is no resistor 105. The reason is that the first terminal P1 is connected to the source of the transistor 103, and the second terminal P2 is connected to the drain of the transistor 103; the on-resistance of the transistor 103 exists between the first terminal P1 and the second terminal P2; and the resistance value from the first terminal P1 to the power supply to which the potential VCC is applied is different from the resistance value from the second terminal P2 to the power supply.

[0260] Due to the difference between the currents I1 and I2, the potential of the transmission signal VT2 is temporarily reduced. When the period during which the voltage variation Vdif rises overlaps with the period during which a pulse is generated in the logic value of the signal J1 due to the decrease in the time differential dv / dt, the pulses cancel each other out and disappear, which may cause a malfunction in which the first circuit 100 cannot correctly transmit the transmission signal VT2.

[0261] When the resistor 105 is provided, the path through which the displacement current Idev1 flows can be made uniform by adjusting the resistance value (see Fig.15 ) and the path through which the displacement current Idev2 flows (refer to Fig.14 ) are close. As a result, the waveforms of the currents I1 and I2 are similar, and the potential of the transmission signal VT2 is not likely to change, and the pulse is not likely to disappear. As a result, the resistor 105 helps prevent malfunction of the first circuit 100 and even helps output an appropriate second signal S2.

[0262] The first variation can be applied to the entire first circuit 100a, 100b, 100x, 100y. By such application, the first signals S1a, S1b, S1x, S1y, specifically, the pulse train generated in the signals J1a, J1b, J1x, J1y are appropriately reflected to obtain the second signals S2a, S2b, S2x, S2y. The application of the first variation helps the output potential OUT outputted by the power conversion device 2000 to appropriately reflect the input signal IN.

[0263] <5. Second Variation of the First Circuit>

[0264] Embodiment 5 of the present invention relates to a second variation of the first circuit 100, 100a, 100b, 100x, 100y. First, the second variation of the first circuit 100 will be described below.

[0265] Fig.17 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 to which a second modification of the first circuit 100 is applied. The second modification of the first circuit 100 has a configuration in which the resistor 105 of the first modification of the first circuit 100 is replaced with a transistor 106 in an on state.

[0266] Specifically, in the second variation, the first circuit 100 further includes a P-channel transistor 106. The transistor 106 includes a drain connected to the first terminal P1 and a source to which a fixed potential VCC is applied. Figure 1 In the first circuit 100 shown as an example, the potential VT1 is output from the source of the transistor 103 to the first terminal P1 , but in the second variation, the potential VT1 is output from the drain of the transistor 106 to the first terminal P1 .

[0267] For example, a potential G1 is applied to the gate of the transistor 106. The potential G1 is lower than the potential VCC applied to the source, and the transistor 106 is maintained in the on state.

[0268] The transistor 106 is a P-channel transistor having an on-resistance value that is slightly different from the on-resistance value of the transistor 103 .

[0269] Since both transistors 106 and 103 are P-channel transistors, the temperature characteristics of the on-resistance values ​​of the two are similar. The similarity of the temperature characteristics has the advantage that the effect of preventing the malfunction of the first circuit 100 is less dependent on the operating temperature environment of the first circuit 100 than in the fourth embodiment, and the above-mentioned effect can be easily obtained in a wide temperature range.

[0270] Even if the on-resistance values ​​of the transistors 103 and 106 are different from each other, there is a difference in effect determined by the degree of the difference, and the effect of reducing the difference between the above-mentioned two types of displacement currents can be obtained.

[0271] The transistor 103 may also be an IGBT. For example, when the transistor 103 is an IGBT, the transistor 106 may also be an IGBT. The collector and emitter of the IGBT may be said to be the first electrode and the second electrode that are mutually conductive by a signal applied to the gate. The gate may be said to be the third electrode that controls the conduction between the first electrode and the second electrode.

[0272] In the first circuit 100, the first terminal P1 and the source of the transistor 104 can be connected via an on-state N-channel transistor. In this case, the N-channel transistor has an on-resistance value that is slightly different from that of the transistor 104.

[0273] Even if the on-resistance value of the N-channel transistor is different from the on-resistance value of the transistor 103, there is a difference in effect determined by the degree of the difference, and the effect of reducing the difference between the above-mentioned two displacement currents can be obtained.

[0274] An IGBT may be used as the transistor 104. For example, when an IGBT is used as the transistor 104, an IGBT in an on state may be used instead of the above-mentioned N-channel transistor.

[0275] The second variation can be applied to the entire first circuit 100a, 100b, 100x, 100y. By such application, the first signals S1a, S1b, S1x, S1y, specifically, the pulse train generated in the signals J1a, J1b, J1x, J1y are appropriately reflected to obtain the second signals S2a, S2b, S2x, S2y. The application of the second variation helps the output potential OUT outputted by the power conversion device 2000 to appropriately reflect the input signal IN.

[0276] <6. Variations on Limitation of Displacement Current>

[0277] Reference Figure 1 and Fig.11 For example, in the clamp circuit 205, the higher the resistance value of the resistor 207 is, the greater the voltage drop across the resistor 207 is, and the higher the voltage borne by the diodes 201 and 202 is, which makes it easier to suppress the influence of the voltage variation Vdif.

[0278] The size of the current limiting resistor can also be set from the following viewpoints: For example, if the rectifying characteristics of the diodes 201 and 202 are improved in the clamp circuit 205, the displacement current can be limited even if the resistance value of the resistor 207 is reduced, and the resistor 207 can typically be omitted.

[0279] However, if the resistor 207 is omitted, the displacement current is suppressed, and the received signals VR1 and VR2 are also suppressed, which is not preferable from the perspective of transmitting signals. On the other hand, from the perspective of relaxing the limitation of the displacement current, it is not preferable to reduce the rectification characteristics of the diodes 201 and 202 and increase the resistance value of the resistor 207. It is preferable to set the resistor 207 taking such a trade-off into consideration. The same is true for the resistors 208, 207a, 208a, 207b, 208b, 207x, 208x, 207y, and 208y.

[0280] For example, the displacement current can be limited as follows in consideration of the appropriate voltage range of the detection circuit 240 , the DC voltage D1 , and the assumed time differential dv / dt.

[0281] The upper limit of the appropriate voltage range is substantially lowered by the clamp circuit 205. The lower limit of the appropriate voltage range is substantially raised by the clamp circuit 206. The substantial lowering and raising are described assuming that their absolute values ​​are 1V.

[0282] For example, even if the appropriate voltage range is 0 to 5V, the actual upper limit is lowered to 4V by the clamp circuit 205, and the actual upper limit is raised to 1V by the clamp circuit 206. When the appropriate voltage range is 0 to 5V, its central value 2.5V is used for the DC voltage D1. Moreover, when the actual upper limit of the appropriate voltage range is 4V and its actual lower limit is 0V by the clamp circuits 205 and 206, the DC voltage D1 can also be 2.5V. This is because the central value between these upper and lower limits is still 2.5V.

[0283] When the displacement current is limited by the clamp circuit 205 and not by the clamp circuit 206, the appropriate voltage range is substantially narrowed from 0 to 5 V to 0 to 4 V. In this case, the DC voltage D1 preferably uses a median value of 2 V between 0 and 4 V.

[0284] Alternatively, when the appropriate voltage range is 0 to 5V but the operation in the region near the boundary is unstable, the clamp circuits 205 and 206 may be used to substantially exclude the region where the operation is unstable. For example, when the operation of the detection circuit 240 is unstable at 0 to 0.5V, the clamp circuit 206 sets the actual lower limit of the appropriate voltage range to 0.5V. For example, when the operation of the detection circuit 240 is unstable at 4.5 to 5V, the clamp circuit 205 sets the actual upper limit of the appropriate voltage range to 4.5V. In this way, setting the clamp circuits 205 and 206 to substantially narrow the appropriate voltage range helps to avoid unstable operation of the detection circuit 240.

[0285] Assume that the appropriate voltage range is 0 to 5 V, and the DC voltage D1 has a central value of 2.5 V. The actual appropriate voltage range is narrowed to 2 to 3 V by the clamp circuits 205 and 206. In this case, if it is assumed that the fluctuation amount of the received signal VR1 increases due to the voltage fluctuation Vdif (see Figure 2 ), for example, when a change of 1 V occurs, the signal VRO1 rises to 3.5 (=2.5+1) V relative to the potential G2. At this time, the potential of the signal VRO1 exceeds the upper limit of the appropriate voltage range of the detection circuit 240, that is, 3 V, and the detection circuit 240 may malfunction.

[0286] When it is assumed that a voltage variation Vdif that causes such a variation in the reception signal VR1 occurs, the clamp circuit 205 is preferably designed so that the upper limit of the substantially appropriate voltage range is higher than 3.5 V, for example, 4 V. If the clamp circuit 205 is designed so that the upper limit of the substantially appropriate voltage range is 4 V and the DC voltage D1 is maintained at 2.5 V, the clamp circuit 206 is preferably designed so that the lower limit of the substantially appropriate voltage range is 1 V.

[0287] The clamp circuits 205a, 206a, 205b, 206b, 205x, 206x, 205y, and 206y can be designed in the same manner.

[0288] <7. Deformation of Lower Arm Circuit 2000b>

[0289] The output potential OUT is a reference for the potential in the signal transmission circuits 1000a and 1000b of the upper bridge arm circuit 2000a. Therefore, similarly to the potential G2 that is a potential reference in the signal transmission circuit 1000, it is preferable to reduce the influence of the voltage variation Vdif caused by the variation of the output potential OUT. In contrast, the potential G3 that is a potential reference in the signal transmission circuits 1000x and 1000y of the lower bridge arm circuit 2000b does not necessarily cause the voltage variation Vdif. From this point of view, the signal transmission circuits 1000x and 1000y do not necessarily have to adopt the same structure as the signal transmission circuit 1000.

[0290] Specifically, for example, the self-reset circuits 241x and 241y may be omitted in the signal transmission circuits 1000x and 1000y.

[0291] Furthermore, the various embodiments may be freely combined, and the various embodiments may be appropriately modified or omitted.

[0292] The various aspects of the present invention are summarized below as supplementary notes.

[0293] (Note 1)

[0294] A signal transmission circuit comprising:

[0295] a first circuit which receives a first signal as input, generates a transmission signal corresponding to a change in a logic value of the first signal, and operates based on a first potential;

[0296] a transformer including a first coil and a second coil, wherein the first coil is input with the transmission signal from the first circuit, and the second coil is inductively coupled with the first coil to output a pair of reception signals; and

[0297] a second circuit which receives the pair of received signals from the second coil, compares the potential difference between the pair of received signals with hysteresis to generate a second signal, and uses the second potential as a reference for operation;

[0298] The second circuit has:

[0299] a detection circuit that performs the comparison and outputs a result of detecting whether the potential difference exceeds a predetermined range as the second signal; and

[0300] The reset circuit resets the operation of the detection circuit when the logic value of the second signal is maintained for a predetermined period.

[0301] (Note 2)

[0302] The signal transmission circuit according to Supplementary Note 1, wherein:

[0303] The second circuit further includes a compensation circuit that generates a pair of third signals, the third signals being obtained by applying a DC voltage based on the second potential as a compensation voltage to the pair of reception signals.

[0304] The detection circuit generates the second signal by performing the comparison on the potential difference between the pair of third signals generated by the compensation circuit.

[0305] (Note 3)

[0306] The signal transmission circuit according to Supplementary Note 2, wherein:

[0307] The compensation circuit has:

[0308] a first input terminal to which one of the pair of received signals is input;

[0309] a second input terminal to which the other of the pair of received signals is input;

[0310] a first output terminal to which one of the pair of third signals is input;

[0311] a second output terminal to which the other of the pair of third signals is input;

[0312] a first resistor having one end connected to the first output terminal and the other end to which the DC voltage is applied;

[0313] a second resistor having one end connected to the second output terminal and the other end to which the DC voltage is applied;

[0314] a first capacitor connected between the first input terminal and the first output terminal; and

[0315] A second capacitor is connected between the second input terminal and the second output terminal.

[0316] (Note 4)

[0317] The signal transmission circuit according to Supplementary Note 3, wherein:

[0318] The second circuit further includes a first clamp circuit and a second clamp circuit, wherein the first clamp circuit and the second clamp circuit are connected in series between the first input terminal and the second input terminal.

[0319] The first clamping circuit comprises:

[0320] The first diode;

[0321] a second diode connected in parallel with the first diode, the forward direction of the second diode being opposite to the forward direction of the first diode; and

[0322] a first current limiting resistor connected in series with each of the first diode and the second diode,

[0323] The second clamping circuit comprises:

[0324] The third diode;

[0325] a fourth diode connected in parallel with the third diode, the forward direction of the fourth diode being opposite to the forward direction of the third diode; and

[0326] A second current limiting resistor is connected in series with each of the third diode and the fourth diode.

[0327] (Note 5)

[0328] A signal transmission circuit according to any one of Supplementary Notes 1 to 4, wherein:

[0329] The first circuit comprises:

[0330] a pulse generating circuit for generating a fourth signal, the fourth signal including a first pulse train having a plurality of pulses in a portion of a period in which the first signal takes a first logic value, and a second pulse train having a plurality of pulses following the first pulse train in the portion; and

[0331] an output circuit that generates the transmission signal in response to a change in the logic value of the fourth signal,

[0332] One cycle of the pulses in the second pulse train is longer than one cycle of the pulses in the first pulse train.

[0333] (Note 6)

[0334] The signal transmission circuit according to Supplementary Note 5, wherein:

[0335] The output circuit includes a transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode.

[0336] The first circuit further includes a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied.

[0337] (Note 7)

[0338] The signal transmission circuit according to Supplementary Note 5, wherein:

[0339] The output circuit includes a first transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode.

[0340] The first circuit further includes a second transistor in an on state, the second transistor having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied.

[0341] (Note 8)

[0342] A power conversion device, comprising:

[0343] Output line;

[0344] a first switching element having one end to which a fixed potential is applied and the other end connected to the output line;

[0345] a second switch element having one end connected to the output line and the other end to which a third potential is applied, the second switch element being exclusively connected to the first switch element;

[0346] A first signal transmission circuit, which adopts the signal transmission circuit described in any one of Supplementary Notes 1 to 5;

[0347] A second signal transmission circuit, which adopts the signal transmission circuit described in any one of Supplementary Notes 1 to 5;

[0348] a first latch circuit which outputs a signal for controlling whether the first switch element is allowed to be turned on, is set by the second signal output by the first signal transmission circuit, and is reset by the second signal output by the second signal transmission circuit,

[0349] The second potential in the first signal transmission circuit and the second potential in the second signal transmission circuit are both the potential of the output line.

[0350] (Note 9)

[0351] The power conversion device according to Supplementary Note 8, further comprising:

[0352] A third signal transmission circuit, which adopts the signal transmission circuit described in any one of Supplementary Notes 1 to 5;

[0353] A fourth signal transmission circuit, which adopts the signal transmission circuit described in any one of Supplementary Notes 1 to 5; and

[0354] a second latch circuit which outputs a signal for controlling whether the second switch element is allowed to be turned on, is set by the second signal output by the third signal transmission circuit, and is reset by the second signal output by the fourth signal transmission circuit;

[0355] The second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are both the third potential.

[0356] Description of the label

[0357] 2a, 2b switching element, 6a, 6b latch circuit, 7 output line, 10, 10a, 10b, 10x, 10y transformer, 11 first coil, 12, 12a, 12b, 12x, 12y second coil, 100, 100a, 100b, 100x, 100y first circuit, 101, 101a, 101b, 101x, 101y pulse generating circuit, 102, 102a, 102b, 102x, 102y output circuit, 103, 103a, 103b, 103x, 103y, 106 transistor, 105, 207, 207a, 207b, 207x, 207y, 208, 208a, 208b, 208x, 208y resistor , 200, 200a, 200b, 200x, 200y second circuit, 201~204, 201a~204a, 201b~204b, 201x~204x, 201y~204y diodes, 205, 205a, 205b, 205x, 205y, 206, 206a, 206b, 206x, 206y clamping circuit, 220, 220a, 220b, 220x, 220y compensation circuit, 221, 221a, 221b, 221x, 221y, 222, 222a, 222b, 222x, 222y capacitors, 223, 223a, 223b, 223x, 223y, 224, 224a, 224b , 224x, 224y voltage divider resistors, 240, 240a, 240b, 240x, 240y detection circuits, 241, 241a, 241b, 241x, 241y self-reset circuits, 1000, 1000a, 1000b, 1000x, 1000y signal transmission circuits, 2000 power conversion device, C1 first pulse train, C2 second pulse train, D1, D1a, D1b, D1x, D1y DC voltages, G1, G2, G3, HV, VCC potentials, i, ia, ib currents, J1, J1a, J1b, J1x, J1y, Qa, Qb, VRO1, VRO1a, VRO1b, VRO1x, VRO1y, VRO2, VR O2a, VRO2b, VRO2x, VRO2y signal, P1, P1a, P1b, P1x, P1y first terminal, OUT output potential, P5, P5a, P5b, P5x, P5y, P6, P6a, P6b, P6x, P6y input terminal, P7, P7a, P7b, P7x, P7y, P8, P8a, P8b, P8x, P8y output terminal, S1, S1a, S1x, S1y first signal, S2, S2a, S2b, S2x, S2y second signal, T1, T2 one cycle, Ta assumed value, VR1, VR1a, VR1b, VR1x, VR1y, VR2, VR2a, VR2b, VR2x, VR2y receiving signal,VT2, VT2a, VT2b, VT2x, VT2y send signals, ΔV, ΔVa, ΔVb, ΔVx, ΔVy subtraction voltage values. ,

Claims

1. A signal transmission circuit, comprising: a first circuit which receives a first signal as input, generates a transmission signal corresponding to a change in a logic value of the first signal, and operates based on a first potential; a transformer having a first coil and a second coil, wherein the first coil is input with the transmission signal from the first circuit, and the second coil is inductively coupled with the first coil to output a pair of reception signals; as well as a second circuit which receives the pair of received signals from the second coil, compares the potential difference between the pair of received signals with hysteresis to generate a second signal, and uses the second potential as a reference for operation; The second circuit has: a detection circuit that performs the comparison and outputs a result of detecting whether the potential difference exceeds a predetermined range as the second signal; as well as The reset circuit resets the operation of the detection circuit when the logic value of the second signal is maintained for a predetermined period.

2. The signal transmission circuit according to claim 1, wherein: The second circuit further includes a compensation circuit that generates a pair of third signals, the third signals being obtained by applying a DC voltage based on the second potential as a compensation voltage to the pair of reception signals. The detection circuit generates the second signal by performing the comparison on the potential difference between the pair of third signals generated by the compensation circuit.

3. The signal transmission circuit according to claim 2, wherein: The compensation circuit has: a first input terminal to which one of the pair of received signals is input; a second input terminal to which the other of the pair of received signals is input; a first output terminal to which one of the pair of third signals is input; a second output terminal to which the other of the pair of third signals is input; a first resistor having one end connected to the first output terminal and the other end to which the DC voltage is applied; a second resistor having one end connected to the second output terminal and the other end to which the DC voltage is applied; a first capacitor connected between the first input terminal and the first output terminal; as well as A second capacitor is connected between the second input terminal and the second output terminal.

4. The signal transmission circuit according to claim 3, wherein: The second circuit further includes a first clamp circuit and a second clamp circuit, wherein the first clamp circuit and the second clamp circuit are connected in series between the first input terminal and the second input terminal. The first clamping circuit comprises: The first diode; a second diode connected in parallel with the first diode, the forward direction of the second diode being opposite to the forward direction of the first diode; and a first current limiting resistor connected in series with each of the first diode and the second diode, The second clamping circuit comprises: The third diode; a fourth diode connected in parallel with the third diode, the forward direction of the fourth diode being opposite to the forward direction of the third diode; and A second current limiting resistor is connected in series with each of the third diode and the fourth diode.

5. The signal transmission circuit according to any one of claims 1 to 4, wherein: The first circuit comprises: a pulse generating circuit for generating a fourth signal, the fourth signal generating a first pulse train having a plurality of pulses in a portion of a period during which the first signal takes a first logic value, and a second pulse train having a plurality of pulses following the first pulse train in the portion; as well as an output circuit that generates the transmission signal in response to a change in the logic value of the fourth signal, One cycle of the pulses in the second pulse train is longer than one cycle of the pulses in the first pulse train.

6. The signal transmission circuit according to claim 5, wherein: The output circuit includes a transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode. The first circuit further includes a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied.

7. The signal transmission circuit according to claim 5, wherein: The output circuit includes a first transistor having a first electrode to which a fixed potential is applied, a second electrode to which the transmission signal is output, and a third electrode to which the fourth signal is applied to control conduction between the first electrode and the second electrode. The first circuit further includes a second transistor in an on state, the second transistor having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied.

8. A power conversion device, comprising: Output line; a first switching element having one end to which a fixed potential is applied and the other end connected to the output line; a second switch element having one end connected to the output line and the other end to which a third potential is applied, the second switch element being exclusively connected to the first switch element; A first signal transmission circuit, comprising the signal transmission circuit according to any one of claims 1 to 5; A second signal transmission circuit, which adopts the signal transmission circuit according to any one of claims 1 to 5; a first latch circuit which outputs a signal for controlling whether the first switch element is allowed to be turned on, is set by the second signal output by the first signal transmission circuit, and is reset by the second signal output by the second signal transmission circuit, The second potential in the first signal transmission circuit and the second potential in the second signal transmission circuit are both the potential of the output line.

9. The power conversion device according to claim 8, wherein: Also features: A third signal transmission circuit, which adopts the signal transmission circuit according to any one of claims 1 to 5; A fourth signal transmission circuit, which adopts the signal transmission circuit according to any one of claims 1 to 5; as well as a second latch circuit which outputs a signal for controlling whether the second switch element is allowed to be turned on, is set by the second signal output by the third signal transmission circuit, and is reset by the second signal output by the fourth signal transmission circuit; The second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are both the third potential.

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