Multi-phase switching converter

Abstract

A phase distributor in a phase controller of a multiphase switching converter detects and corrects errors during generation of a phase control signal for activating a plurality of phases. A phase distributor receives a common control signal of a transition type to indicate a moment when generated timing signals are valid, the valid states of the timing signals providing clocks for state changes of the respective phase control signals. The first error condition is that a plurality of timing signals are valid in one cycle of a common control signal. The first corrective action needs to avoid the first error condition within a first future period after the error detection. The second error condition is that no one timing signal is set to be valid when a transition type occurs on the common control signal. The second corrective action needs to avoid the occurrence of the second error condition within a second future period after the error detection.

Description

Priority declaration

[0001] This application claims priority to Indian Provisional Patent Application No. 202441008611, filed on February 8, 2024, entitled “Self-Correcting Phase Allocator for Multi-Phase Controller” and U.S. Patent Application No. 18 / 944,011, filed on November 12, 2024, entitled “Error Handling in Phase Control Signal Generation Process by Phase Controller of Multi-Phase Switching Converter”. The entire contents of the above Indian Provisional Patent Application and U.S. Patent Application are incorporated herein by reference to the extent not inconsistent with the description herein. Technical Field

[0002] Embodiments of the present invention generally relate to a multi-phase switching converter, and more particularly, to a multi-phase switching converter, a phase distributor, and a method for processing errors in a phase control signal generation process. Background Art

[0003] A switching converter is a component that converts an input alternating current (AC) voltage or direct current (DC) voltage of a certain magnitude into an output DC voltage of a desired magnitude by using and operating a switch, which is well known in the relevant art. A switching converter can be used as an independent power supply and is applied to voltage regulation modules used in various environments such as laptop computers and mobile phones.

[0004] Switching converters typically use multiple power stages that work together to produce a regulated DC voltage. Each power stage produces a corresponding portion of the required load current in a corresponding phase in a series of phases, so this type of switching converter is called a multi-phase switching converter.

[0005] The power stages are controlled by the phase controller via corresponding phase control signals. During a phase duration, one state of the phase control signal (e.g., a logic high level) causes the corresponding power stage to produce a corresponding portion of the load current during the phase duration. The phase control signal is timed according to a corresponding timing signal generated internally by the phase controller.

[0006] It is often the case that the generated phase control signal deviates from the ideal, which may result in undesirable consequences such as excessive ripple in the output current, reduced efficiency, failure to provide the required load current, etc. Various aspects of the present disclosure are directed to handling any such errors in generating the phase control signal by the phase controller. Summary of the invention

[0007] An embodiment of the present invention relates to a multi-phase switching converter for providing a regulated power supply voltage from an input voltage, the multi-phase switching converter comprising: a plurality of power stages, each power stage being used to receive a corresponding phase control signal, and when the corresponding phase control signal is in a first state, connecting the input voltage to a corresponding inductor, and when the corresponding phase control signal is in a second state, disconnecting the input voltage from the corresponding inductor; and a phase controller for generating the phase control signal, the phase controller comprising: a plurality of signal generators, each of which generates a corresponding phase control signal, and the phase control signal is timed to change to the first state according to the setting of a corresponding timing signal; and a phase distributor for receiving a common control signal with a conversion type for indicating the effective moment of each of the timing signals, and for generating the timing signal, wherein the phase distributor detects a first error condition at a first moment, the first error condition comprising that more than one of the timing signals is in an effective state in the same cycle of the common control signal, wherein the phase distributor performs a first corrective action to avoid the first error condition in a first future time period after the first moment.

[0008] In some embodiments, the phase distributor detects a second error condition at a second moment, wherein the second error condition includes that at the moment when the common control signal undergoes the type of transition, none of the timing signals is in a valid state, wherein the phase distributor performs a second corrective action to avoid the occurrence of the second error condition in a second future time period after the second moment.

[0009] In some embodiments, the phase distributor includes: a plurality of annular units, each of which corresponds to a corresponding power level among the plurality of power levels, wherein each of the plurality of annular units is configured to receive an input trigger signal, a phase enable signal, and generate an output trigger signal; wherein the plurality of annular units are connected in a ring so that the input trigger signal of each annular unit corresponds to the output trigger signal of the previous annular unit, wherein each annular unit includes a trigger triggered by the common control signal, wherein during normal operation, in one cycle of the common control signal, only the Q output of the trigger of one annular unit is in a valid state; a plurality of correction units, wherein each of the plurality of correction units corresponds to a corresponding annular unit among the plurality of annular units; and a detection module for detecting the first error condition and the second error condition; wherein the detection module detects the following error conditions: The column situation is detected as the first error situation: in the same cycle, the Q outputs of more than one trigger are in the first logic state; wherein the first corrective action includes: in the first future time period, the Q output of the first trigger that maintains the first logic state immediately before the first error situation occurs is maintained in the first logic state, and in the first future time period, the Q outputs of other triggers that maintain the first logic state are set to the second logic state; wherein the detection module detects the following situation as the second error situation: at the moment when the conversion type occurs, the Q output of none of the multiple triggers is in the first logic state; wherein the second corrective action includes: in the second future time period, the Q output of the trigger of only one annular unit is set to the first logic state, wherein the only one annular unit has the phase enable signal in the first logic state.

[0010] In some embodiments, the duration of the corresponding phase control signal in the first state is fixed, wherein the first future time period starts from the moment when the conversion type of the common control signal occurring after the first moment occurs; wherein the second future time period starts from the moment when the conversion type of the common control signal occurring after the second moment occurs; wherein the first logic state is a logic high level and the second logic state is a logic low level; wherein the conversion type is from a logic low level to a logic high level.

[0011] In some embodiments, each correction unit is configured to receive the phase activation signal, the phase enable signal, the first error detection input signal, the second error detection input signal and the third error detection input signal of the corresponding annular unit, and to generate a first error detection output signal, a second error detection output signal, a third error detection output signal, a first error correction signal and a second error correction signal; wherein the multiple correction units are connected in a sequential manner so that the first error detection input signal, the second error detection input signal and the third error detection input signal of a correction unit in the sequence of the multiple correction units respectively correspond to the first error detection output signal, the second error detection output signal and the third error detection output signal of a previous correction unit in the sequence of the multiple correction units; wherein each of the first error detection input signal, the second error detection input signal and the third error detection input signal of the first correction unit in the sequence of the multiple correction units is coupled to a constant reference potential.

[0012] In some embodiments, the phase distributor further comprises: a plurality of correction data selection multiplexers (MUXes), wherein each correction data selection MUX corresponds to a corresponding correction unit among the plurality of correction units; wherein the detection module comprises: a first inverter configured to receive a second error detection output signal of a last correction unit in the sequence of the plurality of correction units; a first OR gate configured to receive an output of the first inverter, the first error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a first OR output signal; and a first AND gate configured to receive the first OR output signal and the third error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a correction selection signal; wherein the plurality of correction units Each correction data selection MUX in the data selection multiplexer is configured to receive the corresponding first error correction signal and the second error correction signal of the corresponding correction unit as input, and receive the first error detection output signal of the last correction unit in the sequence of the multiple correction units as a selection signal, wherein, if the first error detection output signal of the last correction unit is a logic high level, the correction data selection MUX forwards the first error correction signal as the correction data signal, and if the first error detection output signal of the last correction unit is a logic low level, the correction data selection MUX forwards the second error correction signal as the correction data signal; wherein the control block is also used to receive the corresponding inductor current generated by each of the multiple power stages, and the common control signal is also based on the corresponding inductor current.

[0013] In some embodiments, each of the plurality of annular units includes: a second AND gate configured to receive the corresponding phase enable signal and the input trigger signal, and to generate a second AND output signal; a first MUX configured to receive the second AND output signal and the corresponding correction data signal of the corresponding correction data selection MUX as input, and to receive the correction selection signal as a selection signal, if the correction selection signal is a logic high level, the first MUX forwards the first error correction signal as the first MUX output, and if the correction selection signal is a logic low level, the first MUX forwards the second AND output signal as the first MUX output, wherein the trigger receives the first MUX output as the D input of the trigger; a second MUX configured to receive the Q output of the corresponding trigger and the input trigger signal as input, and receive the phase enable signal as a selection signal, if the phase enable signal is a logic high level, the second MUX forwards the Q output as the output trigger signal, and if the phase enable signal is a logic low level, the second MUX forwards the input trigger signal as the output trigger signal; and a third AND gate configured to receive the Q output of the corresponding trigger and the common control signal as input, and to generate the timing signal.

[0014] In some embodiments, each correction unit in the plurality of correction units includes: a fourth AND gate configured to receive the phase enable signal and the phase activation signal, and to generate a fourth AND output; a second OR gate configured to receive the fourth AND output and the second error detection input signal, and to generate the second error detection output signal; a fifth AND gate configured to receive the fourth AND output and the second error detection input signal, and to generate a fifth AND output; a third OR gate configured to receive the fifth AND output and the first error detection input signal, and to generate the first error detection output signal. a fourth OR gate configured to receive the third error detection input signal and the phase enable signal, and to generate the third error detection output signal; a second inverter configured to receive the third error detection input signal; a sixth AND gate configured to receive the output of the second inverter and the phase enable signal, and to generate the second error correction signal; a third inverter configured to receive the second error detection input signal; and a seventh AND gate configured to receive the output of the third inverter and the fourth AND output, and to generate the first error correction signal.

[0015] In some embodiments, a method for handling errors in the generation of phase control signals is provided, the method being performed by a phase controller of a multi-phase switching converter, the multi-phase switching converter being used to provide a regulated power supply voltage from an input voltage, the phase controller being used to provide corresponding phase control signals to a plurality of power stages, each power stage being used to connect the input voltage to a corresponding inductor when a corresponding phase control signal of the plurality of phase control signals changes to a first state, so that the plurality of power stages are used in cooperation to provide the regulated power supply voltage. The method comprises: generating a common control signal having a transition type to indicate the time when a plurality of timing signals are valid; generating a corresponding timing signal of the plurality of timing signals for each of the plurality of power stages, wherein the corresponding phase control signal is timed to change to the first state according to the setting of the corresponding timing signal; detecting a first error condition including more than one of the plurality of timing signals being in a valid state at the time when the common control signal appears the transition type; and performing a first corrective action to avoid the first error condition within a first future period after the first error condition is detected.

[0016] In some embodiments, the method includes: detecting a second error condition including that none of the timing signals is in a valid state at the moment when the conversion type occurs in the common control signal; and performing a second corrective action to avoid the occurrence of the second error condition in a second future time period after the second error condition is detected.

[0017] In some embodiments, the duration of the corresponding phase control signal in the first state is fixed, wherein the phase controller includes: a plurality of signal generators, wherein each signal generator receives a corresponding timing signal among the plurality of timing signals and generates a corresponding phase control signal among the plurality of phase control signals; and a phase distributor, which receives the common control signal and generates the plurality of timing signals.

[0018] In some embodiments, the phase distributor includes: a plurality of annular units, each of which corresponds to a corresponding power level among the plurality of power levels, wherein each of the plurality of annular units is configured to receive an input trigger signal, a phase enable signal, and generate an output trigger signal; wherein the plurality of annular units are connected in a ring so that the input trigger signal of each annular unit corresponds to the output trigger signal of the previous annular unit, wherein each annular unit includes a trigger triggered by the common control signal, wherein during normal operation, in one cycle of the common control signal, only the Q output of the trigger of one annular unit is in a valid state; a plurality of correction units, wherein each of the plurality of correction units corresponds to a corresponding annular unit among the plurality of annular units; and a detection module for detecting the first error condition and the second error condition; wherein the detection module The detection module detects the following situation as the first error situation: at the first moment, the Q outputs of more than one trigger are in the first logic state; wherein the first corrective action includes: within the first future time period, setting the Q output of the first trigger that maintains the first logic state immediately before the first error situation occurs to the first logic state, and setting the Q outputs of other triggers that maintain the first logic state to the second logic state within the first future time period; wherein the detection module detects the following situation as the second error situation: at the second moment, the Q output of none of the multiple triggers is in the first logic state; wherein the second corrective action includes: within the second future time period, setting the Q output of the trigger included in the first ring unit in the cyclic sequence to the first logic state, and the phase enable signal of the first ring unit is in the first logic state.

[0019] In some embodiments, the first future period starts from the moment when the conversion type of the common control signal occurs after the first moment; wherein the second future period starts from the moment when the conversion type of the common control signal occurs after the second moment; wherein the first logic state is a logic high level and the second logic state is a logic low level; wherein the conversion type is from a logic low level to a logic high level.

[0020] In some embodiments, each correction unit is configured to receive a phase activation signal, the phase enable signal, a first error detection input signal, a second error detection input signal, and a third error detection input signal of a corresponding annular unit, and to generate a first error detection output signal, a second error detection output signal, a third error detection output signal, a first error correction signal, and a second error correction signal; wherein the multiple correction units are connected in a sequential manner so that the first error detection input signal, the second error detection input signal, and the third error detection input signal of a correction unit in the sequence of the multiple correction units respectively correspond to the first error detection output signal, the second error detection output signal, and the third error detection output signal of a previous correction unit in the sequence of the multiple correction units; wherein each of the first error detection input signal, the second error detection input signal, and the third error detection input signal of the first correction unit in the sequence of the multiple correction units is coupled to a constant reference potential.

[0021] In some embodiments, the phase distributor further comprises: a plurality of correction data selection multiplexers (MUXes), wherein each correction data selection MUX corresponds to a corresponding correction unit among the plurality of correction units; wherein the detection module comprises: a first inverter configured to receive a second error detection output signal of a last correction unit in the sequence of the plurality of correction units; a first OR gate configured to receive an output of the first inverter, the first error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a first OR output signal; and a first AND gate configured to receive the first OR output signal and the third error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a correction selection signal; wherein the plurality of correction units Each correction data selection MUX in the data selection multiplexer is configured to receive the corresponding first error correction signal and the second error correction signal of the corresponding correction unit as input, and receive the first error detection output signal of the last correction unit in the sequence of the multiple correction units as a selection signal, wherein, if the first error detection output signal of the last correction unit is a logic high level, the correction data selection MUX forwards the first error correction signal as a correction data signal, and if the first error detection output signal of the last correction unit is a logic low level, the correction data selection MUX forwards the second error correction signal as a correction data signal; wherein the control block is also used to receive the corresponding inductor current generated by each of the multiple power stages, and the common control signal is also based on the corresponding inductor current.

[0022] In some embodiments, a phase distributor of a phase controller of a multi-phase switching converter is provided, wherein the phase controller is used to provide corresponding phase control signals to multiple power stages of the multi-phase switching converter, each power stage is configured to connect a power supply to a corresponding inductor when the corresponding phase control signal is valid, so that the multiple power stages are used to cooperate to provide a regulated power supply voltage, and the phase distributor includes: multiple annular units, which are arranged to be connected in an annular manner, wherein each annular unit corresponds to a corresponding power stage among the multiple power stages, and includes a trigger triggered by a common control signal generated by a control block of the phase controller, wherein during normal operation, the Q outputs of each of the triggers are sequentially set to valid in a cyclic manner, thereby triggering the start of a corresponding phase control signal among the multiple phase control signals, and during normal operation, at any of the common control signals In any cycle, the Q output of the trigger of only one annular unit is set to valid; a plurality of correction units, wherein each of the plurality of correction units corresponds to a corresponding annular unit in the plurality of annular units and is used to receive a first group of signals from the corresponding annular unit, and each correction unit is used to provide a corresponding correction signal to the corresponding annular unit when one or more error conditions occur in the plurality of annular units; and a detection module, which is configured to receive a second group of signals from the plurality of correction units, the detection module is used to detect the one or more error conditions based on the second group of signals, and generate an output signal coupled to each annular unit in the plurality of annular units when an error condition is detected, the output signal being used to enable each of the corresponding correction signals to perform a part of a correction action in the corresponding annular unit.

[0023] In some embodiments, the one or more error conditions include a first error condition, wherein: in the same cycle of the common control signal, the Q outputs of more than one trigger are valid; wherein the multiple correction units generate the correction signal to continue to keep valid the Q output of the trigger that was set valid immediately before the first error condition occurred, and to cancel the Q outputs of other triggers that were set valid in a future cycle after the same cycle.

[0024] In some embodiments, the future cycle is the next cycle after the same cycle.

[0025] In some embodiments, the one or more error conditions include a second error condition, wherein the Q output of none of the multiple triggers is set to valid within the same cycle of the common control signal; wherein the multiple correction units generate the correction signal so that in a future cycle after the same cycle, the Q output of only one trigger of the ring unit is set to valid.

[0026] In some embodiments, the future cycle is the next cycle after the same cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments of the present disclosure will be described with reference to the accompanying drawings, which are briefly described below.

[0028] Figure 1 is a block diagram of an example system in which aspects of the present disclosure may be implemented.

[0029] Figure 2 is a block diagram showing details of a multi-phase switching converter in an embodiment of the present disclosure.

[0030] Figure 3 is a flow chart illustrating the manner in which a phase controller handles errors in the generation of a phase control signal according to an aspect of the present disclosure.

[0031] Figure 4A is a block diagram showing an implementation of a phase controller in an embodiment of the present disclosure.

[0032] Figure 4B is a timing diagram illustrating an error condition in the timing signal generation process in the first scenario in an embodiment of the present disclosure.

[0033] Figure 4C is a timing diagram illustrating correction of an error condition in the first scenario in an embodiment of the present disclosure.

[0034] Figure 4D is a timing diagram illustrating an error condition in the timing signal generation process under the second scenario in an embodiment of the present disclosure.

[0035] Figure 4E is a timing chart illustrating correction of an error condition in the second scenario in an embodiment of the present disclosure.

[0036] Figure 5 is a block diagram showing an implementation of a phase distributor in a phase controller in an embodiment of the present disclosure.

[0037] Figure 6 is a diagram showing an implementation of a ring unit in a phase distributor in an embodiment of the present disclosure.

[0038] Figure 7 is a diagram showing an implementation of a correction unit in a phase distributor in an embodiment of the present disclosure.

[0039] Figure 8 is a diagram showing in more detail the implementation of the phase distributor in the embodiment of the present disclosure.

[0040] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION 1. Overview

[0041] Aspects of the present disclosure relate to a multiphase switching converter that provides a regulated supply voltage to an input voltage. The multiphase switching converter includes a plurality of power stages, each of which receives a corresponding phase control signal. The phase controller of the multiphase switching converter includes a signal generator and a phase distributor, wherein each signal generator generates a corresponding phase control signal, and the phase control signal is transformed to a first state (e.g., a logical high level) in a chronological order / timing according to the assertion / validity / triggering (assertion) of a corresponding timing signal. The phase distributor receives a common control signal with a transition / conversion / jump type (e.g., from a low level to a high level), and the common control signal is used to indicate the time instance (each moment / time point) at which the corresponding timing signal will take effect / valid (asserted).

[0042] According to one aspect of the present disclosure, a phase distributor detects a situation in which more than one timing signal is set valid at a first time instance within a cycle of a common control signal as a first error condition; and the phase distributor performs a first corrective action to avoid the occurrence of the first error condition in a first future time period after the first time instance.

[0043] According to another aspect of the present disclosure, when a corresponding transition type occurs on the common control signal, the phase distributor detects the situation in which no timing signal is set valid at a second time instance as a second error condition; and the phase distributor performs a second corrective action to avoid the second error condition in a second future time period after the second time instance.

[0044] In an embodiment, the phase distributor includes a plurality of annular units and a plurality of correction units, wherein each annular unit corresponds to a corresponding power level and each correction unit corresponds to a corresponding annular unit. The annular units are sequentially connected in an annular shape so that an input trigger signal of each annular unit corresponds to an output trigger signal of a previous annular unit, wherein a first annular unit receives an output trigger signal of a last annular unit. Each annular unit includes a flip-flop triggered by a common control signal.

[0045] Several aspects of the present disclosure will be described below with reference to examples for illustration. However, those skilled in the relevant art will recognize that the present disclosure can still be put into practice in the absence of one or more specific details, or in the case of using other methods, components, materials, etc. In other cases, in order to avoid obscuring the features of the present disclosure, well-known structures, materials or operations are not described in detail. In addition, for the sake of brevity, only some combinations are described herein, but the described features / aspects can be put into practice in various combinations. 2. Example System

[0046] Figure 1 1 is a block diagram of an example system in which aspects of the present disclosure may be implemented. System 100 is shown to include a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and peripherals 150. In one embodiment, system 100 corresponds to a computer (desktop, laptop, etc.), although in other embodiments system 100 may represent other types of systems. It should be understood that system 100 may include more than one computer. Figure 1 More or fewer components than shown.

[0047] CPU 120 generally represents a processor or system-on-chip (SoC), and is shown as receiving a pair of supply voltages (Va and Vb) from power supply 110 on respective paths 112A and 112B. As an example, Va can be a smaller voltage than Vb and can be used to power the core portion of CPU 120, which can include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb can be used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals to power supply 110 (all considered to be transmitted via path 121), which specify, among other things, its power requirements. Such signals can be those that specify a particular operating mode (in terms of power consumption), such as signals such as PS1, PS2, PS3, etc., which refer to "power saving states for improved efficiency".

[0048] The memory 130 may include volatile memory, non-volatile memory, etc. For example, in a personal computer, the memory may include magnetic memory (hard disk) and solid-state memory (RAM, flash memory, etc.). The memory 130 is shown as receiving a supply voltage through a path 113 to power various circuits and modules within it.

[0049] The network interface 140 is used to provide two-way communication between the system 100 and a computer network or the general Internet. The network controller implements the electronic circuits required to communicate using a specific physical layer and data link layer standard (such as Ethernet or Wi-Fi (TM)). The network interface 140 may also include a network protocol stack to allow communication with other computers in the same local area network (LAN) and large-scale network communication through routable protocols (such as the Internet Protocol (IP)). The network interface 140 receives power supply through path 114 to power its internal circuits and modules. The network interface 140 communicates with external systems through path 141 and communicates with the CPU 120 through path 124.

[0050] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power via path 115 and communicates with external devices via path 151 .

[0051] The power supply 110 receives power from one or more power sources (e.g., a battery) via path 101 and is used to provide the required supply voltages on paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is configured to include one or more DC-DC converters therein to generate the supply voltages. The power supply 110 responds to signals received from the CPU 120 via path 121 and reduces / increases the output voltage based on specific signals (e.g., PS1, PS2, and PS3).

[0052] In an embodiment, the power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more voltage regulators. The voltage regulator includes a step-down switching (buck) converter for generating a number of lower voltages from a higher voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost, buck-boost, hysteretic converters, etc., can be used instead of a buck converter. With the help of VRM, multiple devices / ICs requiring different power supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer (PC). Therefore, the following will focus on such as Figure 2 The description continues with the illustrated VRM implemented as a multi-phase switching converter. 3. Multi-phase switching converter

[0053] Figure 2 is an example of the present disclosure ( Figure 1 1. A block diagram of the details of power supply 110 is shown in FIG. 1. Power supply 110 is implemented as a multiphase switching converter that can generate two regulated power supplies (supply rails) Va (node ​​240) and Vb (node ​​250). And the power supply 110 is shown as including a phase controller 210, smart power stages (SPSs) or power stages (including SPSA-1 220-1 to SPSA-6 220-6 and SPSB-1 ​​230-1 to SPSB-3 230-3), inductors 225A-1 to 225A-6, inductors 227B-1 to 227B-3, output capacitors 226A-1 to 226A-6, output capacitors 228B-1 to 228B-3, and bootstrap capacitors 224A-1 to 224A-6, bootstrap capacitors 224B-1 to 224B-3.

[0054] In this example, the power supply Va (node ​​240) is generated by a six-phase buck converter (i.e., six SPSs 220-1 to 220-6), while the power supply Vb (node ​​250) is generated by a three-phase buck converter (i.e., three SPSs 230-1 to 230-3). Nodes / paths 240 and 250 correspond to Figure 1 For simplicity, Figure 2 Other power supply circuits that generate power on paths 113, 114 and 115 are not shown.

[0055] Power stages 220-1 to 220-6 and power stages 230-1 to 230-3 may be referred to hereinafter by corresponding numbers 220 and 230, respectively, as the context requires, as will be clear from the context. In addition, signals / nodes / paths 211-1 to 211-6, 213-1 to 213-6, 215-1 to 215-6, 216-1 to 216-3, 218-1 to 218-3, 229-1 to 229-3 may be referred to by corresponding numbers 211, 213, 215, 216, 218, and 229, respectively, as will be clear from the context. Similar conventions are followed for other modules / components / signals throughout the disclosure.

[0056] Each bootstrap capacitor associated with an SPS is shown connected between the respective nodes SW and BOOT of the respective SPS. Thus, the bootstrap capacitor 224A-1 is shown connected between the switch nodes SWA-1 221 and BOOTA-1 215-1. Although the bootstrap capacitors are shown connected to the outside of each SPS, in alternative embodiments, the bootstrap capacitors may also be internal to the SPS.

[0057] The combination of phase controller 210, power stage, inductor and capacitor (and corresponding circuitry therein) forms one "phase" of a multi-phase switching converter. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions within phase controller 210 represent one phase of a six-phase buck converter.

[0058] Each power stage can be implemented to include a high-side switch, a low-side switch, gate drive circuits for the two switches, and other circuits. Examples of other circuits include, but are not limited to, temperature monitoring circuits, inductor-current sensing (or simulation) circuits, etc., to provide information such as the temperature of the SPS / power stage, the magnitude of the inductor current, etc. to the phase controller 210. Each SPS receives a power supply as an input, which is connected to the high-side switch. In Figure 2, the power supply is numbered 201 and has a voltage Vin. In one embodiment, the value of Vin is 21 volts (V), and Va and Vb are 3.3V and 1.8V respectively. Each SPS is also shown as receiving a voltage Vcc through path 202. In one embodiment, the voltage Vcc is 3.3V, which is provided by the phase controller 210.

[0059] Each SPS communicates with the phase controller 210 via respective signals PWM, CS, and TMP. Thus, SPSA-1 is shown connected to the phase controller 210 via path 211 (with signal PWMA-1 thereon), path 213 (with signal CSA-1 thereon), and path 214 (with signal TMPA thereon). SPSA-6 communicates with the phase controller 210 via signals PWMA-6, CSA-6, and TMPA (signals on path 214). Similarly, SPSB-1 ​​is shown connected to the phase controller 210 via path 216 (signal PWMB-1), path 218 (signal CSB-1), and path 219 (signal TMPB). SPSB-3 communicates with the phase controller 210 via signals PWMB-3, CSB-3, and TMPB (signals on path 219). The other SPSs have similar connections to the phase controller 210.

[0060] Signal TMP is a signal output from the SPS to the phase controller 210 and provides information about the temperature in the SPS, etc. The phase controller 210 can process the TMP signal (or the information included therein) to adjust the current provided by the phase, or for shutdown of the VRM. The TMP outputs of each phase of the converter are connected together and connected to the phase controller 210 through a separate input.

[0061] The signal CS (current sense) is a signal input from the SPS to the phase controller 210 and includes information indicating the magnitude of the inductor current of the phase. This information may be in the form of current, voltage, digital value, etc.

[0062] The signal PWM is a signal input from the phase controller 210 to the SPS, and can be regarded as a "phase control signal" that controls the operating state (ON and OFF state) of the power switch in the SPS of the corresponding phase. In an embodiment of the present disclosure, the phase controller 210 uses a constant-ON-time control technique to generate Va and Vb. Therefore, in such an embodiment, the signal PWM is a variable frequency, fixed pulse width (constant on-time) signal (i.e., a pulse frequency modulated signal, but for ease of reference, the acronym PWM is still used herein to refer to such a signal). The frequency of the signal is typically proportional to the desired regulated voltage (Va or Vb), the input voltage, and the load current. However, in general, depending on the specific implementation details of the power supply 110, the signal PWM may also be of other types.

[0063] When the SPS detects a logic low level (LOW) on the signal PWM, the low-side switch is turned on; and when the SPS detects a logic high level (HIGH) on the signal PWM, the high-side switch is turned on. When a high impedance (hi-Z) state (usually the mid-rail voltage between the power supply and the ground) is detected on the signal PWM, the SPS turns off both its high-side switch and its low-side switch. Therefore, when the corresponding signal PWM switches between the high and low states, the SPS is said to be in an "enabled" state, and when the corresponding signal PWM is in the hi-Z state, the SPS is said to be in a "disabled" state. In other words, when the SPS detects a high impedance (hi-Z) value on the signal PWM and the duration exceeds a predetermined threshold, the SPS will not operate to generate voltage or provide current. When the corresponding signal PWM is in a logic high state, the SPS is said to be in an "activated / active" state, and the SPS drives current from Vin into its inductor.

[0064] The power stages of the power rails operate in a staggered and sequential manner to provide current. In other words, the signals PWM sent to each SPS of the multi-phase switching converter 110 are staggered / interleaved, that is, they are delayed in phase relative to each other, and the conduction durations of these SPSs may overlap, depending at least on the load demand. However, under normal circumstances (without any errors), no two PWM signals will be activated (transformed to, for example, a logic high level) at the same time (or at almost the same time), because such simultaneous transitions may cause undesirable effects, such as large ripples in the output regulated voltage.

[0065] The phase controller 210 controls the operation of the power stage through the above-mentioned signals to provide various functions including regulation functions, so that the corresponding groups of power stages can generate regulated voltages Va and Vb. Therefore, the voltages Va and Vb are shown as being provided as inputs to the phase controller 210 so that one or more feedback loops within the phase controller 210 can operate to regulate the voltages Va and Vb. The phase controller 210 also receives inductor current information (the current flowing through each inductor) from each of the SPSs to implement various operations such as current mode control of voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS in the same power rail (e.g., power rail Va) so that the current from each SPS is substantially equal. The phase controller 210 may also perform various other operations that are not mentioned here for the sake of brevity.

[0066] The phase controller 210 is also used to control the power stage to reduce or increase the current output according to the load demand. In addition, the phase controller 210 can also receive signals from the CPU 120, which indicate the desired power state (e.g., PS1, PS2, etc. mentioned above) for the CPU to continue to operate. In response, the phase controller 210 can disable / enable one or more power stages 220 according to the power state and load current conditions.

[0067] The phase controller 210 implemented according to aspects of the present disclosure handles errors in the generation of the signal PWM, which will be described below by way of example. 4. Flowchart

[0068] Figure 3 1 is a flow chart showing the manner in which a phase controller of a multi-phase switching converter according to one aspect of the present disclosure handles errors in the process of generating a PWM signal. Figure 1 and Figure 2 The flowcharts described in the system / multi-phase switching converter are for illustrative purposes only. However, without departing from the scope and spirit of the various aspects of the present disclosure, many features can also be implemented in other systems and / or other environments, which will be apparent to those skilled in the relevant art by reading the disclosure provided herein.

[0069] In addition, as will be apparent to those skilled in the relevant art, some or all of the steps may be performed in a different order than described below, as appropriate for a particular environment. Many such embodiments are expected to be included in the various aspects of the present disclosure. The flow chart begins at step 301, and the method then immediately proceeds to step 305.

[0070] In step 305 , the phase controller 210 generates a common control signal having a transition type (eg, from a logic low level to a logic high level) to indicate the moment when the timing signal is valid (asserted). The common control signal is generated internally by the phase controller 210 .

[0071] In step 310, the phase controller 210 generates a phase control signal (PWM signal) to the power stage (e.g., SPSA 220) based on the time of the common control signal transition type. Specifically, the PWM signal is timed to transition to a first state (e.g., a logic high level) based on the validity (setting) of the corresponding timing signal. As described above, the time when the timing signal is valid (set) is in turn indicated by the corresponding transition of the common control signal (e.g., from a logic low level to a logic high level).

[0072] Under normal (error-free) operation, at a certain moment (or in response to an instance / moment) of the transition type of the common control signal, only one timing signal will be in an effective (set) state. This technique is adopted for reasons such as improving the efficiency of the switching converter and reducing the ripple in the output regulated voltage. In other words, under normal operation, the timing signals generated within the phase controller 210 are always sequential and staggered. Then, the control flow goes to step 320.

[0073] In step 320, the phase controller 210 checks whether more than one timing signal is in a valid (set) state at a certain time / instance of the transition type of the common control signal. Multiple (more than one) timing signals being valid (set) at the same time may cause adverse effects such as reduced efficiency, larger ripple in the output regulation voltage, etc. If it is determined that such an error condition exists, the control flow will transfer to step 330, otherwise it will transfer to step 340.

[0074] In step 330, phase controller 210 performs corrective action to prevent the error condition described in step 320 from occurring again in the future period after the error condition is detected. Such corrective action may involve only making a single timing signal active (set) in the future period after the error is detected (e.g., in the next or subsequent cycle of the common control signal). Then, control flow returns to step 310.

[0075] In step 340, the phase controller checks whether none of the timing signals is in a valid (e.g., transitioning to a logic high) state at a certain moment / time instance of the transition type of the common control signal. When none of the timing signals is in a valid state, all SPSs will not operate, and accordingly, the regulated voltage amplitude may begin to drop, and / or the load current demand may not be met. If it is determined that such an error condition exists, the control flow will transfer to step 360, otherwise it will transfer to step 310.

[0076] In step 360, phase controller 210 performs corrective action to avoid the error condition indicated in step 340 in future time periods after the error condition is detected. Such corrective action may require only a single timing signal to be in an active (set) state in future time periods after the error is detected (e.g., in the next or subsequent cycles of the common control signal). Control then passes to step 310.

[0077] Thus, the phase controller of the present disclosure provides error handling in the generation of timing signals (and thus phase control signals) in a multi-phase switching converter.

[0078] Next, implementation details of a phase controller for handling errors in the phase control signal generation process in one embodiment of the present disclosure will be provided. 5. Phase controller

[0079] Figure 4A 4 is a block diagram showing implementation details of a phase controller in an embodiment of the present disclosure. The phase controller 210 is shown to include an error amplifier 405, a PWM generator 410, a phase distributor 420, an on-time generator (T-ON Gen / T-ON generator) 425-1 to T-ON Gen 425-6, a phase enable controller 415, and an adder 413. For ease of understanding and clarity, power stages 220-1 to 220-6 and corresponding inductors and capacitors are also shown in the figure. For ease of understanding, Figure 4A Only the six-phase converter including power stages SPSA-1 220-1 to SPSA-6 220-6 that cooperatively generate voltage Va (node ​​240) is shown. In addition, it should be noted that Figure 4A Only components relevant to understanding the present disclosure are shown. It should be understood that the phase controller 210 may include Figure 4A. In addition, for illustration only, the phase controller 210 is described as using a constant on-time control technique. However, it should be understood that the phase controller 210 may also use other types of control techniques. The internal modules of the phase controller 210 may be powered by a power supply not shown.

[0080] Vref represents a target voltage that is desired to be provided at Va of node 240. Therefore, Vref represents a stable reference DC voltage that is generated internally in the phase controller 210 in a known manner. The error amplifier 405 receives the voltage Vref on the reference path 401 (or a portion of the voltage Va via a voltage divider network), the voltage Va on the path / node 240, and generates a voltage Vc1 on the path 403 representing the difference between the voltage Vref on the path 401 and the voltage Va on the path 240, which forms one input of the PWM generator 410. The adder 413 adds the sensed inductor currents flowing through the respective inductors to generate a sum signal Isum on the path 407, which forms another input of the PWM generator 410. The PWM generator 410 generates a signal PWM-CLK on the path 417 based on the signals Vc1 and Isum. The signal PWM-CLK of path 417 may be a pulse train (eg, having a fixed pulse width), and its frequency may vary based on changes in Vin, Vout, and load current.

[0081] The signal PWM-CLK of path 417 is generally a short pulse of fixed duration, used to provide a clock signal for components (such as flip-flops) inside the phase distributor 420. Modules 405, 410, and 413 can be considered together as a "control block" that is configured to generate a "common control signal" PWM-CLK (path 417) so that the voltage Va on path 240 is maintained at a desired constant amplitude as indicated by Vref (path 401).

[0082] The PWM generator 410 may include a sawtooth wave generator, a comparator, etc. ( Figure 4A Components (not shown) for generating the signal PWM-CLK (path 417) are also well known in the relevant art. The PWM generator 410 can be implemented in a known manner.

[0083] The phase enable controller 415 receives (multiple) inputs representing the load current demand, the sensed inductor current of each power stage, the overshoot / undershoot of the voltage Va (path 240), etc. on path 412, and generates a phase enable signal (PH-EN) on paths 416-1 to 416-6. The phase enable controller 415 controls the addition or removal of phases (and corresponding power stages) based on the load current demand. In one embodiment, a logic high signal on path 416 means that the corresponding power stage is "enabled" to meet the load current demand, otherwise the corresponding power stage is "disabled". Therefore, if a logic high signal is received on path 416-2, the power stage SPSA-2220-2 will be enabled. The phase enable controller 415 can be implemented in a known manner.

[0084] Phase distributor (PD) 420 receives signal PWM-CLK on path 417, phase enable signal PH-EN-1 on path 416-1 to phase enable signal PH-EN-6 on path 416-6, and generates start-PWM signals START-PWM-1 (path 422-1) to START-PWM-6 (path 422-6) (also referred to as "timing signals"), which are input signals of each on-time generator 425. PD 420 sets corresponding signal 422 in response to each pulse (e.g., a transition type from a logic low level to a logic high level) of signal PWM-CLK (path 417). In an embodiment, PD 420 generates start-PWM signals (path 422) for enabled power stages (power stages whose corresponding PH-EN signals (path 416) are at a logic high level) in an around-robin fashion. Thus, for example, if power stages SPS-1A 220-1 through SPSA-5 220-5 are enabled for a period of time and SPSA-6 220-6 is disabled for that period of time, PD 420 asserts the signals on paths 422-1 through 422-5 in a cyclic manner in response to corresponding pulses of PWM-CLK (path 417) while keeping the signal on path 422-6 unasserted.

[0085] Each on-time generator 425 receives the corresponding "start PWM signal" on path 422 and generates a corresponding PWM signal on path 211 according to the setting of the corresponding "start PWM signal" on path 422, and the timing of the PWM signal is determined by the "start PWM signal". In this exemplary embodiment, the on-time generator 425 generates a PWM signal (path 211) with a predetermined (constant) on-time duration (logic high level duration) but whose frequency can be changed as described above. The predetermined (fixed) pulse width of each PWM signal (path 211) is independent of the pulse width of PWM-CLK (path 417) and the corresponding start PWM signal (path 422). Only the start (e.g., the transition edge from the logic low level to the logic high level) of the PWM signal (path 211) is triggered by the setting of the corresponding start PWM signal (path 422). The pulse width of each PWM signal (path 211) is set by the circuit inside the on-time generator 425. The on-time generator 425 can be implemented in a known manner.

[0086] Upon receiving the rising edge of each pulse of the signal PWM-CLK on the path 417, the PD 420 sets (changes to a logic high level) the corresponding enable PWM signal on the path 422. As described above, the PD 420 is configured to set the enable PWM signal on the path 422 in a cyclical sequence. Therefore, under normal (i.e., error-free) operation, only one enable PWM signal (path 422) is set for each rising edge of the signal PWM-CLK (on the path 417). In addition, under normal operation, only one enable PWM signal (path 422) is set and in an active / valid state within one cycle of the signal PWM-CLK on the path 417. In other words, more than one enable PWM signal (path 422) is set or active, or none of the enable PWM signals (path 422) is set, in any one cycle of the signal PWM-CLK on the path 417, indicating an error, which will be described in more detail below.

[0087] The signal PWM-CLK on path 417 can be derived / generated using analog components (such as components inside the error amplifier 405 and the PWM generator 410). Analog components are often prone to generating signals such as internal signals or output signals, which may deviate substantially from their ideal values ​​(at least in a short period of time) due to inherent thermal noise or external power / ground / substrate noise, as is well known in the relevant art. These deviations will propagate and appear as glitches (interference pulses) in the path 417 / signal PWM-CLK. A glitch generally refers to an unexpected transition of a signal to an incorrect logic level. Typically, the duration of a glitch is very short, or may be much shorter than the normal duration of the signal. The glitch on path 417 may cause errors in the generation of the start PWM signal 422, which in turn causes errors in the PWM signal (path 211), which will be described in detail below. Specifically, when a glitch in the signal PWM-CLK on path 417 is fed to the clock input of a flip-flop inside the phase distributor (PD 420), it may cause unpredictable behavior at the output (start PWM signal 422) of PD 420. For example, it may happen that some flip-flops in PD 420 are properly triggered by the glitch, while other flip-flops are not, as described below.

[0088] Next, the manner in which the start PWM signal (path 422) is generated from the signal PWM-CLK on path 417, and the error conditions and their correction methods are described. 6. Generation of timing signals

[0089] Figure 4B-Figure 4E It is used to illustrate an error condition in the timing signal (ie, the start PWM signal on path 422 ) and its correction method in an embodiment of the present disclosure. Figure 4B-Figure 4E 4 is a timing diagram (not drawn to scale) showing signal PWM-CLK on path 417 and the start PWM signal 422 generated by PD 420 . Figure 4B-Figure 4E 4 shows example waveforms of the signal PWM-CLK and the start-up PWM signals 422-1, 422-2, and 422-3 on the path 417 during steady-state operation. Figure 4B-Figure 4E In the example description, it is assumed that only SPSA-1 220-1, SPSA-2 220-2, and SPSA-3 220-3 ( Figure 2 ), and SPSA-4 220-4 to SPSA-6 220-6 are disabled. In addition, it should be noted that, although the frequency of the signal PWMA-CLK on the path 417 may change (for example, during load transients and step changes of the power supply Vin, etc.) as described above, for ease of explanation, the frequency of the signal PWMA-CLK on the path 417 is shown as constant in the embodiment.

[0090] Figure 4B is a timing diagram illustrating two types of error conditions occurring in timing signal 422 . Figure 4C It is shown Figure 4B Timing diagram of error conditions and their correction methods.

[0091] refer to Figure 4B , before time t436, it is assumed that the phase controller 210 is operating normally (without error), that is, there is no error in generating the start PWM signals 422-1 to 422-3. Therefore, before time t435, as expected, in any one cycle of the signal PWM-CLK of the path 417, only one of the signals start-PWM-1 (path 422-1), start-PWM-2 (path 422-2) and start-PWM-3 (path 422-3) is set (becomes a logic high level) and is in an effective state. Specifically, in response to the pulse of PWM-CLK (path 417) occurring at time t431, the signal start-PWM-1 (path 422-1) is set / asserted. In response to a pulse of PWM-CLK (path 417) occurring at time t433, signal start-PWM-2 (path 422-2) is asserted, and in response to a pulse of PWM-CLK (path 417) occurring at time t434, signal start-PWM-3 (path 422-3) is asserted. Time intervals t431-t433, t433-t434, t434-t435 illustrate three PWM cycles (i.e., cycles of signal PWM-CLK on path 417). At time t435, signal start-PWM-1 (422-1) is shown as being asserted again in response to a pulse of PWM-CLK (417).

[0092] Due to the presence of the glitch, the signal PWM-CLK on path 417 is narrower than it should be in normal conditions (shown in dashed lines) during the t436-t437 period. This glitch is shown as causing more than one signal 422 to become valid / active in response to the narrow PWM-CLK. This may occur when the currently active flip-flop in the phase distributor is not successfully triggered (provided with a clock signal) by the narrower PWM-CLK signal, while the next flip-flop in the phase distributor is successfully triggered by the narrower PWM-CLK signal. Therefore, the signals start-PWM-1 (path 422-1) and start-PWM-2 (path 422-2) are shown as being active during the interval t436-t437, which indicates an error condition.

[0093] Another glitch on the signal PWM-CLK on path 417 is shown as occurring at time t438. It is assumed that all previous errors have been corrected by t438. Due to the presence of the glitch, none of the enable PWM signals (path 422) are asserted / activated at time t438. This situation may occur when the currently active flip-flop in the phase distributor is successfully triggered (clocked, driven) by the glitch (interference pulse), while the next flip-flop in the phase distributor is not successfully triggered.

[0094] refer to Figure 4C , time interval t441-t445 corresponds to the normal operation state, while time intervals t441-t442, t442-t443, t443-t444 and t444-t445 show four PWM cycles. The error condition that two timing signals 422-1 and 422-2 are activated at time t445 is corrected at the beginning of the next PWM cycle, that is, only one timing signal 422-1 is activated at time t446.

[0095] Assuming that all previous errors have been corrected by time t447, the error condition where all timing signals are inactive at time t447 is shown to have been corrected at the beginning of the next PWM cycle, i.e., only one timing signal 422-1 is shown to be active at time t448.

[0096] Although the error condition is shown to be corrected in the next PWM cycle, in general, such correction can also be achieved in subsequent PWM cycles.

[0097] Figure 4D is a timing diagram illustrating two types of error conditions occurring in timing signal 422 under another scenario. Figure 4E It is shown Figure 4D Timing diagram of error conditions and their correction.

[0098] refer to Figure 4D , time period t451-t454 corresponds to normal (error-free) steady-state operation of the phase controller 210, wherein time intervals t451-t452, t452-t453, and t453-t454 illustrate three PWM cycles.

[0099] At time t454, in response to a pulse (specifically, an edge transition) of the signal PWM-CLK on path 417, the signal start-PWM-1 (path 422-1) is asserted. Due to a glitch pulse occurring at time t455, both the signal start-PWM-1 (path 422-1) and the signal start-PWM-2 (path 422-2) are asserted. Time t456 shows the time when the next PWM-CLK cycle occurs. The signals start-PWM-1 (path 422-1) and start-PWM-2 (path 422-2) are shown as being asserted in response to the PWM-CLK pulse at time t456.

[0100] Assume that all previous errors have been corrected by time t457. At time t457, in response to a pulse of signal PWM-CLK on path 417, signal start-PWM-1 (path 422-1) is asserted. A glitching pulse on signal PWM-CLK on path 417 is shown as occurring at time t458. Due to this glitching pulse, when the next PWM-CLK pulse (i.e., a normal pulse after time t457) occurs, i.e., at time t459, all start PWM signals (422) are not asserted.

[0101] refer to Figure 4E , intervals t461-t462, t462-t463, t463-t464 show three PWM cycles. The error caused by the interference pulse at time t465 is shown to have been corrected at the beginning of the next PWM cycle, that is, at time t466, only one timing signal 422-1 is activated, which is consistent with Figure 4D This is different from the case where both timing signals 422-1 and 422-2 are activated at time t456.

[0102] Assume that all previous errors have been corrected by time t467. The error condition caused by the interference pulse at time t468 is shown to have been corrected at the beginning of the next PWM cycle, that is, at time t469, a timing signal 422-1 is shown to be activated, which is consistent with Figure 4D This is different from the situation in which all timing signals are not activated at time t459.

[0103] In one embodiment of the present disclosure, the following description will be continued in conjunction with an exemplary implementation of a phase distributor implemented inside the phase controller 210 , where the phase distributor is used to handle such errors. 7. Phase splitter

[0104] Figure 54 is a diagram showing implementation details of a phase distributor in an embodiment of the present disclosure. The phase distributor 420 is shown to include annular units 520-1 to 520-6, correction units 550-1 to 550-6, and a detection module 560. The detection module 560 is further shown to include an inverter 575, an OR gate 580, and an AND gate 585. It should be noted that Figure 5 The embodiment of the phase distributor 420 shown in FIG is for illustration only. It should be understood that alternative implementations of the phase distributor 420 may include Figure 5 More or fewer modules as shown in the figure and different logic may be used.

[0105] Each ring unit 520 corresponds to a corresponding power stage 220 ( Figure 5 ). Therefore, Figure 5 Six annular units 520-1 to 520-6 are shown, each of which corresponds to a corresponding SPSA 220. Figure 2 . The ring unit 520 is shown as receiving the phase enable (PH-EN) signal on path 416, receiving the PWM-CLK signal on path 417, receiving the "use-corrected-data" signal on path 586, receiving the input signal i-from-prev-flop from the previous stage flip-flop on path 518, and receiving the MUX output (corrected data) on path 566. And the ring unit 520 is shown as generating the "phase enable" signal is-ph-enabled on path 524, generating the "phase activation" signal is-ph-active on path 526, generating the "to the next stage flip-flop" signal o-to-next-flop on path 523, and generating the start PWM (start-PWM) signal on path 422.

[0106] The ring unit 520 includes related circuits (which will be described below in conjunction with Figure 6 Detailed description), for checking whether the corresponding power stage is enabled / enabled (based on the signal received on path 416), and activating the corresponding power stage based on the input signal i-from-prev-flop received on path 518 and the PWM-CLK signal received on path 417. In one embodiment, when a logic high signal is received on path 518, the ring unit 520 generates a logic high signal on path 523 at the next rising edge of the signal PWM-CLK on path 417, otherwise (i.e., when a logic low signal is received on path 518), a logic low signal is generated. Figure 5It can be observed that the annular cells 520-1 to 520-6 are connected in an annular manner, so that the input signal on the path 518 of each annular cell 520 corresponds to the output signal 523 of the previous annular cell, wherein the first annular cell 520-1 receives the output signal on the path 523-6 of the last annular cell 520-6 (o-to-next-flop). It should be noted that in the present disclosure, the annular cell located immediately adjacent to / immediately next to the right of a "current" annular cell (i.e., the annular cell currently referred to) is referred to as the "next" annular cell, while the annular cell located immediately adjacent to / immediately next to the left of the current annular cell is referred to as the "previous" annular cell. Therefore, the annular cell 520-2 is the previous annular cell of the annular cell 520-3, and the annular cell 520-4 is the next annular cell of the annular cell 520-3. The annular cell 520-1 is the leftmost annular cell, and the annular cell 520-6 is the rightmost annular cell. A similar design is followed for the correction unit 550 .

[0107] Each correction unit 550 corresponds to a respective ring unit 520. The correction unit 550 is shown to receive the following signals: an is-ph-enabled signal on path 524, and an is-ph-active signal on path 526; and an i-more-than-1-ph-active signal on path 542, an i-atleast-1-ph-active signal on path 544, and an i-is-some-ph-enabled signal on path 546 from a previous correction unit; and o-more-than-1-ph-active signal on path 552-6 from correction unit 550-6.

[0108] The correction unit 550 is shown as generating a signal o-more-than-1-ph-active on a path 552, a signal o-atleast-1-ph-active on a path 554, a signal o-is-some-ph-enabled on a path 556, and correction data on a path 566. The correction units are shown connected sequentially so that the input signals 542, 544, and 546 correspond to the output signals 552, 554, and 556 of the previous correction unit, respectively. The input signals 542-1, 544-1, and 546-1 of the first correction unit 550-1 are shown as grounded (constant reference potential). The output of the correction unit 550 on the path 566 is shown as being provided to the corresponding ring unit 520. Therefore, the signal 566-1 of the correction unit 550-1 is shown as being provided to the ring unit 520-1.

[0109] For ease of understanding, the logic states of the following signals of the correction unit 550 in the exemplary embodiment are listed below: is-ph-enabled: A logic high level indicates that the corresponding SPS is enabled, while a logic low level indicates that the corresponding SPS is disabled; is-ph-active: logic high indicates that the Q output of the flip-flop of the corresponding ring cell is in the active state (logic high); o-more-than-1-ph-active: A logic high indicates that more than one flip-flop's Q output is active at a given time. In the following, this state of the signal is referred to as the "first error condition" (as in Figure 4D as in the case of the middle time interval t454-t456); o-atleast-1-ph-active: A logic low level indicates that the Q outputs of all flip-flops are not active at a given time. In the following, such a state of the signal is referred to as the "second error condition" (similar to Figure 4D at t459); and o-is-some-ph-enabled: Logic high indicates that at least one SPS is enabled.

[0110] The signal o-more-than-1-ph-active generated by correction unit 550 on path 552 is at a logic high level if one of the following conditions is true: 1. If the previous correction cell indicates that the Q output of more than one flip-flop is active (as indicated by a logic high level on the input signal i-more-than-1-ph-active on path 542); 2. If the Q output of at least one previous stage is in an active state (as indicated by a logic high level on path 544), and the Q output of the flip-flop in the ring unit corresponding to the current correction unit is also in an active state (as indicated by the signals on paths 524 and 526 being logic high levels).

[0111] The signal o-atleast-1-ph-active generated by correction unit 550 on path 554 is at a logic high level if one of the following conditions is true: 1. If the previous correction cell indicates that the Q output of at least one flip-flop is active (as indicated by the input signal i-atleast-1-ph-active on path 544 being at a logic high level); 2. The Q output of the flip-flop in the ring unit corresponding to the current correction unit is in the active state.

[0112] The signal o-is-some-ph-enabled generated by correction unit 550 on path 556 is at a logic high level if one of the following conditions is true: 1. If the previous correction unit indicates that at least one phase is enabled (as indicated by the input signal i-is-some-ph-enabled on path 546 being at a logic high level); 2. The SPS corresponding to the current calibration unit has been enabled.

[0113] Detection module 560 is shown as receiving signal o-more-than-1-ph-active on path 552 - 6 , signal o-atleast-1-ph-active on path 554 - 6 , and signal o-is-some-ph-enabled on path 556 - 6 , and generating signal use-corrected-data on path 586 .

[0114] The following further describes the implementation details of the ring unit in the embodiment of the present disclosure. 8. Ring unit

[0115] Figure 6 is a block diagram showing implementation details of a ring unit in an embodiment of the present disclosure. Figure 6 Annular unit 520-1 is shown in detail in FIG. Other annular units may also be implemented similar to annular unit 520-1. However, in other embodiments, annular units may have more or fewer modules than shown. Annular unit 520-1 is shown to include AND gates 610 and 625, multiplexers (MUX) 615 and 630, and a D flip-flop 620.

[0116] AND gate 610 receives signal PH-EN-1 on path 416-1, receives signal i-from-prev-flop on path 518, and generates an AND gate output on path 611. Therefore, when both signals PH-EN-1 and i-from-prev-flop are at logic high levels, the AND gate generates a logic high level.

[0117] MUX 615 receives the AND output on path 611, the correction data on path 566, and forwards one of the signals 611 and 566-1 on path 617 as an output (MUX output on path 617) based on the logic value of the selection signal 586 (use correction data). In one embodiment, when the signal "use correction data" on path 586 is at a logic high level, the signal 566-1 is selected as the MUX output on path 617, and when the signal "use correction data" on path 586 is at a logic low level, the AND gate output on path 611 is selected as the MUX output on path 617.

[0118] Flip-flop 620 receives the MUX output on path 617 at its D input and produces a Q output on path 526. Flip-flop 620 is triggered / clocked by the signal PWM-CLK on path 417. In an embodiment, flip-flop 620 is implemented as a positive edge triggered flip-flop with a low active clear (CLR) input. A glitch pulse in the signal PWM-CLK on path 417 may cause flip-flop 620 to exhibit state changes in an unpredictable manner because the glitch pulse may or may not trigger the flip-flop. Therefore, a glitch pulse in the signal PWM-CLK on path 417 may cause the first error condition or the second error condition.

[0119] AND gate 625 receives the signal PWM-CLK on path 417, the Q output on path 526, and generates an AND output on path 422. Figure 4A As shown, the AND output (start-PWM) on path 422 is provided to the corresponding on-time generator 425. Therefore, in the illustrative embodiment, the pulse width of the signal start-PWM on path 422 is (substantially) equal to the pulse width of the signal PWM-CLK on path 417. Although in the illustrative embodiment, the output of AND gate 625 is shown as being provided on path 422, in an alternative embodiment, the Q output of flip-flop 620 can be provided on path 422 as an input to the on-time generator 425. In such an alternative embodiment, once the signal on path 422 is asserted in response to the corresponding pulse of the signal PWM-CLK on path 417, it will remain in an asserted state until the end of the period, as will be apparent to those skilled in the art from the disclosure provided herein.

[0120] The multiplexer (MUX) 630 receives the Q output of the flip-flop 620 on the path 526 and receives the signal i-from-prev-flop on the path 518-1, and then forwards one of the path 526 and 518-1 signals on the path 523-1 as an output (MUX output / o-to-next-flop) based on the logic value of the selection signal (PH-EN-1) of the path 416-1. In an embodiment, when the signal PH-EN-1 on the path 416-1 is at a logic high level, the Q output of the path 526 is selected as the MUX output on the path 523-1, and when the signal PH-EN-1 on the path 416-1 is at a logic low level, the signal i-from-prev-flop on the path 518-1 is selected as the MUX output on the path 523-1. In other words, when the SPS corresponding to the ring cell 520 is not enabled, the input signal (path 518 ) indicating the activation state of the previous ring cell is forwarded on path 523 .

[0121] The output signals is-ph-enabled (path 524-1) and is-ph-active (path 526-1) indicate whether the SPSA 220 corresponding to the ring cell 520 is enabled and whether the Q output of the corresponding flip-flop is activated, respectively. In an embodiment, a logic high level on path 524-1 indicates that the SPSA-1 220-1 is enabled, while a logic low level on path 524-1 indicates that the SPSA-1 220-1 is disabled. A logic high level on path 526-1 indicates that the Q output of path 526-1 is valid (logic high level), while a logic low level on path 526-1 indicates that the Q output on 526-1 is a logic low level.

[0122] Thus, under normal operation (no errors in the PWM signal generation process), the ring cells 520-1 to 520-6 are used to shift the logic high level on the Q output of the flip-flop (thereby turning ON / activating the different phases, i.e., SPSA-1 220-1 to SPSA-6 220-6) in a cyclic sequence. At each transition from a low level to a high level of the signal PWM-CLK on the path 417, the position of the flip-flop 620 in the ring cell 520 of the phase distributor 420 that is in the active state is shifted one position to the right, or rolled back to the leftmost flip-flop position. Thus, under normal operation, at any time, there is one (and only one) flip-flop in the active state (its Q output is a logic high level), and the flip-flop in the active state corresponds to the active phase (SPS) at that time.

[0123] The following further describes the implementation details of the correction unit in the embodiment of the present disclosure. 9. Correction unit

[0124] Figure 7 5 is a block diagram showing details of the correction unit in the embodiment of the present disclosure. Figure 7 In addition to the input signals 542-1, 544-1 and 546-1 of the correction unit 550-1 being grounded (also as shown in FIG. Figure 5 In addition to the ones shown in FIG. 5 , other correction units may also be implemented similar to the ring unit 550-2. However, in other embodiments, the correction unit may have more or fewer modules than shown. The correction unit 550-2 is shown to include an AND gate 710, an AND gate 730, an AND gate 760, and an AND gate 770, an OR gate 720, an OR gate 740, and an OR gate 750, an inverter 755, an inverter 765, and a MUX 775.

[0125] AND gate 710 receives the signal is-ph-enabled on path 524-2 and the signal is-ph-active on path 526-2, and generates an AND output on path 711. OR gate 720 receives the AND output on path 711 and the signal i-atleast-1-ph-active on path 544-2, and generates an OR output on path 554-1. Therefore, OR gate 720 of correction unit 550 is used to determine whether the Q output of at least one flip-flop is valid (in the active state). The output signal o-atleast-1-ph-active of the last correction unit 550-6 presents a logic low level, which indicates that the Q outputs of all flip-flops are not in the active state at a given time.

[0126] AND gate 730 receives the output of AND gate 710 on path 711 and the signal i-atleast-1-ph-active on path 544-2, and generates an AND output on path 731. OR gate 740 receives the AND output on path 731 and the signal i-more-than-1-ph-active on path 542-2, and generates an OR output (o-more-than-1-ph-active) on path 552-2. Therefore, AND gate 730 and OR gate 740 of correction unit 550 are used together to determine whether the Q output of more than one flip-flop is in the active state at a given time. The logic high level of any one of output signals o-more-than-1-ph-active 552-1 to 552-6 indicates that the Q output of more than one flip-flop is in the active state at a given time.

[0127] OR gate 750 receives the signal i-is-some-ph-enabled on path 546-2 and the signal is-ph-enabled on path 524-2, and generates or outputs o-is-some-ph-enabled on path 556-2. Therefore, OR gate 750 of correction unit 550 is used to determine whether at least one SPS is enabled at a given time. The logic high level of any one of output signals 0-is-some-pH-enabled 556-1 to 556-6 indicates that at least one SPS is enabled at a given time.

[0128] AND gate 760 receives the inverted signal of input i-is-some-ph-enabled (path 546-2) and the signal is-ph-enabled on path 524-2 on path 757, and generates an AND output use-ph-if-lost on path 763-2. AND gate 770 receives the inverted signal of input i-at-least-1-ph-active (path 544-2) and the output of AND gate 710 on path 711 on path 767, and generates an AND output (use-ph-if-multi) on path 773-2.

[0129] MUX 775 is shown as receiving the signal use-ph-if-multi on path 773-2, receiving the signal use-ph-if-lost on path 763-2, and forwarding one of the signals on paths 773 and 763 as an output on path 566-2 based on the logic value of the select signal o-more-than-1-ph-active received on path 552-6. The signal o-more-than-1-ph-active on path 552-6 corresponds to the output of the last correction unit 550-6. When the signal o-more-than-1-ph-active on path 552-6 is a logic high level (indicating a first error condition), MUX 775 forwards the signal use-ph-if-multi on path 773 on path 566, otherwise forwards the corresponding signal use-ph-if-lost of path 763. The output of MUX 775 on path 566 is provided to the corresponding ring unit 520. Thus, signal 566-1 of MUX 775-1 is shown provided to ring unit 520-1.

[0130] Although the illustrative embodiments show a specific arrangement of logic gates for error detection and error correction in the phase distributor 420, alternative embodiments may include fewer or more modules with appropriate changes to the arrangement, as will be apparent to those skilled in the art by reading the disclosure provided herein. In addition, the transitions and logic states of the signals may be appropriately selected according to the design requirements of a particular environment, as will be apparent to those skilled in the art by reading the disclosure provided herein.

[0131] As described below, components 710, 720, 730, 740 and 750 of each correction unit 550 together enable detection of errors in the Q output of the ring unit of PD420, while components 755, 760, 765, 770 and 775 of correction unit 550 together with MUX 615 of the ring unit are used to correct the detected errors. 10. Identify error conditions

[0132] Figure 8 yes Figure 5 An example diagram of a phase divider, in which the internal details of the ring unit and the correction unit are additionally shown. For ease of understanding, Figure 8 Only the internal details of the ring units 520-1, 520-2 and 520-6 and the corresponding correction units 550-1, 550-2 and 550-6 are shown in FIG. In the following description, it is assumed that all six power stages 220 are enabled.

[0133] To facilitate understanding of the present disclosure, the following lists the logic states of various signals related to the present disclosure in normal operation and when an error occurs. Those skilled in the art can understand the logic states of other signals by reading the disclosure herein. Normal operation (no errors)

[0134] In normal operation, the Q outputs of paths 526-1 to 526-6 (Q outputs 526-1 to 526-6) have values ​​of a staggered sequence of logic high levels, where flip-flops 620-1 to 620-6 are triggered by the clock signals provided by the corresponding rising edges of signal PWM-CLK (path 417). The signal o-atleast-1-ph-active in each of paths 554-1 to 554-6 is a logic high level. The signal o-more-than-1-ph-active in each of paths 552-1 to 552-6 is a logic low level. The signal o-is-some-ph-enabled in each of paths 556-1 to 556-6 is a logic high level. Therefore, the inputs of OR gate 580 are all low levels, and correspondingly, the output of AND gate 585 on path 586 (using the correction data) is a logic low level. Therefore, each of the MUXs 615-1 to 615-6 of the ring unit 520 forwards the corresponding output of the AND gates 610-1 to 610-6. The MUXs 630-1 to 630-6 receive the logic high level on the corresponding paths 416-1 to 416-6. Therefore, the MUXs 630-1 to 630-6 forward the corresponding Q output of the flip-flop 620. The MUXs 775-1 to 775-6 receive the logic low level on the path 552-6 and forward the corresponding signals of the signals in the paths 773-1 to 773-6 on the paths 566-1 to 566-6. Error Condition 1 - More than one timing signal is asserted in response to the same pulse of PWM-CLK

[0135] Assume that when a glitch occurs on the signal PWM-CLK on path 417, the flip-flop currently in the active state is 620-1. Assume that the glitch causes (only) flip-flop 620-2 to be successfully triggered (providing the clock signal), so that the Q output of path 526-2 exhibits a logic high level. This occurs because the Q output of flip-flop 620-1 is already a logic high level, PH-EN-2 is also a logic high level, and MUX 615 has the logic value of the select signal of path 586, which forwards the logic high level output of AND gate 610-2 to the D input of flip-flop 620-2. It should be noted that if this error is not corrected, in response to a normal pulse of PWM-CLK (path 417) that occurs after the glitch, the switching power stages SPSA-1 220-1 and SPSA-2 220-2 will be activated simultaneously (via the corresponding start PWM signal 422 and PWM signal 211). It should also be noted that if this type of error is not corrected, the error condition will persist even if the glitch does not occur later, because each Q output at a logic high level will shift to the corresponding next flip-flop in the ring structure.

[0136] The logical states of the ring unit 520 and the correction unit 550 due to an error condition are described below:

[0137] For the correction unit 550-1:

[0138] The signal o-at-least-1-ph-active on path 554-1 is a logic high level (because the output of AND gate 710-1 is a logic high level). The signal o-more-than-1-ph-active on path 552-1 is a logic low level (because the output of AND gate 730-1 is a logic low level and the signal on path 542-1 is a logic low level). The signal 0-is-some-pH-enabled on path 556-1 is a logic high level (because the signal PH-EN-1 on path 416-1 is a logic high level).

[0139] For the correction unit 550-2:

[0140] The signal o-at-least-1-ph-active on path 554-2 is at a logic high level (because the signal 554-1 of the path is at a logic high level and the output of AND gate 710-2 is at a logic high level). The signal o-more-than-1-ph-active on path 552-2 is at a logic high level (because the output of AND gate 730-2 is at a logic high level). In other words, the current flip-flop 620-2 is in an active state (as indicated by the output of AND gate 710-2 presenting a logic high level), and the previous flip-flop 620-1 is also in an active state (as indicated by the signal i-at-least-1-ph-active on path 544-2).

[0141] For correction units 550-3, 550-4, 550-5, and 550-6:

[0142] Each of the input signals i-atleast-1-ph-active (path 544), i-more-than-1-ph-active (path 542), and i-is-some-ph-enabled (path 546) is a logic high level, and correspondingly each of the output signals o-atleast-1-ph-active (path 554), o-more-than-1-ph-active (path 552), and o-is-some-ph-enabled (path 556) is a logic high level.

[0143] Since the signal o-more-than-1-ph-active of path 552-6 and the signal o-is-some-ph-enabled of path 556-6 are logic high, the output of OR gate 580 is logic high, and accordingly the output of AND gate 585 is logic high (which indicates that an error condition has occurred in the signal). Therefore, the first error condition is detected.

[0144] Referring to the MUX 775-1 in the first correction unit 550-1, the selection signal o-more-than-1-ph-active of the path 552-6 is a logic high level. Therefore, the MUX 775-1 forwards the output of the AND gate 770-1 on the path 566-1, which is a logic high level. The selection signal (path 586) of the MUX 615-1 of the ring unit 520-1 is a logic high level, and accordingly, the MUX 615-1 forwards the signal of the path 566-1 as the D input to the flip-flop 620-1. When the next normal rising edge (referred to as the "first correction edge") of the signal PWM-CLK (path 417) that appears after the glitch arrives, the flip-flop 620-1 outputs a logic high level on the path 526-1. It can be understood that the Q output on the path 526-1 will continue to remain at a logic high level.

[0145] Referring to MUX 775-2 within the second correction unit 550-2, the select signal (o-more-than-1-ph-active) of path 552-6 is at a logic high level. Therefore, MUX 775-2 forwards the output of AND gate 770-2 on path 566-2. Since the signal i-atleast-1-ph-active of path 544-2 is at a logic high level, the inverting input to AND gate 770-2 (on path 767-2) is at a logic low level, so the output of AND gate 770-2 is at a logic low level. The select signal (path 586) of MUX 615-2 of the ring unit 520-2 is at a logic high level, so MUX 615-2 forwards the signal of path 566-2 as the D input to flip-flop 620-2. Therefore, at the first corrective edge of PWM-CLK (path 417), the Q output (path 526-2) of MUX 615-2, flip-flop 620-2, will transition from the previous logic high value to a logic low value. In other words, starting from the first corrective edge, only one flip-flop (and correspondingly only one start PWM signal / PWM signal / power level) is active in each cycle of PWM-CLK (path 417).

[0146] When the signal on path 526-2 goes low, the output of AND gate 710-2 (and therefore the output of AND gate 730-2) goes to a logic low level, so that the signal o-more-than-1-ph-active on path 552-2 also goes to a logic low level, which clears the error detection signal o-more-than-1-ph-active on path 552-6 (the transition from high to low level). Therefore, the signal on path 586 (using the correction data) transitions to a logic low level. Phase distributor 420 resumes normal operation from the occurrence of the first correction edge of PWM-CLK (path 417). Therefore, at the next normal rising edge of PWM-CLK (path 417) (after the first correction edge), SPSA-1 220-1 is turned off and SPSA-2 220-2 is turned on because the signal on path 526-1 (the Q output of flip-flop 620-1) transitions to a logic low level, while the signal on path 526-2 (the Q output of flip-flop 620-2) transitions to a logic high level.

[0147] Therefore, the phase distributor 420 drives the first trigger in the phase distributor 420 that maintains an activated state at a logic high level (620-1 in the example embodiment, corresponding to power level SPSA-1220-1, which is the first power level to be activated before the error that causes multiple power levels to be activated occurs) to maintain a high level, while the remaining triggers that maintain a logic high level (620-2 in the example embodiment, corresponding to power level SPSA-2 220-2) are turned to a logic low level.

[0148] Although for simplicity, the illustrative embodiments describe error handling when two triggers become activated at the same time, various aspects of the present disclosure are applicable when more than two triggers become activated at the same time, which will be apparent to those skilled in the art from reading the disclosure herein.

[0149] Therefore, phase distributor 420 detects and corrects the first error condition, that is, more than one timing signal is asserted during one period of the PWM clock. The description continues below to illustrate the detection and correction of the second error condition. Error condition 2 - No timing signal is asserted in response to the same pulse of PWM-CLK

[0150] Assume that when a glitch occurs on the signal PWM-CLK on the path 417, the trigger currently in the active state is 620-1. Assume that the glitch causes (only) the trigger 620-1 to be successfully triggered. In other words, the trigger 620-1 currently in the active state in the phase distributor 420 is successfully triggered by the glitch (achieving the clock triggering operation), but the next trigger 620-2 in the phase distributor is not successfully triggered. Due to the glitch, the Q output on the path 526-1 is converted from a logic high level to a logic low level. All other Q outputs continue to remain at a logic low level because the other triggers are not triggered by the glitch. Therefore, at a certain time corresponding to the normal rising edge of the signal PWM-CLK on the path 417, none of the start PWM signals (path 422) are set (such as Figure 4B It should be noted that if this error is not corrected, the error condition will persist even without further glitches, where all Q outputs will continue to remain at a logic low level because the logic low output of each ring cell is simply transferred to the next ring cell, so no power stage will be activated again.

[0151] The following describes the logic states of the ring unit 520 and the correction unit 550 in the second error situation:

[0152] For the correction unit 550-1:

[0153] The signal o-at-least-1-ph-active on path 554-1 is a logic low (because the output of AND gate 710-1 is a logic low, which is due to the signal of path 526-1 being a logic low, and the signal of path 544-1 is also a logic low). The signal o-more-than-1-ph-active on path 552-1 is a logic low (because the output of AND gate 730-1 is a logic low and the signal of path 542-1 is also a logic low). The signal 0-is-some-pH-enabled on path 556-1 is a logic high (because the signal PH-EN-1 on path 416-1 is a logic high).

[0154] For the correction unit 550-2:

[0155] The signal o-at-least-1-ph-active on path 554-2 is a logic low level (because the signal on path 554-1 is a logic low level, the output of AND gate 710-2 is a logic low level, which is because the Q output on path 526-2 has been maintained at a logic low level since the previous rising edge of PWM-CLK (path 417) before the glitch occurred). The signal o-more-than-1-ph-active on path 552-2 is a logic low level (because the output of AND gate 730-2 is a logic low level and the signal on path 542-2 is a logic low level). In other words, if no glitch occurs in the signal PWM-CLK (path 417), the flip-flop (e.g., 620-2) that should be currently active does not become active (as indicated by the logic low level on the Q output (path 526-2) of the flip-flop 620-2), and the previous flip-flop 620-1 has also become inactive (as indicated by the input signal i-at-least-1-ph-active on path 544-2).

[0156] For correction units 550-3, 550-4, 550-5, and 550-6:

[0157] Each of the input signals i-atleast-1-ph-active (path 544) and i-more-than-1-ph-active (path 542) is a logic low level, while the signal i-is-some-ph-enabled (path 546) is a logic high level. Accordingly, each of the output signals o-atleast-1-ph-active (path 554) and o-more-than-1-ph-active (path 552) is a logic low level, while the output signal o-is-some-ph-enabled (path 556) is a logic high level.

[0158] Since the signal o-atleast-1-ph-active of path 554-6 is at a logic low level, the output of OR gate 580 is at a logic high level. Accordingly, the output of AND gate 585 is at a logic high level (this is because the signal o-is-some-ph-enabled of path 556-6 is at a logic high level). Therefore, the second error condition is detected.

[0159] Referring to the MUX 775-1 within the first correction unit 550-1, the selection signal o-more-than-1-ph-active of the path 552-6 is a logic low level. Therefore, the MUX 566-1 will forward the output of the AND gate 760-1 on the path 566-1, which is a logic high level. The selection signal (path 586) of the MUX 615-1 of the ring unit 520-1 is a logic high level, so the MUX 615-1 forwards the signal of the path 566-1 as the D input to the flip-flop 620-1. After the glitch occurs, when the next normal rising edge (referred to as the "second correction edge") of the signal PWM-CLK (path 417) arrives, the flip-flop 620-1 outputs a logic high level on the path 526-1. It can be understood that the Q output of the path 526-1 is converted from a logic low level to a logic high level.

[0160] Referring to MUX 775-2 within the second correction cell 550-2, the select signal o-more-than-1-ph-active for path 552-6 is a logic low. Therefore, MUX 566-2 forwards the output of AND gate 760-2 on path 566-2. Since the signal i-is-some-ph-enabled for path 546-2 is a logic high, the inverting input to AND gate 760-2 (on path 757-2) is a logic low, so the output of AND gate 760-2 is a logic low. The select signal (path 586) of MUX 615-2 of ring cell 520-2 is a logic high, so MUX 615-2 forwards the signal of path 566-2 as the D input to flip-flop 620-2. Therefore, at the second correction edge of PWM-CLK (path 417), MUX 615-2, the Q output of flip-flop 526-2 remains at a logic low. In other words, at the second correction edge, only the flip-flop (620-1 in the example) in the first ring cell (from the left) whose corresponding input signal PH-EN 416 is in a logic high state is activated (thus only start-PWM-1 422-1 is set), thereby ensuring that only the Q output of one flip-flop is at a logic high level (and therefore only one power stage SPSA-1 220-1 is in an active state), thereby getting the PD 420 out of the error condition.

[0161] Therefore, in the alternative, assuming that only SPSA-2 220-2 and SPSA-3 220-3 are enabled and the other SPSs (i.e., SPSA-1 220-1 and SPSA-4 220-4 through SPSA-6 220-6) are disabled, if a glitch occurs when flip-flop 620-3 is activated, the correction operation will be to set the Q output of flip-flop 620-2 of ring cell 520-2 to a logic high level instead of setting the Q output of flip-flop 620-1 of ring cell 520-1 to a logic high level.

[0162] When the signal of path 526-1 goes high, the signal o-atleast-1-ph-active (path 554-1) also goes high, thereby clearing (transitioning from low to high) the error detection signal o-atleast-1-ph-active (path 554-6). Therefore, the signal on path 586 (using the correction data) transitions to a logic low level. The phase distributor 420 resumes normal operation starting from the second correction edge of the PWM-CLK (path 417). Therefore, at the next normal rising edge of the signal PWM-CLK (path 417) (located after the second correction edge), SPSA-1 220-1 is turned off and SPSA-2 220-2 is turned on because the signal on path 526-1 (the Q output of the flip-flop 620-1) transitions to a logic low level, while the signal on path 526-2 (the Q output of the flip-flop 620-2) transitions to a logic high level.

[0163] Therefore, the first error condition can cause more than one flip-flop to become active (Q output is logic high) due to a glitch. This may occur when the currently active flip-flop in the phase distributor is not successfully triggered (clocked) by the glitch, but the next flip-flop in the phase distributor is successfully triggered by the glitch. Correction of the first error condition requires that the first flip-flop that was active before the error occurs remain active, while deactivating all other flip-flops in the PWM-CLK cycle after the error detection. However, when the rightmost flip-flop in the ring structure (here 620-6) is the first flip-flop that was active before the error occurs (and the error causes the leftmost flip-flop 620-1 in the ring structure to become active), the correction operation requires that flip-flop 620-1 remain active, while all other flip-flops (including 620-6) become inactive.

[0164] In the second error condition, all flip-flops in phase distributor 420 become inactive (their Q outputs go low) due to the glitch. This may occur when the currently active flip-flop in phase distributor 420 is successfully triggered due to the glitch, but the next flip-flop in phase distributor 420 is not successfully triggered. Correction of the second error condition requires activating the leftmost enabled / enabled power stage while keeping all other power stages inactive.

[0165] Although the example embodiments show a particular manner for selecting a power stage to be activated as part of the correction, any enabled power stage may be activated as part of the correction by making appropriate modifications to the ring unit and / or correction unit circuits, as will be apparent to those skilled in the art upon reading the disclosure herein.

[0166] It will be appreciated that PD 420 can be scaled to detect and correct errors in any number of power stages by simply adding more ring cells and correction cells so that there is a pair of ring cells and correction cells for each power stage in a multi-phase switching converter.

[0167] Although the example embodiment describes that the error is corrected within a single cycle (i.e., when the next normal rising edge of the signal PWM-CLK (path 417) arrives after the glitch occurs), it will be understood that by appropriately modifying the circuit in the PD, the correction can also be arranged to be performed after two or more cycles of PWM-CLK (path 417).

[0168] although Figure 4A The example embodiment shown in shows constant on-time current mode control of the multi-phase switching converter 110, but aspects of the present disclosure may apply equally well when other types of control are employed. 11. Conclusion

[0169] In this specification, "one embodiment", "an embodiment", or similar expressions mentioned in various places mean that the specific features, structures, or characteristics described in association with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment", "in an embodiment", and similar expressions appearing in various places in this specification may (but not necessarily) all refer to the same embodiment.

[0170] exist Figure 1 , Figure 2 as well as Figure 4A-4E , Figure 5-Figure 8In the illustration, although each terminal / node is shown as being directly connected to (i.e., "connected to") multiple other different terminals, it should be understood that there may be other additional components in the connection path that are suitable for a particular environment, and therefore, these connections can be considered to be "electrically coupled / electrically connected" to the same terminals to which they are connected.

[0171] In this application, the power supply terminal and the ground terminal are referred to as constant reference potential.

[0172] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented only as examples and not limitations. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above embodiments, but should only be defined in accordance with the following claims and their equivalents.

Claims

1. A multi-phase switching converter, characterized in that: The multi-phase switching converter is used to provide a regulated power supply voltage from an input voltage, and the multi-phase switching converter includes: a plurality of power stages, each power stage being configured to receive a corresponding phase control signal and to connect the input voltage to a corresponding inductor when the corresponding phase control signal is in a first state and to disconnect the input voltage from the corresponding inductor when the corresponding phase control signal is in a second state; and A phase controller, used to generate the phase control signal, the phase controller comprising: a plurality of signal generators, each of which generates a corresponding phase control signal, wherein the phase control signal is timed to change to the first state according to the setting of the corresponding timing signal; and A phase distributor, for receiving a common control signal of a conversion type for indicating the time when each of the timing signals is valid, and for generating the timing signals, wherein the phase distributor detects a first error condition at a first time, the first error condition comprising more than one of the timing signals being in a valid state in the same cycle of the common control signal, and wherein the phase distributor performs a first corrective action to avoid the first error condition in a first future time period after the first time.

2. The multi-phase switching converter according to claim 1, characterized in that: The phase distributor detects a second error condition at a second moment, wherein the second error condition includes that at the moment when the common control signal undergoes the type of transition, none of the timing signals is in a valid state, wherein the phase distributor performs a second corrective action to avoid the occurrence of the second error condition in a second future time period after the second moment.

3. The multi-phase switching converter according to claim 2, characterized in that: The phase distributor comprises: a plurality of toroidal cells, wherein each toroidal cell corresponds to a respective power stage of the plurality of power stages, wherein each toroidal cell of the plurality of toroidal cells is configured to receive an input trigger signal, a phase enable signal, and generate an output trigger signal; wherein the plurality of annular units are connected in an annular manner such that the input trigger signal of each annular unit corresponds to the output trigger signal of the previous annular unit, wherein each annular unit comprises a trigger triggered by the common control signal, wherein during normal operation, in one cycle of the common control signal, the Q output of the trigger of only one annular unit is in a valid state; a plurality of correction units, wherein each correction unit of the plurality of correction units corresponds to a respective annular unit of the plurality of annular units; and A detection module, used to detect the first error condition and the second error condition; The detection module detects the following situation as the first error situation: in the same cycle, the Q outputs of more than one flip-flop are in the first logic state; The first corrective action includes: maintaining the Q output of the first flip-flop that maintains the first logic state immediately before the first error condition occurs in the first logic state during the first future period, and setting the Q outputs of other flip-flops that maintain the first logic state to a second logic state during the first future period; The detection module detects the following situation as the second error situation: at the moment when the conversion type occurs, the Q output of none of the multiple flip-flops is in the first logic state; The second corrective action comprises: setting the Q output of the flip-flop of only one ring cell to the first logic state within the second future time period, wherein the only one ring cell has the phase enable signal in the first logic state.

4. The multi-phase switching converter according to claim 3, characterized in that: The duration of the corresponding phase control signal in the first state is fixed, wherein the first future period starts from the occurrence of a moment of the transition type of the common control signal occurring after the first moment; wherein the second future period starts from the moment of the conversion type of the common control signal occurring after the second moment; Wherein, the first logic state is a logic high level, and the second logic state is a logic low level; The conversion type is from a logic low level to a logic high level.

5. The multi-phase switching converter according to claim 4, characterized in that: Each correction unit is configured to receive the phase activation signal of the corresponding ring unit, the phase enable signal, the first error detection input signal, the second error detection input signal and the third error detection input signal, and to generate a first error detection output signal, a second error detection output signal, a third error detection output signal, a first error correction signal and a second error correction signal; wherein the plurality of correction units are connected in a sequential manner such that the first error detection input signal, the second error detection input signal, and the third error detection input signal of a correction unit in the sequence of the plurality of correction units correspond to the first error detection output signal, the second error detection output signal, and the third error detection output signal of a previous correction unit in the sequence of the plurality of correction units, respectively; Wherein each of the first error detection input signal, the second error detection input signal and the third error detection input signal of a first correction unit in the sequence of the plurality of correction units is coupled to a constant reference potential.

6. The multi-phase switching converter according to claim 5, characterized in that: The phase distributor also includes: a plurality of correction data selection multiplexers, wherein each of the correction data selection multiplexers corresponds to a respective correction unit of the plurality of correction units; Wherein, the detection module includes: a first inverter configured to receive a second error detection output signal of a last correction unit in the sequence of the plurality of correction units; a first OR gate configured to receive the output of the first inverter, the first error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a first OR output signal; and a first AND gate configured to receive the first OR output signal and the third error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a correction selection signal; wherein each correction data selection multiplexer of the plurality of correction data selection multiplexers is configured to receive the corresponding first error correction signal and the second error correction signal of the corresponding correction unit as input, and receive the first error detection output signal of the last correction unit in the sequence of the plurality of correction units as a selection signal, wherein if the first error detection output signal of the last correction unit is a logic high level, the correction data selection multiplexer forwards the first error correction signal as the correction data signal, and if the first error detection output signal of the last correction unit is a logic low level, the correction data selection multiplexer forwards the second error correction signal as the correction data signal; The control block is further configured to receive a corresponding inductor current generated by each of the plurality of power stages, and the common control signal is also based on the corresponding inductor current.

7. The multi-phase switching converter according to claim 6, characterized in that: Each of the plurality of annular units comprises: a second AND gate configured to receive a corresponding phase enable signal and the input trigger signal and to generate a second AND output signal; a first multiplexer configured to receive the second AND output signal and the corresponding correction data signal of the corresponding correction data selection multiplexer as inputs and the correction selection signal as a selection signal, the first multiplexer forwarding the first error correction signal as a first multiplexer output if the correction selection signal is a logic high level, and the first multiplexer forwarding the second AND output signal as the first multiplexer output if the correction selection signal is a logic low level, wherein the flip-flop receives the first multiplexer output as a D input of the flip-flop; a second multiplexer configured to receive the Q output of the corresponding flip-flop and the input trigger signal as inputs and the phase enable signal as a selection signal, the second multiplexer forwarding the Q output as the output trigger signal if the phase enable signal is at a logic high level, and forwarding the input trigger signal as the output trigger signal if the phase enable signal is at a logic low level; and The third AND gate is configured to receive the Q output of the corresponding flip-flop and the common control signal as inputs, and to generate the timing signal.

8. The multi-phase switching converter according to claim 7, characterized in that: Each of the plurality of correction units comprises: a fourth AND gate configured to receive the phase enable signal and the phase activation signal and to generate a fourth AND output; a second OR gate configured to receive the fourth AND output and the second error detection input signal and to generate the second error detection output signal; a fifth AND gate configured to receive the fourth AND output and the second error detection input signal and to generate a fifth AND output; a third OR gate configured to receive the fifth AND output and the first error detection input signal, and to generate the first error detection output signal; a fourth OR gate configured to receive the third error detection input signal and the phase enable signal, and to generate the third error detection output signal; a second inverter configured to receive the third error detection input signal; a sixth AND gate configured to receive the output of the second inverter and the phase enable signal, and to generate the second error correction signal; a third inverter configured to receive the second error detection input signal; and A seventh AND gate is configured to receive the output of the third inverter and the fourth AND output, and to generate the first error correction signal.

9. A method for handling errors in a phase control signal generation process, characterized in that: The method is performed by a phase controller of a multi-phase switching converter, the multi-phase switching converter is used to provide a regulated power supply voltage from an input voltage, the phase controller is used to provide corresponding phase control signals to a plurality of power stages, each power stage is used to connect the input voltage to a corresponding inductor when a corresponding phase control signal in the plurality of phase control signals is changed to a first state, so that the plurality of power stages are used in cooperation to provide the regulated power supply voltage, the method comprising: generating a common control signal having a switching type for indicating a valid time instant of a plurality of timing signals; generating a corresponding timing signal among the plurality of timing signals for each power stage among the plurality of power stages, wherein the corresponding phase control signal is timed to transition to the first state according to the assertion of the corresponding timing signal; detecting a first error condition comprising more than one of the plurality of timing signals being in an active state at a time when the common control signal undergoes the type of transition; and A first corrective action is performed to avoid the first error condition within a first future period after the first error condition is detected.

10. The method according to claim 9, characterized in that The method comprises: detecting a second error condition comprising the absence of any one of said timing signals being in a valid state at the time when said transition type occurs in said common control signal; and A second corrective action is performed to avoid the second error condition within a second future period after the second error condition is detected.

11. The method according to claim 10, characterized in that The duration of the corresponding phase control signal in the first state is fixed, wherein the phase controller comprises: a plurality of signal generators, wherein each signal generator receives a corresponding timing signal of the plurality of timing signals and generates a corresponding phase control signal of the plurality of phase control signals; and A phase distributor receives the common control signal and generates the plurality of timing signals.

12. The method according to claim 11, characterized in that The phase distributor comprises: a plurality of toroidal cells, wherein each toroidal cell corresponds to a respective power stage of the plurality of power stages, wherein each toroidal cell of the plurality of toroidal cells is configured to receive an input trigger signal, a phase enable signal, and generate an output trigger signal; wherein the plurality of annular units are connected in an annular manner such that the input trigger signal of each annular unit corresponds to the output trigger signal of the previous annular unit, wherein each annular unit comprises a trigger triggered by the common control signal, wherein during normal operation, in one cycle of the common control signal, the Q output of the trigger of only one annular unit is in a valid state; a plurality of correction units, wherein each correction unit of the plurality of correction units corresponds to a respective annular unit of the plurality of annular units; and A detection module, used to detect the first error condition and the second error condition; The detection module detects the following situation as the first error situation: at the first moment, the Q outputs of more than one flip-flop are in the first logic state; The first corrective action includes: setting the Q output of a first flip-flop that maintains the first logic state immediately before the first error condition occurs to the first logic state within the first future period, and setting the Q output of other flip-flops that maintain the first logic state to a second logic state within the first future period; The detection module detects the following situation as the second error situation: at the second moment, the Q output of no trigger among the plurality of triggers is in the first logic state; The second correction action includes: in a second future time period, setting the Q output of the trigger included in the first ring unit in the cyclic sequence to a first logic state, and the phase enable signal of the first ring unit is in the first logic state.

13. The method according to claim 12, characterized in that The first future period starts from the time when the moment of the transition type of the common control signal occurring after the first moment occurs; wherein the second future period starts from the moment of the conversion type of the common control signal occurring after the second moment; Wherein, the first logic state is a logic high level, and the second logic state is a logic low level; The conversion type is from a logic low level to a logic high level.

14. The method according to claim 13, characterized in that Each correction unit is configured to receive the phase activation signal of the corresponding ring unit, the phase enable signal, the first error detection input signal, the second error detection input signal and the third error detection input signal, and to generate a first error detection output signal, a second error detection output signal, a third error detection output signal, a first error correction signal and a second error correction signal; wherein the plurality of correction units are connected in a sequential manner such that the first error detection input signal, the second error detection input signal, and the third error detection input signal of a correction unit in the sequence of the plurality of correction units correspond to the first error detection output signal, the second error detection output signal, and the third error detection output signal of a previous correction unit in the sequence of the plurality of correction units, respectively; Wherein each of the first error detection input signal, the second error detection input signal and the third error detection input signal of a first correction unit in the sequence of the plurality of correction units is coupled to a constant reference potential.

15. The method according to claim 14, characterized in that The phase distributor also includes: a plurality of correction data selection multiplexers, wherein each correction data selection multiplexer corresponds to a respective correction unit of the plurality of correction units; Wherein, the detection module includes: a first inverter configured to receive a second error detection output signal of a last correction unit in the sequence of the plurality of correction units; a first OR gate configured to receive the output of the first inverter, the first error detection output signal of the last correction unit in the sequence of the plurality of correction units, and to generate a first OR output signal; and a first AND gate configured to receive the first OR output signal and the third error detection output signal of the last correction unit in the sequence of the plurality of correction units and generate a correction selection signal; wherein each correction data selection multiplexer of the plurality of correction data selection multiplexers is configured to receive the corresponding first error correction signal and the second error correction signal of the corresponding correction unit as input, and receive the first error detection output signal of the last correction unit in the sequence of the plurality of correction units as a selection signal, wherein if the first error detection output signal of the last correction unit is a logic high level, the correction data selection multiplexer forwards the first error correction signal as the correction data signal, and if the first error detection output signal of the last correction unit is a logic low level, the correction data selection multiplexer forwards the second error correction signal as the correction data signal; The control block is further configured to receive a corresponding inductor current generated by each of the plurality of power stages, and the common control signal is also based on the corresponding inductor current.

16. A phase distributor, characterized in that: The phase distributor is applied to a phase controller of a multi-phase switching converter, the phase controller is used to provide corresponding phase control signals to multiple power stages of the multi-phase switching converter, each power stage is configured to connect a power supply to a corresponding inductor when the corresponding phase control signal is valid, so that the multiple power stages are used to cooperate to provide a regulated power supply voltage, the phase distributor includes: A plurality of ring units are arranged to be connected in a ring, wherein each ring unit corresponds to a corresponding power level among the plurality of power levels and comprises a trigger triggered by a common control signal generated by a control block of the phase controller, wherein during normal operation, the Q outputs of the respective triggers are sequentially set to be valid in a cyclic manner, thereby triggering the start of a corresponding phase control signal among the plurality of phase control signals, and during normal operation, in any one cycle of the common control signal, the Q output of the trigger of only one ring unit is set to be valid; a plurality of correction units, wherein each correction unit of the plurality of correction units corresponds to a corresponding annular unit of the plurality of annular units and is configured to receive a first set of signals from the corresponding annular unit, and each correction unit is configured to provide a corresponding correction signal to the corresponding annular unit when one or more error conditions occur in the plurality of annular units; and a detection module configured to receive a second set of signals from the plurality of correction units, the detection module being configured to detect the one or more error conditions based on the second set of signals, and generating an output signal coupled to each of the plurality of annular units upon detection of an error condition, the output signal being configured to cause each of the corresponding correction signals to perform a portion of a correction action in the corresponding annular unit.

17. The phase distributor according to claim 16, characterized in that: The one or more error conditions include a first error condition, wherein the first error condition is that: in the same cycle of the common control signal, the Q outputs of more than one flip-flop are valid; Among them, the multiple correction units generate the correction signal to keep the Q output of the trigger that was set valid immediately before the first error situation occurred valid in a future cycle after the same cycle, and to cancel the Q output of other triggers that were set valid.

18. The phase distributor according to claim 17, characterized in that: The future cycle is the next cycle after the same cycle.

19. The phase distributor according to claim 16, characterized in that: The one or more error conditions include a second error condition, wherein: within a same cycle of the common control signal, the Q output of none of the plurality of flip-flops is asserted; The plurality of correction units generate the correction signals so that in a future cycle after the same cycle, only the Q output of the trigger of one ring unit is set to be valid.

20. The phase distributor according to claim 19, characterized in that The future cycle is the next cycle after the same cycle.

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