Unconstrained relaxation digital-to-analog converter digital calibration method based on group least mean square algorithm

Abstract

The invention discloses an unconstrained relaxation digital-to-analog converter digital calibration method based on a group least mean square algorithm, and the method comprises the steps: initializing an SLMS algorithm parameter, and generating a random binary sequence ba with the length of n; 1 random binary sequences ba with the length of n are used for charging and discharging a calibration circuit of the Uc-ReDAC, output voltage # imgabs0 # is recorded, the error e (n) between 1 calibration voltage in the calibration circuit and the corresponding # imgabs1 # is calculated, the error mean value # imgabs2 # is calculated, and the current self-adaptive step length of the SLMS algorithm is calculated through the error mean value # imgabs3 #; updating the weight coefficient m by using the error mean value # imgabs4 # and the current adaptive step length; s2, judging whether the number of iterations is the maximum number of iterations, if not, updating the optimal weight coefficient Gm, and returning to the step S1, otherwise, outputting tau0; and generating a new binary coding set according to the output tau 0. According to the method, the actual clock constant of the RC network is found by using the SLMS algorithm, and the new binary coding set is generated based on the constant, so that the influence of the parasitic effect of the RC network on the Uc-ReDAC performance is effectively inhibited.

Description

Technical Field

[0001] The invention belongs to the field of digital-to-analog converters, relates to a digital calibration technology, and in particular to an unconstrained relaxation type digital-to-analog converter digital calibration method based on a group least mean square algorithm. Background Art

[0002] Digital Synthesis DAC (DS-DAC) is a new type of digital-to-analog conversion technology that uses digital synthesis to generate continuous analog signals. Unlike traditional digital-to-analog converters (DACs), digital synthesis DACs can directly generate complex analog signals without analog filters by converting discrete digital signals into high-quality analog waveforms. This technology has higher flexibility and accuracy and is widely used in high-performance signal generation, communication systems, audio processing, and precision measurement.

[0003] Generally, all-digital DAC is implemented by digital pulse width modulation and lowpass filter (LPF). Σ-Δ modulation can significantly improve the conversion accuracy of digital synthesis DAC. Relaxation DAC (ReDAC) consists of capacitors, resistors and small CMOS logic circuits. It has a simple structure and can work under low power supply voltage, solving the problem of high conversion time cost of all-digital DAC based on PWM.

[0004] Unconstrained Relaxation Digital-to-analog Converter (Uc-ReDAC), based on ReDAC, builds a new capacitor charging and discharging mathematical model, and solves the problem of the deviation between the ReDAC system clock cycle and the ideal clock cycle through a swarm intelligence optimization algorithm. However, the Uc-ReDAC RC network is affected by parasitic effects, resulting in the actual clock constant being greater than the ideal clock constant. Summary of the invention

[0005] Purpose of the invention: In order to overcome the deficiencies in the prior art, a digital calibration method for an unconstrained relaxation type DAC based on a group least mean square algorithm is provided. The SLMS algorithm is used to find the actual clock constant of the RC network, and a new binary code set is generated based on this constant, which effectively suppresses the influence of the parasitic effect of the RC network on the performance of Uc-ReDAC.

[0006] Technical solution: To achieve the above purpose, the present invention provides an unconstrained relaxation type digital-to-analog converter digital calibration method based on a group least mean square algorithm, comprising the following steps:

[0007] S1: Initialize SLMS algorithm parameters and generate a random binary sequence b of length n a ;

[0008] S2: Using l random binary sequences b of length n a Charge and discharge the calibration circuit of Uc-ReDAC and record the output voltage V Ca,n ;

[0009] S3: Calculate the n calibration voltages and the corresponding The error e(n) and calculate the mean error

[0010] S4: Using the mean error Calculate the current adaptive step size of the SLMS algorithm;

[0011] S5: Using the mean error And the current adaptive step size update weight coefficient m;

[0012] S6: Determine whether the number of iterations is the maximum number of iterations. If not, update the optimal weight coefficient Gm and return to step S1. Otherwise, output τ 0 ;

[0013] S7: According to the output τ 0 Generates a new binary encoding set.

[0014] Furthermore, the SLMS algorithm parameters initialized in step S1 include the number of binary sequences l, n, T, τ, V DD , weight coefficient m, step size u and maximum number of iterations (max).

[0015] Furthermore, the mathematical model of Uc-ReDAC in step S2 is:

[0016]

[0017] Among them, V C,n Represents the voltage value across the capacitor at nT, V C,0 Represents the initial voltage value of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the clock period of the system, τ=RC represents the ideal time constant, n represents the length of the binary sequence, b i represents the i-th term of the binary sequence, and σ represents the exponential decay factor of the RC network.

[0018] Furthermore, the calibration voltage calculation formula in step S3 is:

[0019]

[0020] Among them, p(n) is interference noise with a mean value of 0, which is used to simulate the voltage error caused by other factors in the circuit, such as clock jitter, power supply noise, etc.

[0021] Furthermore, the calibration voltage in step S3 corresponds to The error e(n) is calculated as:

[0022]

[0023] Furthermore, the calculation of the current adaptive step size of the SLMS algorithm in step S4 includes: in order to take into account the convergence speed and steady-state error of the SLMS algorithm, the present invention sets appropriate parameters in the capacitor charging function based on the charging characteristics of the capacitor so that its function change curve meets the requirements of the variable step size LMS algorithm; the capacitor charging function is

[0024]

[0025] Where q(t) is the voltage of the capacitor at time t, Q max It is the steady-state voltage after the capacitor is fully charged;

[0026] Based on the capacitor charging function, take the absolute value of the independent variable, add parameters a, b, c, and establish the relationship between step size and error

[0027]

[0028] Among them, u(n) is the step size of the adaptive step size LMS algorithm; by adjusting the values ​​of parameters a, b and c, the amplitude and change trend of the step size function are changed to apply to different adaptive filtering systems.

[0029] Furthermore, due to the presence of other interferences p(n) such as clock jitter and power supply noise in the circuit, when using the existing LMS algorithm to iterate m, even if mτ and τ 0 There is a certain gap between the values ​​of y and p(n). n The value may be very close to The LMS algorithm will determine mτ at this time as the actual clock constant. If only a binary sequence is used to charge and discharge the RC circuit to update m, there is a large chance that the solved τ 0 Therefore, the present invention proposes a swarm least mean square (SLMS) algorithm to charge and discharge the RC circuit using multiple binary sequences and use the average error to update m.

[0030] In step S5, the optimal iteration direction selection strategy is designed for the SLMS algorithm, and the weight coefficient m update formula is determined according to the functional relationship between the Uc-ReDAC output voltage and the RC network exponential decay factor to ensure that the algorithm can find the actual clock constant.

[0031] Furthermore, for different binary sequences, V c,n The exponential decay factor σ of the RC network in formula (1) will show different functional relationships, and different functional relationships have different effects on the iteration of the m value. c,n In the interval [σ,σ 0 ] increases gradually, resulting in mτ being unable to approach τ 0 ;

[0032] In view of the above situation, the optimal iteration direction selection strategy in step S5 is specifically: design a method based on the average value of the first iteration error The method for determining the optimal iteration direction is as follows: 0 ] is a small range, so The relationship between V c,n In the interval [σ,σ 0 ] is increasing or decreasing; by judging Whether the value of is less than 0, determine the update formula of m and find the correct iteration direction; if m is less than 0, change the update formula of m; otherwise, keep the update formula of m unchanged.

[0033] Furthermore, the updating formula of the weight coefficient m in step S5 is:

[0034]

[0035] in, is the average of multiple errors, is the average error at the first iteration.

[0036] Furthermore, the initial value of Gm in step S6 is When the current error When it is less than Gm, update Gm to the current error Otherwise, keep the Gm value unchanged;

[0037] When the number of iterations reaches the maximum number of iterations

[0038] τ 0 =Gm×τ (7)

[0039] Furthermore, in step S7, according to the output τ 0 Generate a new binary code set, the objective function is

[0040]

[0041] Uc-ReDAC uses the adaptive probabilistic binary particle swarm optimization (AP-BPSO) algorithm to optimize the target voltage and obtain the binary sequence b k , due to b k is obtained under the ideal clock constant, while the time constant τ of the actual RC network 0 >τ. Therefore, using b k Charging and discharging the actual RC circuit will result in unsatisfactory integral and differential nonlinearity of Uc-ReDAC.

[0042] In view of the above situation, the method of the present invention includes designing a variable step function based on the capacitor charging characteristics of the RC network, and adjusting the values ​​of the parameters in the variable step function in combination with the Uc-ReDAC system, effectively taking into account the convergence speed and steady-state error of the algorithm; proposing an SLMS algorithm to update the weight coefficient m of the Uc-ReDAC system to avoid the contingency that the algorithm judges an undesirable clock constant as an actual clock constant due to the influence of other noises in the circuit; designing an optimal iteration direction selection strategy, and determining the weight coefficient m update formula according to the functional relationship between the Uc-ReDAC output voltage and the RC network exponential attenuation factor to ensure that the algorithm can find the actual clock constant.

[0043] In the present invention, firstly, a variable step-size least mean square (LMS) algorithm is designed, and then a swarm least mean square (SLMS) algorithm is proposed to update the weight coefficient m of the Uc-ReDAC system; then, the optimal iteration direction selection strategy is designed according to the functional relationship between the Uc-ReDAC output voltage and the exponential decay factor of the RC network; finally, a variable step-size function is designed based on the capacitor charging characteristics of the RC network, and the values ​​of the parameters in the variable step-size function are adjusted in combination with the Uc-ReDAC system, so as to effectively balance the convergence speed and steady-state error of the algorithm.

[0044] Parasitic effects can cause the actual clock constant in the RC network to be greater than the ideal clock constant. The existing code set is generated under the ideal clock constant, and there will be errors when the RC network is charged using the original code set. The solution of the present invention is mainly to find the actual clock constant in the RC network and generate a new code set. The new code set is generated under the actual clock constant, so it is not affected by parasitic effects.

[0045] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0046] 1. The present invention proposes a variable step-size LMS algorithm based on the RC network capacitor charging characteristics, and combines the Uc-ReDAC system to adjust the values ​​of the parameters in the variable step-size function, which can effectively take into account the convergence speed and steady-state error of the algorithm, and provides the basic conditions for the Uc-ReDAC digital calibration method provided by the present invention.

[0047] 2. The present invention proposes an adaptive step-size SLMS algorithm, which uses the average error instead of the single error to update the weight coefficient, and designs a mechanism to determine the weight coefficient update direction, which is determined according to the functional relationship between the output voltage and the exponential decay factor of the RC network. This algorithm can effectively find the actual clock constant in the Uc-ReDAC RC network.

[0048] 3. The present invention proposes an unconstrained relaxation digital-to-analog converter digital calibration method based on the least mean square algorithm. The method finds the actual clock constant in the RC network through the SLMS algorithm and generates a new binary code set based on this constant. This method effectively suppresses the influence of the RC network parasitic effect on the performance of Uc-ReDAC, and the calibrated Uc-ReDAC has better static parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 The schematic diagram of the Uc-ReDAC digital calibration method provided by the present invention;

[0050] Figure 2 A structural diagram of Uc-ReDAC provided in this embodiment;

[0051] Figure 3 The step size and error and the number of iterations and error curves when the parameter a changes in the embodiment;

[0052] Figure 4 The step size and error and the number of iterations and error curves when the parameter b changes in the embodiment;

[0053] Figure 5 The step size and error and the number of iterations and error curves when the parameter c changes in the embodiment;

[0054] Figure 6 V c,n The relationship curve between σ and

[0055] Figure 7 A flow chart of calibrating Uc-ReDAC using the SLMS algorithm provided in an embodiment of the present invention;

[0056] Figure 8 This is a performance comparison chart of each algorithm when the interference noise variance is 0.0001;

[0057] Fig. 9This is a performance comparison chart of each algorithm when the interference noise variance is 0.04;

[0058] Fig.10 FIG. 4 is a static parameter diagram of Uc-ReDAC calibrated according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0060] This embodiment provides an unconstrained relaxation type digital-to-analog converter digital calibration method based on a group least mean square algorithm, such as Figure 1 As shown, it includes the following steps:

[0061] S1: Initialize SLMS algorithm parameters and generate a random binary sequence b of length n a ;

[0062] Initialize the SLMS algorithm parameters including the number of binary sequences l, n, T, τ, V DD , the values ​​of weight coefficient m, step size u and maximum number of iterations (max);

[0063] S2: Use l (l = 4) random binary sequences b with length n = 80 a Charge and discharge the calibration circuit of Uc-ReDAC and record the output voltage

[0064] The mathematical model of Uc-ReDAC is:

[0065]

[0066] Among them, V C,n Represents the voltage value across the capacitor at nT, V C,0 Represents the initial voltage value of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the clock period of the system, τ=RC represents the ideal time constant, n represents the length of the binary sequence, b i represents the i-th term of the binary sequence, and σ represents the exponential decay factor of the RC network.

[0067] Reference Figure 2As shown in the structure, the essence of Uc-ReDAC is to use binary coding and three-state buffers to charge and discharge the capacitor. The binary sequence is generated by the optimization algorithm on the PC side and transmitted to the ROM of the FPGA. The FPGA addresses the ROM according to the specified voltage, and sends the corresponding binary code to the three-state buffer to output the specified voltage at both ends of the capacitor.

[0068] In this embodiment, R = 1kΩ, C = 100pF, V DD =3.3V, T=10ns, l=4, the mean of p(n) is 0, the variance is 0.001, and the initial value of m is 1.

[0069] S3: Calculate the 4 calibration voltages in the calibration circuit and the corresponding The error e(n) and calculate the mean error

[0070] The calibration voltage calculation formula is:

[0071]

[0072] Among them, p(n) is interference noise with a mean value of 0, which is used to simulate the voltage error caused by other factors in the circuit, such as clock jitter, power supply noise, etc.

[0073] Calibration voltage and corresponding The error e(n) is calculated as:

[0074]

[0075] S4: Using the mean of 4 errors Calculate the current adaptive step size of the SLMS algorithm;

[0076] The calculation of the current adaptive step size of the SLMS algorithm includes: in order to take into account the convergence speed and steady-state error of the SLMS algorithm, the present invention sets appropriate parameters in the capacitor charging function based on the charging characteristics of the capacitor so that its function change curve meets the requirements of the variable step size LMS algorithm; the capacitor charging function is

[0077]

[0078] Where q(t) is the voltage of the capacitor at time t, Q max It is the steady-state voltage after the capacitor is fully charged;

[0079] Based on the capacitor charging function, take the absolute value of the independent variable, add parameters a, b, c, and establish the relationship between step size and error

[0080]

[0081] Where u(n) is the step size of the adaptive step size LMS algorithm; the error e(n) is the average of the four errors By adjusting the values ​​of parameters a, b and c, the amplitude and variation trend of the step function are changed to be suitable for different adaptive filtering systems;

[0082] In this embodiment, in order to clarify the influence of parameters a, b and c in the step function on the convergence, stability and anti-interference ability of the algorithm in the Uc-ReDAC system, the influence of the value of each parameter on the performance of the algorithm is discussed respectively, so as to select the optimal parameters. The simulation software uses Matlab2016, the number of sampling points is set to 100, 200 simulation experiments are carried out, and the average value is statistically calculated to draw the learning curve.

[0083] Figure 3 The following is a graph showing the relationship between the step size and error when b=0.1, c=0.1, and a is 0.06, 0.1, 0.3, and 0.6, as well as the number of iterations n and the error e(n). Figure 3 From (a) in the figure, we can see that when the value of a is too small, the step size is always small and the algorithm converges slowly. Figure 3 In (b), when a is large, the step size is large in the late convergence period, resulting in an increase in the steady-state error. When a is 0.6, although the convergence speed is fast, the steady-state error is large. When a is 0.06, the convergence speed is slower than when a is 0.1 and 0.3. When a is 0.3, the convergence speed is faster, but its steady-state error increases compared to a=0.1. After comprehensive consideration, a=0.25 is finally selected.

[0084] Figure 4 The following is a graph showing the relationship between the step size and error and the number of iterations n and the error when parameter b changes when a=0.25 and c=0.1. b is 0.05, 0.1, 0.2, and 0.3 respectively. Figure 4 From (a), we can see that when the error is the same, the larger the value of b, the faster the algorithm converges. However, the increase in the algorithm convergence speed comes at the expense of stability. Therefore, the value of b also needs to be referenced. Figure 4 In (b), when b is 0.05, the algorithm converges slowly. When b is 0.3, although the convergence speed is fast, the steady-state error is large and unstable. When b is 0.1 or 0.2, the algorithm converges quickly, and the steady-state error is smaller when b=0.1. Therefore, b=0.1 is finally selected.

[0085] The relationship between step size and error and the number of iterations n and error when a=0.25, b=0.1, c=0.01, 0.05, 0.1, 0.2 respectively is shown in the figure below. Figure 5 As shown by Figure 5From (a), we can see that the larger the value of c, the smaller the step size of the algorithm in the initial stage, resulting in slow convergence of the system. The smaller the value of c, the larger the step size when the algorithm error is small, resulting in a large steady-state error after the system converges. Figure 5 From (b), we can see that when c is 0.01 and 0.05, the steady-state error is large after the algorithm converges. When c is 0.2, the algorithm converges slowly, but the steady-state error is minimal. When c is 0.1, the algorithm has a faster convergence speed, but the steady-state error is slightly larger than c = 0.2. After comprehensive consideration, c = 0.13 is selected.

[0086] S5: Using the mean error And the current adaptive step size update weight coefficient m;

[0087] Due to the existence of other interferences p(n) such as clock jitter and power supply noise in the circuit, when using the existing LMS algorithm to iterate m, even if mτ and τ 0 There is a certain gap between the values ​​of y and p(n). n The value may be very close to The LMS algorithm will determine mτ at this time as the actual clock constant. If only a binary sequence is used to charge and discharge the RC circuit to update m, there is a large chance that the solved τ 0 Therefore, the present invention proposes a swarm least mean square (SLMS) algorithm to charge and discharge the RC circuit using multiple binary sequences and use the average error to update m.

[0088] An optimal iteration direction selection strategy is designed for the SLMS algorithm, and the weight coefficient m update formula is determined according to the functional relationship between the Uc-ReDAC output voltage and the exponential decay factor of the RC network to ensure that the algorithm can find the actual clock constant.

[0089] For different binary sequences, V c,n The exponential decay factor σ of the RC network in formula (1) will show different functional relationships, and different functional relationships have different effects on the iteration of the m value. c,n In the interval [σ,σ 0 ] increases gradually, resulting in mτ being unable to approach τ 0 ;

[0090] In view of the above situation, the optimal iteration direction selection strategy is as follows: design based on the average value of the first iteration error The method for determining the optimal iteration direction is as follows: 0 ] is a small range, so The relationship between V c,n In the interval [σ,σ0 ] is increasing or decreasing; by judging Whether the value of is less than 0, determine the update formula of m, and then find the correct iteration direction; if m is less than 0, change the update formula of m; otherwise, keep the update formula of m unchanged;

[0091] The update formula of the weight coefficient m is:

[0092]

[0093] in, is the average of multiple errors, is the average error at the first iteration;

[0094] In this embodiment, the Uc-ReDAC is implemented with σ=0.905. In equation (1), let V DD =1, V c,n The relationship curve with σ function is as follows Figure 6 shown. Figure 6 In (a), V c,n In the interval [σ,σ 0 ] decreases gradually, the error e(n) has a greater probability of being less than 0, the updated m<1, mτ becomes smaller, and after multiple iterations, mτ gradually deviates from τ 0 . Figure 6 In (b), V c,n In the interval [σ,σ 0 ] increases gradually, the error e(n) has a greater probability of being greater than 0, the updated m>1, mτ becomes larger, and by setting a suitable step size, after multiple iterations, mτ will continue to approach τ 0 .

[0095] S6: Figure 7 As shown in Figure 1, the specific process of the SLMS algorithm is as follows: first, initialize m, step size, number of binary sequences, binary sequence dimension, and maximum number of iterations; then, use the generated binary sequence to calculate the initial error between the actual voltage and the calibration voltage. according to The sign of determines the update formula of m; secondly, using the updated m, recalculate the error Then, the step size is updated using the proposed variable step size strategy, and m is updated using the current step size value until the maximum number of iterations is reached; finally, τ is calculated based on the best m found. 0 .

[0096] In this step, it is determined whether the number of iterations is the maximum number of iterations. If not, the optimal weight coefficient Gm is updated and the process returns to step S1. Otherwise, the output τ 0 ;

[0097] The initial value of Gm is When the current error When it is less than Gm, update Gm to the current error Otherwise, keep the Gm value unchanged;

[0098] When the number of iterations reaches the maximum number of iterations

[0099] τ 0 =Gm×τ (7)

[0100] S7: According to the output τ 0 Generate a new binary code set, the objective function is

[0101]

[0102] In order to verify the effectiveness and effect of the solution of the present invention, this embodiment is verified by experiments, as follows:

[0103] The experimental computer is an Intel(R) Core(TM) i3-10105 processor with a main frequency of 3.7GHz, the operating system is Windows 11, and the programming environment is Matlab 2016.

[0104] In order to verify the effectiveness of the variable step size strategy based on the RC network capacitor charging function proposed in this invention, the adaptive filter is a second-order linear filter, and the initial weight of the filter of the unknown system is w=[0.8 0.5] T , at the 500th sampling point, it becomes w=[0.4 0.2] T , the input signal X(n) of the adaptive filter is a Gaussian white noise with a mean of 0 and a variance of 1, and the interference noise v(n) is a Gaussian white noise with a mean of 0 and a variance of 0.0001; the input signal and the interference noise are uncorrelated. Let the number of sampling points be 1000, do 200 simulation experiments, and compare the performance of each algorithm. When the variance of the interference noise is 0.0001, the optimal parameters of each algorithm are shown in Table 1, and the comparative learning curves of each algorithm are shown in Figure 8 shown.

[0105] Table 1 Selection of algorithm parameters when the interference noise variance is 0.0001

[0106]

[0107] Algorithm 1 The step size update formula is:

[0108]

[0109] The step length update formula of Algorithm 2 is:

[0110]

[0111] The step length update formula of Algorithm 3 is:

[0112]

[0113] The step length update formula of Algorithm 4 is:

[0114]

[0115] Depend on Figure 8 It can be seen that the algorithm of the present invention reaches convergence after about 25 iterations, and the steady-state error after convergence is close to 0.000011. Compared with Algorithm 1, Algorithm 2 and Algorithm 3, which almost reach a steady-state error of 0.01 after about 300 iterations, the algorithm of the present invention has a faster convergence speed and better steady-state error. The steady-state error of Algorithm 4 is consistent with that of this paper and is close to 0.000011, but its convergence speed is slightly slower than that of the algorithm of this paper.

[0116] The noise is set to Gaussian white noise with a variance of 0.04 and a mean of 0. At this time, the optimal parameter selection of each algorithm is shown in Table 2, and the learning curve is shown in Fig. 9 shown.

[0117] Table 2 Selection of algorithm parameters when the interference noise variance is 0.04

[0118]

[0119] observe Fig. 9 It can be seen that after reaching convergence, the steady-state error results of the algorithm of the present invention and other algorithms are basically similar, almost all around 0.045; but the convergence speed of the algorithm of the present invention is the fastest. Compared with Algorithm 1, Algorithm 2 and Algorithm 3, which reach convergence in about 26 iterations, the algorithm proposed by the present invention has reached stable convergence in about 16 iterations.

[0120] In order to verify the effectiveness of the adaptive step-size group filtering algorithm proposed in this paper in the Uc-ReDAC system, the clock constant increment τ is calculated using the algorithm proposed in this paper, the large step-size LMS algorithm, and the small step-size LMS algorithm. 1 Calibrate the Uc-ReDAC for 1.2, 3.6 and 5.8. Perform five experiments in succession and record the τ of each experiment. 0 And calculate the average.

[0121] Table 3 τ 1 =1.2 The calibration results of each algorithm

[0122]

[0123] Table 3 shows τ 1 =1.2, the actual clock constant in the circuit is 101.2.0 They are 101.25, 101.18, 101.20, 101.22 and 101.18 respectively. The difference between them and 101.2 is no more than 0.05 and there are three times that they are τ solved by three algorithms. 0 The best value in the five experiments. 0 The average value is 101.21, which is the best among the three algorithms. The step size of the small step size LMS algorithm is set to 0.003. is 101.21, which is consistent with the algorithm in this paper. However, the τ solved in the first and second experiments is 0 The values ​​are 101.07 and 101.32 respectively, which are 0.13 and 0.12 different from the actual clock constant. The step size of the large-step LMS algorithm is set to 0.01, and the solved τ 0 The average value is 101.17. The τ solved in the second and third experiments 0 The difference from the actual clock constant is as large as 0.22.

[0124] Table 4 τ 1 =3.6Calibration results of each algorithm

[0125]

[0126]

[0127] Table 4 shows τ 1 =3.6, that is, the clock constant in the actual circuit is 103.6, the calibration results of the three algorithms. 0 They are 103.58, 103.47, 103.58, 103.59 and 103.57 respectively. is 103.56. Except for the second experiment, the τ solved by the algorithm of the present invention is 0 The difference with 103.6 is the smallest among the three algorithms. The LMS algorithm with a small step size solves τ in the first four experiments. 0 The values ​​of τ obtained by the LMS algorithm with a large step size in the second and fifth experiments are 102.07, 103.28, 102.92 and 101.76, which are not ideal. 0 is the best among the three algorithms, but the τ solved in the first experiment is 0 It is 104.23, which is quite different from 103.6.

[0128] Table 5 τ 1 =5.8 when the calibration results of each algorithm

[0129]

[0130] Table 5 shows the clock constant increment τ of the three algorithms. 1 =5.8, the calibration results of the three algorithms. The τ solved by the small step size LMS algorithm in the fifth experiment 0 The difference between 103.94 and the actual clock constant 105.8 is too large, which is 1.86. The LMS algorithm with a large step size solves τ in the first and fifth experiments. 0 The differences between 105.2 and 105.29 and 105.8 are 0.6 and 0.51 respectively, which fails to effectively solve the influence of parasitic effects. 0 The maximum difference from the actual clock constant is 0.04, and four experimental results are the best among the three algorithms.

[0131] For three different degrees of parasitic effects, whether the LMS algorithm with a large step length or the LMS algorithm with a small step length uses the error to update m, it will always be affected by p(n), resulting in the final solution of τ 0 There is a large deviation from the actual clock constant of the circuit. The algorithm in this paper updates m by using the SLMS algorithm to avoid the contingency caused by the influence of p(n) when using a single error to update m.

[0132] When τ 1 = 1.2, the τ obtained by the small step LMS solution 0 The maximum and minimum values ​​are 101.32 and 101.07 respectively. The τ obtained by LMS with a large step size is 0 The maximum value is 101.42 and the minimum value is 100.98. It can be seen that when the clock constant increment caused by parasitic effects in the system is small, the LMS algorithm with a small step size has better performance. 1 When the value is 5.8, the small step size LMS algorithm converges slowly and is affected by p(n) during the convergence process, which easily leads to τ with a large difference from the actual clock constant. 0 The optimal solution is determined. At this time, the large step size LMS algorithm has better performance. The algorithm in this paper adds a variable step size strategy and selects parameters reasonably. When faced with clock constant increments caused by parasitic effects of different degrees, it can always solve τ with a smaller difference from the actual clock constant. 0 .

[0133] In this embodiment, the digital calibration technology provided by the present invention is used to realize the static parameters of 10-bit Uc-ReDAC1 and 11-bit Uc-ReDAC2. Fig.10 shown. Fig.10 (a) and (b) are the INL and DNL of Uc-ReDAC1, respectively. The maximum DNL (INL) is 0.98 (0.53) and the RMS value is 0.4 (0.27). Fig.10(c) and (d) are the INL and DNL of Uc-ReDAC2, respectively. The maximum DNL (INL) is 1.06 (0.79) and the RMS value is 0.42 (0.34).

[0134] Table 6 ReDAC performance comparison

[0135]

[0136] In this embodiment, Table 6 compares the performance of Uc-ReDAC generated based on the calibration method of the present invention and ReDAC implemented by different calibration methods. Method 1 solves the problem that the ReDAC system clock is an irrational number by finding a suitable r and setting σ=r. The realized ReDAC resolution is 10 bits, the maximum DNL (INL) is 0.45 (1.01), the root mean square value is 0.22 (0.36), and the sampling rate is 1.7MS / s. Method 2 After the ReDAC completes charging and discharging, the GPIO of the FPGA first outputs a low level for a short period of time and then switches to a high impedance state to offset the influence of the ReDAC parasitic effect. The realized ReDAC resolution is 11 bits, the maximum DNL (INL) is 1 (1.53), the root mean square value is 0.32 (0.42), and the sampling rate is 10.5kS / s.

[0137] At the same target voltage, Uc-ReDAC uses the AP-BPSO algorithm to find binary codes. Compared with ReDAC's use of SAR logic to find binary codes, the code length found is shorter. Therefore, Uc-ReDAC has a faster conversion speed. The present invention uses the proposed adaptive SLMS algorithm to find the actual clock constant in the circuit and regenerate the binary code set, suppressing the influence of parasitic effects on the system. The sampling rate of Uc-ReDAC1 is 6.76MS / s, and the sampling rate of Uc-ReDAC2 is 4.25MS / s.

Claims

1. A digital calibration method for an unconstrained relaxation type digital-to-analog converter based on a group least mean square algorithm, characterized in that: The steps include: S1: Initialize SLMS algorithm parameters and generate a random binary sequence b of length n a ; S2: Using l random binary sequences b of length n a Charge and discharge the calibration circuit of Uc-ReDAC and record the output voltage S3: Calculate the calibration voltage and the corresponding The error e(n) and calculate the mean error S4: Using the mean error Calculate the current adaptive step size of the SLMS algorithm; S5: Using the mean error And the current adaptive step size update weight coefficient m; S6: Determine whether the number of iterations is the maximum number of iterations. If not, update the optimal weight coefficient Gm and return to step S1. Otherwise, output τ0; S7: Generate a new binary code set based on the output τ0.

2. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 1, characterized in that: The SLMS algorithm parameters initialized in step S1 include the number of binary sequences l, n, T, τ, V DD , weight coefficient m, step size u and maximum number of iterations.

3. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 1, characterized in that: The mathematical model of Uc-ReDAC in step S2 is: Among them, V C,n Represents the voltage value across the capacitor at nT, V C,0 Represents the initial voltage value of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the clock period of the system, τ=RC represents the ideal time constant, n represents the length of the binary sequence, b i represents the i-th term of the binary sequence, and σ represents the exponential decay factor of the RC network.

4. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 1, characterized in that: The calibration voltage calculation formula in step S3 is: Among them, p(n) is interference noise with a mean value of 0, which is used to simulate the voltage error caused by other factors in the circuit.

5. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 4, characterized in that: In step S3, the calibration voltage corresponds to The error e(n) is calculated as:

6. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 5, characterized in that: The calculation of the current adaptive step length of the SLMS algorithm in step S4 includes: based on the charging characteristics of the capacitor, setting parameters in the capacitor charging function so that its function change curve meets the requirements of the variable step length LMS algorithm; the capacitor charging function is Where q(t) is the voltage of the capacitor at time t, Q max It is the steady-state voltage after the capacitor is fully charged; Based on the capacitor charging function, take the absolute value of the independent variable, add parameters a, b, c, and establish the relationship between step size and error By adjusting the values ​​of parameters a, b and c, the amplitude and variation trend of the step function are changed to be suitable for different adaptive filtering systems.

7. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 1, characterized in that: In step S5, the optimal iteration direction selection strategy is designed for the SLMS algorithm, and the weight coefficient m update formula is determined according to the functional relationship between the Uc-ReDAC output voltage and the RC network exponential decay factor; The optimal iteration direction selection strategy is as follows: design based on the average value of the first iteration error The method for determining the optimal iteration direction is as follows: Since the interval [σ,σ0] is a small range interval, The relationship between V c,n Whether it is increasing or decreasing in the interval [σ,σ0]; by judging Whether the value of is less than 0, determine the update formula of m and find the correct iteration direction; if m is less than 0, change the update formula of m; otherwise, keep the update formula of m unchanged.

8. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 7, characterized in that: The updating formula of the weight coefficient m in step S5 is: in, is the average of multiple errors, is the average error at the first iteration.

9. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 8, characterized in that: The initial value of Gm in step S6 is When the current error When it is less than Gm, update Gm to the current error Otherwise, keep the Gm value unchanged; When the number of iterations reaches the maximum number of iterations τ0=Gm×τ (7).

10. The unconstrained relaxation type digital-to-analog converter digital calibration method based on group least mean square algorithm according to claim 4, characterized in that: In step S7, a new binary code set is generated according to the output τ0, and the objective function is:

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