Automatic negotiation and link training architecture based on FPGA (Field Programmable Gate Array) and control method

Abstract

The invention relates to the technical field of Ethernet communication, in particular to an automatic negotiation and link training architecture based on an FPGA and a control method, and the architecture comprises a PMA physical medium connection module which comprises a plurality of channels, and each channel is provided with an AN / LT unit; the SWH exchange and processing module is used for receiving a plurality of channel data and distributing the channel data to the corresponding PCS physical coding sub-layer modules so as to carry out coding operation and decoding operation on the channel data; the AN auxiliary logic module and the AN / LT channel control logic module are mutually independent from the PCS physical coding sub-layer module, the AN auxiliary logic module is used for assisting the automatic negotiation function of an AN / LT unit, and the AN / LT channel control logic module is used for controlling the automatic negotiation and link training process of the AN / LT unit and channel rebinding processing. The invention provides a more flexible AN / LT architecture, and the capability of coping with complex and changeable working conditions is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet communication, and in particular to an automatic negotiation and link training architecture and a control method based on FPGA. Background Art

[0002] The AN / LT architecture, namely the Auto-negotiation (AN) and Link Training (LT) architecture, is a key technology for rate adaptation and signal optimization in high-speed Ethernet communications. In high-speed Ethernet communications, a series of preparations need to be performed before data transmission between communication terminals to ensure smooth communication. Among them, Auto-negotiation (AN) is a method of finding the best configuration supported by both parties through negotiation, while Link Training (LT) is the process of adjusting the characteristics of the transmission signal to ensure that the signal can be optimally transmitted through the link.

[0003] The traditional ASIC (application-specific integrated circuit) Ethernet AN / LT architecture has many limitations due to its customized nature. First, it does not support channel rebinding, which means that when the channel configuration needs to be changed to adapt to different application scenarios, the traditional ASIC architecture cannot respond flexibly. Secondly, the auxiliary logic of the traditional ASIC Ethernet AN / LT circuit is integrated in the PCS (physical coding sublayer) sublayer of the SerDes (serializer / deserializer). This design is not only inflexible, but also limits its application scenarios. In addition, the traditional ASIC Ethernet AN / LT circuit usually only supports a single protocol and cannot meet the needs of FPGA (field programmable gate array) scenarios that require flexibility in applicable scenarios.

[0004] As a programmable hardware platform, FPGA has a wide range of applications in the field of communications. In the FPGA scenario, the AN / LT function of SerDes needs to support all lanes of PMA (physical medium attachment) as the main lane, and PMA needs to be able to support MAC (media access control) connections with multiple links, and any lane can be used as a master lane. In addition, the SerDes of FPGA also needs to support protocols that do not contain AN / LT functions. However, traditional ASIC Ethernet AN / LT circuits cannot meet these requirements. Therefore, a more flexible AN / LT architecture needs to be designed for FPGA scenarios. Summary of the invention

[0005] In view of this, the present invention provides an automatic negotiation and link training architecture and control method based on FPGA to solve the problem that the traditional ASIC Ethernet AN / LT circuit has limitations in flexibility and applicability.

[0006] In a first aspect, the present invention provides an automatic negotiation and link training architecture based on FPGA, the automatic negotiation and link training architecture comprising:

[0007] A PMA physical medium connection module, used to establish a physical connection between a target communication device and a physical transmission medium; the PMA physical medium connection module includes a plurality of channels, each of which is provided with an AN / LT unit, and the AN / LT unit is used to perform automatic negotiation and link training functions on the corresponding channel;

[0008] The SWH switching and processing module is located between the PMA physical medium connection module and the PCS physical coding sublayer module, and is used to receive multiple channel data from the PMA physical medium connection module and distribute the multiple channel data to corresponding PCS physical coding sublayer modules;

[0009] A PCS physical coding sublayer module, used for performing encoding and decoding operations on the allocated channel data;

[0010] The AN auxiliary logic module and the AN / LT channel control logic module are respectively connected to the SWH switching and processing module, and are independent of the PCS physical coding sublayer module; the AN auxiliary logic module is used to assist the automatic negotiation function of the AN / LT unit, and the AN / LT channel control logic module is used to control the automatic negotiation and link training process of the AN / LT unit, as well as the channel rebinding processing.

[0011] In an optional implementation, the automatic negotiation is used to determine the best communication parameters supported by both communicating parties, and the link training is used to optimize the transmission characteristics of the signal on the channel link.

[0012] In an optional implementation, the SWH switching and processing module is further configured to distribute the plurality of channel data to corresponding PCS physical coding sublayer modules according to preset data priorities and target transmission requirements.

[0013] In an optional implementation, the PCS physical coding sublayer module is also used to be compatible with multiple coding formats to adapt to different communication protocols and data types.

[0014] In an optional implementation, the AN auxiliary logic module includes:

[0015] AN status monitoring unit, used to monitor various status information during the automatic negotiation process in real time;

[0016] AN completion signal monitoring unit, used to detect the successful completion signal of the automatic negotiation process;

[0017] An FEC protocol monitoring unit is used to monitor the FEC protocol to correct transmission errors during data transmission;

[0018] AN protocol new page monitoring unit, used to track and detect newly appeared protocol pages;

[0019] The AN connection status output unit is used to output the connection status information after the automatic negotiation process.

[0020] In an optional implementation, the AN / LT channel control logic module includes:

[0021] AN operation control unit, used to control the start, pause, stop and switching operations of the automatic negotiation process at different stages;

[0022] LT enabling control unit, used to control the enabling and disabling of the link training function;

[0023] A signal handshake unit is used to control the signal handshake operation between the master channel and the slave channel.

[0024] In a second aspect, the present invention provides a control method for an automatic negotiation and link training architecture based on FPGA, the control method is applied to an automatic negotiation and link training architecture based on FPGA as described above, and the control method comprises:

[0025] Through the SWH switching and processing module, multiple channel data of the PMA physical medium connection module are distributed to the corresponding PCS physical coding sublayer module;

[0026] Through the AN / LT channel control logic module, based on the allocation results of the multiple channel data, a dynamic binding operation between the multiple channels is performed; the dynamic binding operation includes adjusting the master-slave relationship and the signal transmission path of each channel.

[0027] In an optional implementation, the performing of the dynamic binding operation among the multiple channels based on the allocation result of the multiple channel data by the AN / LT channel control logic module includes:

[0028] Obtaining a target binding indication through the AN / LT channel control logic module, and sending binding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data;

[0029] After the AN / LT unit of the PMA physical medium connection module completes the binding operation, a binding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module for subsequent data transmission processing;

[0030] Obtaining a rebinding indication through the AN / LT channel control logic module, and sending rebinding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data;

[0031] After the AN / LT unit of the PMA physical medium connection module completes the rebinding operation, a rebinding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module to re-perform subsequent data transmission processing.

[0032] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute a control method for an automatic negotiation and link training architecture based on FPGA according to the second aspect or any corresponding embodiment thereof.

[0033] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a control method for an automatic negotiation and link training architecture based on an FPGA according to the second aspect or any corresponding embodiment thereof.

[0034] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, which are used to enable a computer to execute a control method for an automatic negotiation and link training architecture based on FPGA according to the second aspect or any corresponding embodiment thereof.

[0035] The technical solution provided by the present invention may include the following beneficial effects:

[0036] In terms of the Ethernet automatic negotiation and link training (AN / LT) process, the present invention allows flexible configuration through soft logic, breaking the previous relatively fixed setting mode, and can adjust the various parameters and links in the AN / LT process according to different network environments and equipment requirements, greatly improving the system's ability to cope with complex and changeable working conditions. In addition, the present invention separates the AN auxiliary logic module from the PCS physical coding sublayer module of the SerDes, reducing the chip area it occupies; after removing the AN auxiliary logic module in the PCS physical coding sublayer module, the logic path is reduced, significantly reducing signal transmission delay, reducing timing jitter in data transmission, and improving the stability and accuracy of data transmission. This enables the present invention to operate stably at a higher frequency, avoiding communication failures such as bit errors and packet loss caused by timing problems, ensuring the high-quality operation of the communication link, and adapting to high-speed, large-data communication scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a structural diagram based on the existing AN / LT architecture;

[0039] Figure 2 is a structural schematic diagram of an automatic negotiation and link training architecture based on FPGA according to an embodiment of the present invention;

[0040] Figure 3 is a flow chart of a control method of an automatic negotiation and link training architecture based on FPGA according to an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of flexible AN / LT architecture channel rebinding based on FPGA according to an embodiment of the present invention;

[0042] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0044] In related technologies, most SerDes designed by ASIC are custom protocols and do not support channel rebinding. Only SerDes that support Ethernet support AN / LT, and its AN auxiliary logic is integrated in the PCS layer. Figure 1 As shown in the figure, the AN auxiliary logic is solidified in the PCS layer, which is not flexible enough and affects its area and timing. It is also impossible to rebind multiple channels. For example, the current application needs to bind lane0 and lane1, while the next application needs to bind lane0 and lane2. The traditional AN / LT architecture is not capable of the above functions.

[0045] It should be noted that in the ASIC (application-specific integrated circuit) design of related technologies, most SerDes use custom protocols. The functions of this type of custom protocol SerDes are relatively simple and do not have the ability to rebind channels. In other words, they cannot flexibly adjust the combination relationship between channels according to the dynamic changes of actual application scenarios to meet different data transmission requirements. Only SerDes designed for Ethernet supports automatic negotiation (AN) and link training (LT), which greatly limits the use of AN / LT functions in non-Ethernet application scenarios.

[0046] See also Figure 1 The structural diagram of the existing AN / LT architecture is shown in the figure. In the SerDes supporting Ethernet, the AN auxiliary logic is integrated into the PCS (physical coding sublayer). This fixed layout brings many disadvantages:

[0047] Lack of flexibility: Since it is fixed at the PCS layer, the AN auxiliary logic cannot change its configuration or calling method as needed. It is difficult for technicians to optimize and adjust it according to changing application scenarios, which greatly reduces the flexibility of the entire system.

[0048] Area and timing issues: Integration at the PCS layer occupies a certain amount of physical space on the chip, making it difficult to reduce the chip area. At the same time, it also lengthens the logical path of signal transmission, affecting the timing. Signal transmission is prone to unstable conditions such as delays and jitters, limiting the system's ability to operate stably at high frequencies.

[0049] Insufficient channel binding capability: Due to design limitations, the traditional architecture cannot realize the rebinding of multiple channels. For example, in the face of different channel binding requirements proposed by different application scenarios, such as the current application needs to bind lane0 and lane1 together to transmit data, and the next application needs to bind lane0 and lane2. This dynamic change demand exceeds the capability of the traditional AN / LT architecture, making it unable to adapt to the complex and changing actual business scenarios.

[0050] Based on this, the present invention proposes a flexible AN / LT architecture design based on the FPGA solution, which utilizes the programmable characteristics of FPGA, adds channel rebinding soft logic, removes the AN auxiliary logic from the PCS layer, and rebuilds it using soft logic. It can adjust the various parameters and links in the AN / LT process according to different network environments and equipment requirements, greatly improving the system's ability to cope with complex and changeable working conditions.

[0051] In this embodiment, an automatic negotiation and link training architecture based on FPGA is provided. Figure 21 is a schematic diagram of a structure of an automatic negotiation and link training architecture based on FPGA according to an embodiment of the present invention, wherein the automatic negotiation and link training architecture comprises:

[0052] A PMA physical medium connection module is used to establish a physical connection between a target communication device and a physical transmission medium; the PMA physical medium connection module includes a plurality of channels, each of which is provided with an AN / LT unit, and the AN / LT unit is used to perform automatic negotiation and link training functions on the corresponding channel;

[0053] The SWH switching and processing module is located between the PMA physical medium connection module and the PCS physical coding sublayer module, and is used to receive multiple channel data from the PMA physical medium connection module and distribute the multiple channel data to corresponding PCS physical coding sublayer modules;

[0054] The PCS physical coding sublayer module is used to encode and decode the allocated channel data;

[0055] The AN auxiliary logic module and the AN / LT channel control logic module are respectively connected to the SWH switching and processing module, and are independent of the PCS physical coding sublayer module; the AN auxiliary logic module is used to assist the automatic negotiation function of the AN / LT unit, and the AN / LT channel control logic module is used to control the automatic negotiation and link training process of the AN / LT unit, as well as the channel rebinding processing.

[0056] Furthermore, the PMA physical medium connection module includes multiple channel lanes (such as lane0 to laneN), and each lane has an AN / LT unit. The PMA physical medium connection module is responsible for connecting to the physical transmission medium (such as cables, optical fibers, etc.) and is the interface for data to enter and leave the physical medium. The AN / LT unit performs automatic negotiation and link training functions on each lane. Automatic negotiation is used to determine the best communication parameters (such as transmission rate, duplex mode, etc.) supported by both communicating parties, and link training is used to optimize the transmission characteristics of the signal on the link to ensure reliable data transmission.

[0057] The SWH switching and processing module is located between the PMA physical medium connection module and the PCS physical coding sublayer module, and plays a pivotal role in data transmission and processing. The SWH switching and processing module receives data from multiple lanes of the PMA physical medium connection module (i.e., channel data), and distributes this data to the subsequent PCS physical coding sublayer module or other related modules for processing according to certain rules and requirements. At the same time, it can also perform some preliminary processing or exchange operations on the data to meet the overall communication requirements of the system.

[0058] Figure 2It includes multiple PCS physical coding sublayer modules, which are connected to the SWH switching and processing modules respectively. The PCS physical coding sublayer module is responsible for encoding and decoding data at the physical layer. Encoding is to convert data from the upper layer into a signal format suitable for transmission on the physical medium, and decoding is to restore the signal received from the physical medium to the original data for subsequent processing and transmission.

[0059] The AN auxiliary logic module is mainly used to assist the automatic negotiation function of the AN / LT unit, such as monitoring the status of automatic negotiation and providing relevant auxiliary information to ensure the smooth progress and accuracy of the automatic negotiation process. The AN / LT channel control logic module is used to control the link training process of the AN / LT unit and channel-related operations, such as controlling the start, stop, and parameter adjustment of link training, as well as managing and controlling some characteristics and states of the channel to optimize link performance and ensure the normal operation of the channel.

[0060] Figure 2 In the figure, the AN / LT unit of each channel lane in the PMA physical medium connection module is connected to the SWH switching and processing module through arrows, indicating that data is transmitted from each channel lane of the PMA physical medium connection module to the SWH switching and processing module. The SWH switching and processing module is connected to multiple PCS physical coding sublayer modules. The direction of the arrow indicates that data flows from the SWH switching and processing module to the PCS physical coding sublayer module, realizing the transmission and interaction of data between different modules. The SWH switching and processing module is also connected to the AN auxiliary logic module and the AN / LT channel control logic module respectively. These connection relationships show that the AN auxiliary logic module and the AN / LT channel control logic module are removed from the PCS layer and work together with the PCS physical coding sublayer module to complete the relevant functions and operations in the entire communication process.

[0061] In an optional implementation, the automatic negotiation is used to determine the best communication parameters supported by both communicating parties, and the link training is used to optimize the transmission characteristics of the signal on the channel link.

[0062] In an optional implementation, the SWH switching and processing module is further configured to distribute the multiple channel data to corresponding PCS physical coding sublayer modules according to preset data priorities and target transmission requirements.

[0063] In an optional implementation, the PCS physical coding sublayer module is also used to be compatible with multiple coding formats to adapt to different communication protocols and data types.

[0064] In an optional implementation, the AN auxiliary logic module includes:

[0065] AN status monitoring unit, used to monitor various status information during the automatic negotiation process in real time;

[0066] AN completion signal monitoring unit, used to detect the successful completion signal of the automatic negotiation process;

[0067] An FEC protocol monitoring unit is used to monitor the FEC protocol to correct transmission errors during data transmission;

[0068] AN protocol new page monitoring unit, used to track and detect newly appeared protocol pages;

[0069] The AN connection status output unit is used to output the connection status information after the automatic negotiation process.

[0070] Furthermore, the AN auxiliary logic of this embodiment includes AN status monitoring, AN completion signal monitoring, FEC protocol monitoring, AN protocol new page monitoring and AN connection status output. That is, in the Ethernet AN / LT architecture of this embodiment, the various components of the AN auxiliary logic module have the following meanings:

[0071] AN status monitoring unit: used to monitor various status information in the automatic negotiation (AN) process in real time, such as the parameter matching progress of the two communicating parties in the negotiation process, the current negotiation strategy status, etc., so as to timely understand the dynamic situation of the negotiation and provide a basis for subsequent decision-making or adjustment.

[0072] AN completion signal monitoring unit: It mainly detects whether the automatic negotiation is successfully completed. Once the signal is detected, it means that both parties have determined the appropriate communication parameters, such as transmission rate, duplex mode, etc., and can enter the normal data transmission stage or trigger subsequent related operations.

[0073] FEC (Forward Error Correction) protocol monitoring unit: During data transmission, the forward error correction protocol can be used to correct transmission errors. Monitoring the FEC protocol can ensure the normal operation of the FEC mechanism during the AN process and subsequent data transmission, and timely discover problems in the execution of the FEC protocol, such as whether the error correction capability is normal, whether there is a protocol mismatch, etc., to ensure reliable data transmission.

[0074] AN protocol new page monitoring unit: In some complex AN protocols, there may be multiple pages of protocol content. This monitoring function is responsible for tracking and detecting whether there are new protocol pages, ensuring that no important protocol information is missed and that the negotiation process is carried out in accordance with the complete protocol specifications.

[0075] AN connection status output unit: outputs the connection status information after automatic negotiation to other related modules or systems. This connection status information may include whether the connection is successfully established, the stability of the connection, the key parameters determined by negotiation, etc., so that other parts of the system can perform corresponding operations according to the connection status, such as adjusting resource allocation, starting data transmission process or performing fault diagnosis, etc.

[0076] In an optional implementation, the AN / LT channel control logic module includes:

[0077] AN operation control unit, used to control the start, pause, stop and switching operations of the automatic negotiation process at different stages;

[0078] LT enabling control unit, used to control the enabling and disabling of the link training function;

[0079] The signal handshake unit is used to control the signal handshake operation between the master channel and the slave channel.

[0080] Furthermore, the AN / LT channel control logic of this embodiment includes AN operation control, LT enable control, and signal handshake (i.e., signal handshake between master lane and slave lane). That is, in the Ethernet AN / LT architecture of this embodiment, the various components of the AN / LT channel control logic module have the following meanings:

[0081] AN operation control unit: It is mainly responsible for controlling the start, pause, stop and switching of the automatic negotiation (AN) process at different stages. For example, when the system needs to renegotiate communication parameters or trigger the AN process under specific conditions, the AN operation control unit will issue corresponding instructions to drive the AN process to proceed according to the predetermined logic, ensuring the orderliness and effectiveness of the AN operation.

[0082] LT Enable Control Unit: used to control the enabling and disabling of the Link Training (LT) function. In some cases, such as system initialization, link status changes, or according to specific application requirements, the LT function needs to be turned on or off to adjust the transmission signal characteristics to optimize link performance. The LT Enable Control Unit can accurately control the state transition of the Link Training (LT) function according to the system status and instructions to ensure that the link training process is carried out at the appropriate time.

[0083] Signal handshake unit: In a multi-lane architecture, there are the concepts of master lane and slave lane. The signal handshake mechanism ensures effective communication and coordination between the master lane and the slave lane. For example, before data transmission, the signal handshake is used to confirm whether both parties are ready. During the transmission process, it can also be used to transmit status information, error indications, etc., to maintain reliable data transmission and collaborative work between different lanes, realize effective interaction and coordination between lanes during channel rebinding, and ensure the stability and flexibility of the system.

[0084] Furthermore, the SWH switching and processing module of this embodiment realizes data distribution through SWH logic, and the SWH switching and processing module plays a pivotal role in data distribution here. It can distribute the data received from the PMA physical medium connection module to different PCS physical coding sublayer modules. Through the reasonable allocation of the SWH switching and processing modules, this embodiment can send data to the most suitable PCS physical coding sublayer module for subsequent processing according to different application requirements. The AN auxiliary logic of the AN auxiliary logic module is implemented by soft logic, which realizes the decoupling of the PCS sublayer and the AN auxiliary logic. The AN auxiliary logic module is no longer an inherent component of the PCS sublayer, thereby reducing the implementation area of ​​the PCS sublayer in hardware. For chip design, this can save precious chip area, reduce the manufacturing cost of the chip, improve the integration of the chip, and leave more space for other functional modules. In addition, this embodiment separates the AN auxiliary logic, reduces the interference to the logical path of the PCS sublayer, reduces the timing impact on it, and enables data to be more accurately and quickly processed during the encoding and decoding process of the PCS sublayer, thereby improving the overall performance of the system. In addition, the AN auxiliary logic module and the AN / LT channel control logic module are built with FPGA soft logic. Since FPGA (field programmable gate array) soft logic is used to build the AN auxiliary logic and AN / LT channel rebinding logic, they are no longer fixed hardware circuits, but software logic that can be flexibly adjusted and modified through programming. This means that during system operation or at different stages of project development, technicians can easily modify the functions and behaviors of these logics according to specific needs, greatly improving the flexibility and efficiency of development. This embodiment can be specially customized for different application scenarios, greatly increasing the flexibility of use, and can also be quickly ported to different hardware, greatly increasing versatility.

[0085] In summary, this embodiment allows flexible configuration through soft logic in the Ethernet automatic negotiation and link training (AN / LT) process, breaking the previous relatively fixed setting mode, and can adjust the various parameters and links in the AN / LT process according to different network environments and equipment requirements, greatly improving the system's ability to cope with complex and changeable working conditions. In addition, this embodiment separates the AN auxiliary logic module from the PCS physical coding sublayer module of the SerDes, reducing the chip area it occupies; after removing the AN auxiliary logic module in the PCS physical coding sublayer module, the logic path is reduced, significantly reducing the signal transmission delay, reducing the timing jitter in data transmission, and improving the stability and accuracy of data transmission. This enables the present embodiment to operate stably at a higher frequency, avoiding communication failures such as bit errors and packet loss caused by timing problems, ensuring the high-quality operation of the communication link, and adapting to high-speed and large-data communication scenarios.

[0086] According to an embodiment of the present invention, an embodiment of a control method for an automatic negotiation and link training architecture based on an FPGA is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0087] In this embodiment, a control method based on FPGA automatic negotiation and link training architecture is provided. The control method is applied to Figure 2 In the FPGA-based automatic negotiation and link training architecture shown in FIG. Figure 3 is a flow chart of a control method of an automatic negotiation and link training architecture based on FPGA according to an embodiment of the present invention, such as Figure 3 As shown, the process includes the following steps:

[0088] Step S301: distribute multiple channel data of the PMA physical medium connection module to corresponding PCS physical coding sublayer modules through the SWH switching and processing module.

[0089] Furthermore, step S301 is mainly responsible for performing preliminary distribution processing on the channel data received from the PMA physical medium connection module. The PMA physical medium connection module includes multiple channels, each of which carries data to be transmitted, which may come from different data sources or have different characteristics. The SWH switching and processing module serves as the hub of data distribution, and distributes these channel data to the corresponding PCS physical coding sublayer module according to certain rules. Different PCS physical coding sublayer modules can be responsible for different types of data processing. Through reasonable distribution, data can be distributed to the most suitable processing unit to improve the processing efficiency of the entire system. For example, according to the priority, data type or information of the target receiving end of the data, the SWH switching and processing module distributes the data to different PCS physical coding sublayer modules for subsequent more accurate encoding or decoding operations.

[0090] Step S302, through the AN / LT channel control logic module, based on the allocation result of the multiple channel data, a dynamic binding operation between the multiple channels is performed; the dynamic binding operation includes adjusting the master-slave relationship and the signal transmission path of each channel.

[0091] Furthermore, step S302 aims to dynamically adjust the relationship between multiple channels and the signal transmission path according to the current channel data allocation to optimize the performance and reliability of the entire communication link. The AN / LT channel control logic module decides how to bind the channels based on the allocation results of multiple channel data. In a multi-channel communication system, some channels may be set as master channels, while other channels are slave channels. By adjusting the master-slave relationship, the data transmission process can be optimized. Different signal transmission paths may have different performance characteristics, such as different bandwidths, delays or reliability. By dynamically adjusting the signal transmission path, data can select the most suitable path for transmission to avoid congestion or failure of certain paths affecting data transmission. For example, when it is monitored that the performance of a transmission path has degraded or a failure has occurred, the data can be switched to other paths with better performance to ensure the continuity and efficiency of data transmission.

[0092] In an optional implementation, step S302 includes:

[0093] Obtaining a target binding indication through the AN / LT channel control logic module, and sending binding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data;

[0094] After the AN / LT unit of the PMA physical medium connection module completes the binding operation, a binding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module for subsequent data transmission processing;

[0095] Obtaining a rebinding indication through the AN / LT channel control logic module, and sending rebinding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data;

[0096] After the AN / LT unit of the PMA physical medium connection module completes the rebinding operation, a rebinding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module to re-perform subsequent data transmission processing.

[0097] Further, the AN / LT channel control logic module first receives a target binding indication from other parts of the system or an upper control unit. This indication contains information about how to bind channels, such as which channels need to be bound together and in what manner. The AN / LT channel control logic module sends the corresponding binding data to the PMA physical medium connection module based on the received binding indication and the allocation results of the existing multiple channel data. The AN / LT unit in the PMA physical medium connection module completes the actual binding operation on the physical layer according to the received binding data, including adjusting the connection and configuration of the channel. When the binding operation is completed, the PMA physical medium connection module sends a successful binding status signal to the AN / LT channel control logic module to notify it that the binding operation has been completed. After receiving the status signal, the AN / LT channel control logic module performs subsequent data transmission processing according to the information, such as adjusting the data sending and receiving strategy according to the bound channel status to ensure that the data is stably transmitted on the bound channel. Similar to the acquisition of the target binding indication, the rebinding indication is generated when the system needs to readjust the channel binding relationship, which may be triggered by changes in link status, changes in network environment, or dynamic adjustment requirements of system performance. Based on the rebinding indication and channel data allocation results, the AN / LT channel control logic module sends the rebinding data to the PMA physical media connection module, which contains new binding requirements to guide the AN / LT unit to perform the rebinding operation. The AN / LT unit in the PMA physical media connection module performs the rebinding operation according to the rebinding data and readjusts the connection and configuration of the channel. After completing the rebinding operation, the PMA physical media connection module returns a successful rebinding status signal to the AN / LT channel control logic module. After receiving this signal, the AN / LT channel control logic module re-evaluates and optimizes subsequent data transmission processing according to the new channel status, such as updating the data transmission route, reallocating bandwidth, or adjusting transmission priority, etc., to adapt to the new channel binding situation and ensure continuous, efficient and stable data transmission.

[0098] For further information, see Figure 4The schematic diagram of flexible AN / LT architecture channel rebinding based on FPGA is shown. In this embodiment, arbitrary binding between multiple channels is realized by adding AN / LT channel control logic module, such as Figure 4 As shown, in a hardware device with 4 lanes, if the current application requires lane0 to be bound to lane1, re-binding data is sent to the PMA physical medium connection module through the AN / LT channel control logic module, and the AN / LT unit of the PMA physical medium connection module returns a successful binding status signal to the AN / LT channel control logic module after running, and performs subsequent data transmission; if a subsequent application requires lane0 to be bound to lane2, re-binding data is sent to the PMA physical medium connection module through the AN / LT channel control logic module, and the AN / LT unit of the PMA physical medium connection module returns a successful binding status signal to the AN / LT channel control logic module after running, and performs subsequent data transmission again.

[0099] In summary, this embodiment allows flexible configuration through soft logic in the Ethernet automatic negotiation and link training (AN / LT) process, breaking the previous relatively fixed setting mode, and can adjust the various parameters and links in the AN / LT process according to different network environments and equipment requirements, greatly improving the system's ability to cope with complex and changeable working conditions. In addition, this embodiment separates the AN auxiliary logic module from the PCS physical coding sublayer module of the SerDes, reducing the chip area it occupies; after removing the AN auxiliary logic module in the PCS physical coding sublayer module, the logic path is reduced, significantly reducing the signal transmission delay, reducing the timing jitter in data transmission, and improving the stability and accuracy of data transmission. This enables the present embodiment to operate stably at a higher frequency, avoiding communication failures such as bit errors and packet loss caused by timing problems, ensuring the high-quality operation of the communication link, and adapting to high-speed and large-data communication scenarios.

[0100] The embodiment of the present invention also provides a computer device, see Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0101] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0102] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0103] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0104] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0105] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0106] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0107] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0108] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. An FPGA-based automatic negotiation and link training architecture, characterized in that: The auto-negotiation and link training architecture includes: A PMA physical medium connection module, used to establish a physical connection between a target communication device and a physical transmission medium; the PMA physical medium connection module includes a plurality of channels, each of which is provided with an AN / LT unit, and the AN / LT unit is used to perform automatic negotiation and link training functions on the corresponding channel; The SWH switching and processing module is located between the PMA physical medium connection module and the PCS physical coding sublayer module, and is used to receive multiple channel data from the PMA physical medium connection module and distribute the multiple channel data to corresponding PCS physical coding sublayer modules; A PCS physical coding sublayer module, used for performing encoding and decoding operations on the allocated channel data; The AN auxiliary logic module and the AN / LT channel control logic module are respectively connected to the SWH switching and processing module, and are independent of the PCS physical coding sublayer module; the AN auxiliary logic module is used to assist the automatic negotiation function of the AN / LT unit, and the AN / LT channel control logic module is used to control the automatic negotiation and link training process of the AN / LT unit, as well as the channel rebinding processing.

2. The automatic negotiation and link training architecture according to claim 1, characterized in that: The automatic negotiation is used to determine the best communication parameters supported by both communicating parties, and the link training is used to optimize the transmission characteristics of the signal on the channel link.

3. The automatic negotiation and link training architecture according to claim 1, characterized in that: The SWH switching and processing module is further used to distribute the multiple channel data to corresponding PCS physical coding sublayer modules according to preset data priorities and target transmission requirements.

4. The automatic negotiation and link training architecture according to claim 1, characterized in that: The PCS physical coding sublayer module is also used to be compatible with multiple coding formats to adapt to different communication protocols and data types.

5. The automatic negotiation and link training architecture according to claim 1, characterized in that: The AN auxiliary logic module includes: AN status monitoring unit, used to monitor various status information during the automatic negotiation process in real time; AN completion signal monitoring unit, used to detect the successful completion signal of the automatic negotiation process; An FEC protocol monitoring unit is used to monitor the FEC protocol to correct transmission errors during data transmission; AN protocol new page monitoring unit, used to track and detect newly appeared protocol pages; The AN connection status output unit is used to output the connection status information after the automatic negotiation process.

6. The automatic negotiation and link training architecture according to claim 1, characterized in that: The AN / LT channel control logic module includes: AN operation control unit, used to control the start, pause, stop and switching operations of the automatic negotiation process at different stages; LT enabling control unit, used to control the enabling and disabling of the link training function; The signal handshake unit is used to control the signal handshake operation between the master channel and the slave channel.

7. A control method for an automatic negotiation and link training architecture based on FPGA, the control method being applied to an automatic negotiation and link training architecture based on FPGA as claimed in any one of claims 1 to 6, characterized in that: The control method comprises: Through the SWH switching and processing module, multiple channel data of the PMA physical medium connection module are distributed to the corresponding PCS physical coding sublayer module; Through the AN / LT channel control logic module, based on the allocation results of the multiple channel data, a dynamic binding operation between the multiple channels is performed; the dynamic binding operation includes adjusting the master-slave relationship and the signal transmission path of each channel.

8. The control method according to claim 7, characterized in that: The performing of the dynamic binding operation among the multiple channels based on the allocation result of the multiple channel data by the AN / LT channel control logic module includes: Obtaining a target binding indication through the AN / LT channel control logic module, and sending binding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data; After the AN / LT unit of the PMA physical medium connection module completes the binding operation, a binding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module for subsequent data transmission processing; Obtaining a rebinding indication through the AN / LT channel control logic module, and sending rebinding data to the PMA physical medium connection module based on the allocation result of the plurality of channel data; After the AN / LT unit of the PMA physical medium connection module completes the rebinding operation, a rebinding success status signal is returned to the AN / LT channel control logic module through the PMA physical medium connection module to re-perform subsequent data transmission processing.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the control method of the FPGA-based automatic negotiation and link training architecture as described in claim 7 or 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the control method of an automatic negotiation and link training architecture based on FPGA as described in claim 7 or 8.

Images