Video acquisition processing circuit and configuration method

Abstract

The invention provides a video acquisition processing circuit and a configuration method. The video acquisition processing circuit comprises an application processor, a synchronous rectification step-down circuit, a video conversion circuit, a synchronous step-down converter and a power supply step-down circuit, the synchronous rectification step-down circuit, the synchronous step-down converter and the power supply step-down circuit are all connected to the application processor, and the application processor is connected with the video conversion circuit; the application processor is used for collecting and outputting HDMI video data; the synchronous rectification step-down circuit is used for providing 4V voltage for the application processor, the power supply step-down circuit is used for providing 3.3 V voltage for the application processor, and the synchronous step-down converter is used for providing 5V voltage for the application processor; the video conversion circuit is used for converting the HDMI video data into LVDS signals and outputting the LVDS signals to a terminal display device. The HDMI video signal output by the application processor is processed by the video conversion circuit to generate an LVDS signal and the LVDS signal is displayed to the terminal equipment, so that the data security of the equipment is effectively enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of video acquisition and display, and in particular to a video acquisition processing circuit and a configuration method. Background Art

[0002] With the rapid development of communication technology, the requirements for the display screens of EMUs are constantly increasing, requiring not only improved display effects, but also improved power consumption and process. Existing application processors have the characteristics of high computing power, low power consumption, super multimedia, and rich data interfaces. However, there is currently a lack of matching circuits for the deep integration of application processors and domestic operating systems. Summary of the invention

[0003] In view of this, the embodiments of this specification provide a video acquisition and processing circuit and a configuration method to reduce the risk of dependence on external supply chains, enhance the data security of equipment, and improve localization.

[0004] The embodiments of this specification provide the following technical solutions:

[0005] A video acquisition and processing circuit, comprising:

[0006] Application processor, synchronous rectification buck circuit, video conversion circuit, synchronous buck converter and power buck circuit;

[0007] The synchronous rectification buck circuit, the synchronous buck converter and the power buck circuit are all connected to the application processor, and the application processor is connected to the video conversion circuit;

[0008] The application processor is used to collect and output HDMI video data;

[0009] The synchronous rectifier step-down circuit is used to provide a 4V voltage for the application processor, the power step-down circuit is used to provide a 3.3V voltage for the application processor, and the synchronous step-down converter is used to provide a 5V voltage for the application processor;

[0010] The video conversion circuit is used to convert HDMI video data into LVDS signals and output the LVDS signals to the terminal display device.

[0011] Furthermore, the application processor includes:

[0012] HDMI TX1 pin, HDMI auxiliary pin and HDMI power pin;

[0013] HDMI TX1 pins include DMI_TX1_D0P / eDP_TX1_D0P pin, HDMI_TX1_D1N / eDP_TX1_D1N pin, HDMI_TX1_D2P / eDP_TX1_D2P pin, HDMI_TX1_D3N / eDP_TX1_D3N pin, HDMI_TX1_D0N / eDP_TX1_D0N pin, HDMI_TX1_D2N / eDP_TX1_D2N pin, and HDMI_TX1_D3N / eDP_TX1_D3N pin;

[0014] HDMI auxiliary pins include HDMI_TX1_SBDP / eDP_TX1_AUXP pin and HDMI_TX1_SBDN / eDP_TX1_AUXN pin;

[0015] The HDMI power pins include the HDMI / eDP_TX1_VDD_CMN_1V8 pin, the HDMI / eDP_TX1_VDD_IO_1V8 pin, and the HDMI / eDP_TX1_VDD_0V75 pin.

[0016] Furthermore, the synchronous rectification step-down circuit includes:

[0017] Input pin IN, output pin OUT, enable pin EN, feedback pin FB and PG pin;

[0018] The input pin IN is used to receive an input voltage ranging from 4.5V to 26V;

[0019] The output pin OUT is used to provide a stepped-down stable output voltage, the stable output voltage is 600mV to 5.5V;

[0020] The enable pin EN is used to control the opening and closing of the synchronous rectification buck circuit. It is enabled when the level is low and closed when the level is high.

[0021] The PG pin is used to indicate power;

[0022] The feedback pin FB is used to set the output voltage by connecting external resistor R1 and external resistor R2.

[0023] Furthermore, the power supply step-down circuit includes:

[0024] RT / CLK pin, GND ground pin, PVIN input pin, PVIN input pin, VSENSE input pin, COMP output pin, SS / TR output pin, EN input pin and PH output pin;

[0025] The RT / CLK pin is used to automatically select RT mode and CLK mode;

[0026] The GND ground pin is used for the return of the control circuit and the low-side power MOSFET;

[0027] The PVIN input pin is used to provide the power switch of the power converter;

[0028] The VIN input pin is used to provide power;

[0029] The VSENSE input pin is used for the inverting input of the gm error amplifier;

[0030] COMP output pin is used for frequency compensation;

[0031] The SS / TR output pin is used for tracking and timing control;

[0032] The EN input pin is the enable pin;

[0033] The PH output pin is the switching node.

[0034] A configuration method for a video acquisition processing circuit, the configuration method configuring the video acquisition processing circuit, comprising:

[0035] Configure the HDMI interface of the application processor in the device tree;

[0036] Configure the video conversion circuit.

[0037] Furthermore, the HDMI interface of the application processor is configured in the device tree, including:

[0038] Enable the function of the first HDMI display output interface of the application processor;

[0039] Connecting the first HDMI display output interface to the video output port of the application processor;

[0040] Enable the audio output of the first HDMI display output interface;

[0041] Opening the first HDMI display output interface and a physical layer circuit associated with the first HDMI display output interface;

[0042] Open the startup logo of the first HDMI display output interface.

[0043] Further, the video conversion circuit is configured, including:

[0044] Configure the corresponding device tree and open the corresponding macro;

[0045] After the video conversion circuit is powered on, the chip ID register of the video conversion circuit is first read to confirm whether the I2C communication is normal, and the register of the video conversion circuit is configured;

[0046] After confirming that the MIPI signal is output normally and the register configuration of the video conversion circuit is correct, light up the terminal display device.

[0047] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0048] The HDMI high-definition video signal is output through the application processor, and then decoded, processed and encoded by the video conversion circuit to generate an LVDS video signal to drive the terminal display device for display. This can reduce the risk of dependence on the external supply chain, enhance the data security of the equipment, and improve localization. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 is a schematic diagram of the overall structure of a video acquisition and processing circuit according to an embodiment of the present invention;

[0051] Figure 2 is a schematic diagram of an application processor according to an embodiment of the present invention;

[0052] Figure 3 is a schematic diagram of a synchronous rectification and buck circuit according to an embodiment of the present invention;

[0053] Figure 4 is a schematic diagram of a synchronous buck converter according to an embodiment of the present invention;

[0054] Figure 5 is a schematic diagram of a power supply step-down circuit according to an embodiment of the present invention;

[0055] Figure 6 is a schematic diagram of a video conversion circuit according to an embodiment of the present invention;

[0056] Figure 7 is a schematic diagram of a USB 3.0 interface of an application processor according to an embodiment of the present invention;

[0057] Figure 8 is a schematic diagram of a PCIE interface of an application processor according to an embodiment of the present invention;

[0058] Fig. 9 Schematic diagram of the RGMII interface of the application processor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0060] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0061] like Figure 1 As shown, a video acquisition processing circuit includes:

[0062] Application processor, synchronous rectification step-down circuit, video conversion circuit, synchronous step-down converter and power supply step-down circuit.

[0063] The synchronous rectification buck circuit, the synchronous buck converter and the power buck circuit are all connected to the application processor, and the application processor is connected to the video conversion circuit.

[0064] The application processor is used to collect and output HDMI video data, the synchronous rectification step-down circuit is used to provide 4V voltage for the application processor, the power step-down circuit is used to provide 3.3V voltage for the application processor, and the synchronous step-down converter is used to provide 5V voltage for the application processor. The video conversion circuit is used to convert HDMI video data into LVDS signals and output the LVDS signals to the terminal display device.

[0065] In the embodiment of the present invention, the application processor can use the RK3588 chip, and the video conversion circuit can use the Longxun LT6211 chip. The HDMI signal provided by RK3588 is converted into an LVDS signal by Longxun LT6211, and then the display screen is lit. In addition, RK3588 has multiple interfaces, which can easily provide various USB, I2C, and UART signals to realize specific functions.

[0066] like Figure 2 As shown, the application processor includes:

[0067] HDMI TX1 pin, HDMI auxiliary pin and HDMI power pin. Among them, HDMI TX1 pin includes DMI_TX1_D0P / eDP_TX1_D0P pin, HDMI_TX1_D1N / eDP_TX1_D1N pin, HDMI_TX1_D2P / eDP_TX1_D2P pin, HDMI_TX1_D3N / eDP_TX1_D3N pin, HDMI_TX1_D0N / eDP_TX1_D0N pin, HDMI_TX1_D2N / eDP_TX1_D2N pin, HDMI_TX1_D3N / eDP_TX1_D3N pin. HDMI auxiliary pins include HDMI_TX1_SBDP / eDP_TX1_AUXP pin and HDMI_TX1_SBDN / eDP_TX1_AUXN pin; HDMI power pins include HDMI / eDP_TX1_VDD_CMN_1V8 pin, HDMI / eDP_TX1_VDD_IO_1V8 pin and HDMI / eDP_TX1_VDD_0V75 pin.

[0068] like Figure 3 As shown, the synchronous rectification buck circuit includes:

[0069] Input pin IN, output pin OUT, enable pin EN, feedback pin FB and PG pin.

[0070] The input pin IN is used to receive an input voltage ranging from 4.5V to 26V; the output pin OUT is used to provide a stable output voltage after step-down, and the stable output voltage is 600mV to 5.5V; the enable pin EN is used to control the opening and closing of the synchronous rectification step-down circuit, which is enabled at a low level and closed at a high level; the PG pin is used to indicate power; the feedback pin FB is used to set the output voltage by connecting the external resistor R1 and the external resistor R2.

[0071] In the embodiment of the present invention, the synchronous rectification and buck circuit can use the MP8759 chip. RK3588 requires 4V power supply, which is realized by the synchronous rectification and buck chip MP8759, and the LDO chip MP8759 is used to convert 12V into 4V.

[0072] like Figure 4 As shown, the synchronous buck converter includes: a BS pin, a FB pin, an EN pin and a LX pin.

[0073] The BS pin is used to supply the high-side gate drive voltage; the FB pin is connected to the midpoint of the output first resistor divider R3 and the second resistor divider R2 and is used for output feedback; the EN pin is used for enable control; and the LX pin is connected to the switch node of the inductor.

[0074] In the embodiment of the present invention, the synchronous buck converter can use the SY8113B chip. Each module needs 5V and 3V3 power supply, the 5V power supply is provided by the synchronous buck converter SY8113B, and the 3V3 power supply is provided by the DCDC power buck chip TPS54620RGYR.

[0075] like Figure 5 As shown, the power supply step-down circuit includes:

[0076] RT / CLK pin, GND ground pin, PVIN input pin, PVIN input pin, VSENSE input pin, COMP output pin, SS / TR output pin, EN input pin and PH output pin.

[0077] The RT / CLK pin is used to automatically select RT mode and CLK mode; the GND ground pin is used to return the control circuit and the low-side power MOSFET; the PVIN input pin is used to provide the power switch of the power converter; the VIN input pin is used to provide power; the VSENSE input pin is used for the inverting input of the gm error amplifier; the COMP output pin is used for frequency compensation; the SS / TR output pin is used for tracking and timing control; the EN input pin is the enable pin; and the PH output pin is the switching node.

[0078] like Figure 6 As shown, in one embodiment of the present invention, the video conversion circuit may use the Longxun LT6211 chip.

[0079] like Figure 7 , Figure 8 , Fig. 9 As shown, the RK3588 chip also supports multiple interfaces, such as USB3.0, PCIE and RGMII.

[0080] A configuration method for a video acquisition processing circuit, the configuration method configuring the video acquisition processing circuit, comprising:

[0081] Configure the HDMI interface of the application processor in the device tree;

[0082] Configure the video conversion circuit.

[0083] Specifically, configuring the HDMI interface of the application processor in the device tree includes the following steps:

[0084] Enable the function of the first HDMI display output interface of the application processor;

[0085] Connecting the first HDMI display output interface to the video output port of the application processor;

[0086] Enable the audio output of the first HDMI display output interface;

[0087] Opening the first HDMI display output interface and a physical layer circuit associated with the first HDMI display output interface;

[0088] Open the startup logo of the first HDMI display output interface.

[0089] Specifically, configuring the video conversion circuit includes the following steps:

[0090] Configure the corresponding device tree and open the corresponding macro;

[0091] After the video conversion circuit is powered on, the chip ID register of the video conversion circuit is first read to confirm whether the I2C communication is normal, and the register of the video conversion circuit is configured;

[0092] After confirming that the MIPI signal is output normally and the register configuration of the video conversion circuit is correct, light up the terminal display device.

[0093] Beneficial effects of the embodiments of the present invention:

[0094] The HDMI high-definition video signal is output through the application processor, and then the LVDS video signal is generated after decoding, video processing and encoding by the video conversion circuit to drive the terminal display device for display. The application processor has the function of receiving external instructions and data to complete the generation, decoding and display of graphics; this technology is mainly used in scenarios such as smart cockpits, smart large screens, AR / VR, edge computing, high-end IPC, NVR, high-end tablets and ARM PCs in China, and is the core system and key technology of EMUs. This circuit design has low cost and low power consumption under the premise of meeting performance requirements. It not only meets the relevant technical indicators of high-speed EMUs, but also has the technical level of similar products at home and abroad, getting rid of dependence on and restrictions on foreign technology, and at the same time generating good economic and social benefits in the rail transit industry. It has high application value and broad prospects in the field of domestic high-speed rail and subway, and provides certain technical support for rail transit Ethernet communication systems.

[0095] The above is only a specific embodiment of the present invention, and cannot be used to limit the scope of the invention. Therefore, the replacement of equivalent components, or equivalent changes and modifications made according to the scope of protection of the patent of the present invention, should still fall within the scope of this patent. In addition, the technical features of the present invention can be freely combined with each other, with each other, and with each other.

Claims

1. A video acquisition and processing circuit, characterized in that: include: Application processor, synchronous rectification buck circuit, video conversion circuit, synchronous buck converter and power buck circuit; The synchronous rectification and buck circuit, the synchronous buck converter and the power buck circuit are all connected to the application processor, and the application processor is connected to the video conversion circuit; The application processor is used to collect and output HDMI video data; The synchronous rectification step-down circuit is used to provide a 4V voltage for the application processor, the power supply step-down circuit is used to provide a 3.3V voltage for the application processor, and the synchronous step-down converter is used to provide a 5V voltage for the application processor; The video conversion circuit is used to convert the HDMI video data into an LVDS signal, and output the LVDS signal to a terminal display device.

2. The video acquisition processing circuit according to claim 1, characterized in that: The application processor comprises: HDMI TX1 pin, HDMI auxiliary pin and HDMI power pin; The HDMI TX1 pin includes a DMI_TX1_D0P / eDP_TX1_D0P pin, a HDMI_TX1_D1N / eDP_TX1_D1N pin, a HDMI_TX1_D2P / eDP_TX1_D2P pin, a HDMI_TX1_D3N / eDP_TX1_D3N pin, a HDMI_TX1_D0N / eDP_TX1_D0N pin, a HDMI_TX1_D2N / eDP_TX1_D2N pin, and a HDMI_TX1_D3N / eDP_TX1_D3N pin; The HDMI auxiliary pins include a HDMI_TX1_SBDP / eDP_TX1_AUXP pin and a HDMI_TX1_SBDN / eDP_TX1_AUXN pin; The HDMI power pins include a HDMI / eDP_TX1_VDD_CMN_1V8 pin, a HDMI / eDP_TX1_VDD_IO_1V8 pin, and a HDMI / eDP_TX1_VDD_0V75 pin.

3. The video acquisition processing circuit according to claim 1, characterized in that: The synchronous rectification step-down circuit comprises: Input pin IN, output pin OUT, enable pin EN, feedback pin FB and PG pin; The input pin IN is used to receive an input voltage ranging from 4.5V to 26V; The output pin OUT is used to provide a stepped-down stable output voltage, wherein the stable output voltage is 600mV to 5.5V; The enable pin EN is used to control the synchronous rectification buck circuit to be turned on and off, which is enabled when the voltage is low and turned off when the voltage is high; The PG pin is used to indicate power; The feedback pin FB is used to set the output voltage by connecting an external resistor R1 and an external resistor R2.

4. The video acquisition processing circuit according to claim 1, characterized in that: The power supply step-down circuit comprises: RT / CLK pin, GND ground pin, PVIN input pin, PVIN input pin, VSENSE input pin, COMP output pin, SS / TR output pin, EN input pin and PH output pin; The RT / CLK pin is used to automatically select the RT mode and the CLK mode; The GND ground pin is used for the return of the control circuit and the low-side power MOSFET; The PVIN input pin is used to provide a power switch for the power converter; The VIN input pin is used to provide power; The VSENSE input pin is used for the inverting input of the gm error amplifier; The COMP output pin is used for frequency compensation; The SS / TR output pin is used for tracking and timing control; The EN input pin is an enable pin; The PH output pin is a switching node.

5. A method for configuring a video acquisition processing circuit, the method configuring the video acquisition processing circuit according to any one of claims 1 to 4, characterized in that: Configuring the HDMI interface of the application processor in a device tree; Configure the video conversion circuit.

6. The configuration method of the video acquisition and processing circuit according to claim 5, characterized in that: The HDMI interface of the application processor is configured in the device tree, including: Enable the function of the first HDMI display output interface of the application processor; Connecting the first HDMI display output interface to the video output port of the application processor; Turn on the audio output of the first HDMI display output interface; Opening the first HDMI display output interface and a physical layer circuit associated with the first HDMI display output interface; Turn on the startup logo of the first HDMI display output interface.

7. The configuration method of the video acquisition and processing circuit according to claim 5, characterized in that: Configure the video conversion circuit, including: Configure the corresponding device tree and open the corresponding macro; After the video conversion circuit is powered on, the chip ID register of the video conversion circuit is first read to confirm whether the I2C communication is normal, and the register of the video conversion circuit is configured; After determining that the MIPI signal is output normally and the register configuration of the video conversion circuit is correct, the terminal display device is turned on.

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