Multichannel data acquisition system of microphone area array

Abstract

The invention discloses a multichannel data acquisition system of a microphone area array, which comprises a peripheral hardware module, a microprocessor, an Ethernet interface, an upper computer and a voltage conversion module, the peripheral hardware module, the microprocessor, the Ethernet interface and the upper computer are connected in sequence, the voltage conversion module converts a system power supply into adaptive voltage, and the adaptive voltage is transmitted to the upper computer. And power is respectively supplied to the peripheral hardware module, the microprocessor and the Ethernet interface. The data acquisition system provided by the invention is high in integration level and small in size, can be installed on the surface of a small-size navigation body model in a wind tunnel experiment, accurately measures the pulsating pressure on the surface of the model, and avoids interference caused by too long leads in the prior art. According to the microprocessor, logic resources of the FPGA chip are effectively utilized, and the cost is greatly reduced. The method not only can be used for measurement of a microphone area array, but also can be used for data acquisition of other weak signals subsequently.

Description

Technical Field

[0001] The invention belongs to the technical field of navigation body data collection, and in particular relates to the design of a multi-channel data collection system of a microphone array. Background Art

[0002] The fluid dynamic noise of a vehicle is an important indicator that affects its own safety, and the surface pulsating pressure is one of the important excitation sources of the fluid dynamic noise of medium and high-speed vehicles. Therefore, accurately measuring the pulsating pressure distribution on the surface of a vehicle is of great significance for optimizing the structure of the vehicle, reducing noise, and improving the stealth performance of the vehicle. Microphone arrays are a major measurement tool for measuring the pulsating pressure on the surface of a vehicle. In order to improve the accuracy and real-time performance of the microphone array in collecting pulsating pressure, it is necessary to integrate the acquisition system with the microphone array and place it on the model surface for measurement. Therefore, the acquisition system needs to be miniaturized while having high precision and high sampling rate.

[0003] Traditional multi-channel data acquisition systems achieve multi-channel data acquisition by connecting multiple FPGA core boards and analog-to-digital conversion chips in parallel. This type of structure often results in the logic resources of each core board not being fully utilized, and the acquisition system is too large and expensive. Due to the limitation of the model volume, the multi-channel data acquisition system of the microphone array must be miniaturized, so the traditional data acquisition system is not suitable for measuring the pulsating pressure on the surface of the curved model in the wind tunnel test. Summary of the invention

[0004] The purpose of the present invention is to solve the problem that the existing data acquisition system is difficult to be installed on the model surface due to its large size. A multi-channel data acquisition system with a microphone array is proposed, which can accurately measure the weak and broadband pulsating pressure on the surface of small-volume models in wind tunnel experiments.

[0005] The technical solution of the present invention is: a multi-channel data acquisition system for a microphone array, comprising a peripheral hardware module, a microprocessor, an Ethernet interface, a host computer and a voltage conversion module, wherein the peripheral hardware module, the microprocessor, the Ethernet interface and the host computer are connected in sequence, the host computer sends a control signal to the microprocessor through the Ethernet interface, the microprocessor drives the peripheral hardware module to collect analog signals of the microphone array according to the control signal, and generates digital signals through analog-to-digital conversion, the microprocessor asynchronously caches the digital signals and then uploads them to the host computer through the Ethernet interface for analysis and display, and the voltage conversion module converts the system power supply into an adaptive voltage and then supplies power to the peripheral hardware module, the microprocessor and the Ethernet interface respectively.

[0006] Furthermore, the peripheral hardware module includes 16 AD7606 chips, each of which has the same structure. The AVCC1 pin of the AD7606 chip is respectively connected to its AVCC2 pin, AVCC3 pin, AVCC4 pin, grounding capacitor C1_16, grounding capacitor C2_16, grounding capacitor C3_16, grounding capacitor C4_16 and 5V voltage, the REGCAP1 pin of the AD7606 chip is connected to the grounding capacitor C10_16, and the REGCAP2 pin of the AD7606 chip is connected to the grounding capacitor C11_16. _16, the REFIN / REFOUT pins of the AD7606 chip are connected to the ground capacitor C12_16, the ground capacitor C16_16 and the ground capacitor C17_16 respectively, the REFCAPA pin and the REFCAPB pin of the AD7606 chip are connected to the ground capacitor C18_16, the REFGND1 pin to the REFGND2 pin, the V1GND pin to the V8GND pin, the AGND1 pin to the AGND6 pin, the DB0 pin to the DB6 pin, the DB9 pin to the DB The 15 pins are all grounded, the RANGE pin of the AD7606 chip is connected to the 8th pin of the resistor RN1_16, the CONVSTA pin and the CONVSTB pin of the AD7606 chip are both connected to the 7th pin of the resistor RN1_16, the RESET pin of the AD7606 chip is connected to the 6th pin of the resistor RN1_16, the RD pin of the AD7606 chip is connected to the 5th pin of the resistor RN1_16, the CS pin of the AD7606 chip is connected to the 8th pin of the resistor RN2_16, and the BU pin of the AD7606 chip is connected to the The SY pin is connected to the 7th pin of the resistor RN2_16, the DB7 pin of the AD7606 chip is connected to the 6th pin of the resistor RN2_16, the DB8 pin of the AD7606 chip is connected to the 5th pin of the resistor RN2_16, the 1st to 4th pins of the resistor RN1_16 and the 1st to 4th pins of the resistor RN2_16 together constitute 8 I / O channels connected to the microprocessor, the OS0 pin, OS1 pin and OS2 pin of the AD7606 chip are all connected to the ground resistor R1_16, and the REF pin of the AD7606 chip is The SELECT pin is connected to one end of the resistor R2_16, the PAR / SER / BYTE_SEL pin of the AD7606 chip is connected to one end of the resistor R3_16, the / STBY pin of the AD7606 chip is connected to one end of the resistor R4_16, the other end of the resistor R2_16, the other end of the resistor R3_16 and the other end of R4_16 are all connected to the 3.3V voltage, and the VDRIVE pin of the AD7606 chip is respectively connected to the 3.3V voltage and the grounding capacitor C14_16.

[0007] Further, the Ethernet interface includes an Ethernet chip, the XI pin of the Ethernet chip is respectively connected to the grounding capacitor C23 and one end of the crystal oscillator, the XO pin of the Ethernet chip is respectively connected to the grounding capacitor C26 and the other end of the crystal oscillator, the CLK125_NDO / LED_MODE pin of the Ethernet chip is connected to one end of the resistor R4, the RX_CLK / PHYAD2 pin of the Ethernet chip is connected to the grounding resistor R6, the RX_DV / CLK125_EN pin of the Ethernet chip is connected to one end of the resistor R7, and the RXD3 / MODE3 pin of the Ethernet chip is connected to one end of the resistor R11. The RXD2 / MODE2 pin of the Ethernet chip is connected to one end of the resistor R12, the RXD1 / MODE1 pin of the Ethernet chip is connected to one end of the resistor R13, the RXD0 / MODE0 pin of the Ethernet chip is connected to one end of the resistor R14, the MDC pin of the Ethernet chip is connected to one end of the resistor R8, the MDIO pin of the Ethernet chip is connected to one end of the resistor R9, the INT_N / PME_N2 pin of the Ethernet chip is connected to one end of the resistor R10, the other end of the resistor R4, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8, and the other end of the resistor R9 are connected. One end of the resistor R10, the other end of the resistor R11, the other end of the resistor R12, the other end of the resistor R13 and the other end of the resistor R14 are all connected to a 3.3V voltage, the EP pin, VSS pin and NC pin of the Ethernet chip are all grounded, the ISET pin of the Ethernet chip is connected to the grounding resistor R15, the TXRXP_A pin of the Ethernet chip is respectively connected to its TXRXM_A pin, the P2 pin of the network cable holder and the P3 pin of the network cable holder, the TXRXP_B pin of the Ethernet chip is connected to the P4 pin of the network cable holder, and the TXRXM_B pin of the Ethernet chip is connected to the network cable. The P7 pin of the socket is connected, the TXRXP_C pin of the Ethernet chip is connected to the P5 pin of the network cable socket, the TXRXM_C pin of the Ethernet chip is connected to its TXRXP_D pin, the P6 pin of the network cable socket and the P8 pin of the network cable socket respectively, the TXRXM_D pin of the Ethernet chip is connected to the P9 pin of the network cable socket, the P10 pin, SHIELD0 pin and SHIELD1 pin of the network cable socket are all grounded, the LED1 / PHYAD0 / PME_N1 pin of the Ethernet chip is connected to one end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R2 is connected to 3.The other end of the resistor R3 is connected to the grounding capacitor C24 and the cathode of the yellow LED light-emitting diode in the network cable seat respectively, the LED2 / PHYAD1 pin of the Ethernet chip is connected to the grounding resistor R1 and one end of the resistor R5 respectively, the other end of the resistor R5 is connected to the grounding capacitor C25 and the cathode of the green LED light-emitting diode in the network cable seat respectively, the anode of the yellow LED light-emitting diode and the anode of the green LED light-emitting diode are both connected to the 3.3V voltage, the AVDDH pin of the Ethernet chip is connected to its NC pin, the grounding capacitor C10, the grounding capacitor C11, the grounding capacitor C12 and one end of the first inductor respectively, the first inductor The other end of the inductor is connected to the ground capacitor C9 and the 3.3V voltage respectively. The AVDDL_PLL pin of the Ethernet chip is connected to the ground capacitor C2, the ground capacitor C3, the ground capacitor C4 and one end of the second inductor respectively. The other end of the second inductor is connected to the ground capacitor C1 and the 1.2V voltage respectively. The AVDDL pin of the Ethernet chip is connected to the ground capacitor C6, the ground capacitor C7, the ground capacitor C8 and one end of the third inductor respectively. The other end of the third inductor is connected to the ground capacitor C5 and the 1.2V voltage respectively. The DVDDL pin of the Ethernet chip is connected to the 1.2V voltage, and the DVDDH pin of the Ethernet chip is connected to the 3.3V voltage. .

[0008] Furthermore, the voltage conversion module includes a power adapter and a step-down chip. The power adapter converts the 220V system power supply into a 5V voltage and powers the AD7606 chip in the peripheral hardware module. The step-down chip converts the 5V voltage into an adaptation voltage for different devices in the multi-channel data acquisition system.

[0009] Furthermore, the step-down chip includes a 3.3V step-down chip, a 1.8V step-down chip, a 1.2V step-down chip and a 1V step-down chip.

[0010] Furthermore, the 3.3V step-down chip provides power for the I / O channels of the microprocessor and the Ethernet chip.

[0011] Furthermore, the 1.8V step-down chip provides auxiliary voltage for the microprocessor.

[0012] Furthermore, the 1.2V step-down chip provides core voltage for the Ethernet chip.

[0013] Furthermore, a 1V step-down chip provides core voltage for the microprocessor.

[0014] Furthermore, the AVIN1 pin of the step-down chip is respectively connected to its PVIN2 pin, PVIN3 pin, EN pin, grounding capacitor C210 and 5V voltage, the SS / TR pin of the step-down chip is connected to the grounding capacitor C211, the DEF pin, TPAD pin, PGND1 pin, PGND2 pin, AGND3 pin and FSW pin of the step-down chip are all grounded, the FB pin of the step-down chip is respectively connected to one end of the resistor R153 and the grounding resistor R156, the PG pin of the step-down chip is connected to one end of the resistor R152, the VOS pin of the step-down chip is respectively connected to the other end of the resistor R152, the other end of the resistor R153, one end of the inductor L13, the grounding capacitor C206 and the grounding capacitor C207, and outputs an adaptation voltage, and the other end of the inductor L13 is respectively connected to the SW1 pin, SW2 pin and SW3 pin of the step-down chip.

[0015] The beneficial effects of the present invention are:

[0016] (1) The microprocessor in the present invention effectively utilizes the logic resources of the FPGA chip, greatly reducing the cost.

[0017] (2) The data acquisition system provided by the present invention has high integration and small size. It can be installed on the surface of a small-volume aircraft model in a wind tunnel experiment to accurately measure the pulsating pressure on the model surface, avoiding the interference caused by too long leads in the past.

[0018] (3) The present invention can not only be used for the measurement of microphone arrays, but can also be used for data collection of other weak signals in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a block diagram of a multi-channel data acquisition system of a microphone array provided by an embodiment of the present invention.

[0020] Figure 2 Shown is a circuit diagram of the AD7606 chip provided in an embodiment of the present invention.

[0021] Figure 3 Shown is a circuit diagram of an Ethernet chip provided by an embodiment of the present invention.

[0022] Figure 4 FIG. 1 is a schematic diagram of a voltage conversion solution for a multi-channel data acquisition system provided by an embodiment of the present invention.

[0023] Figure 5 Shown is a circuit diagram of a 1V step-down chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Now, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the embodiments shown and described in the accompanying drawings are only exemplary and are intended to explain the principles and spirit of the present invention, rather than to limit the scope of the present invention.

[0025] The embodiment of the present invention provides a multi-channel data acquisition system of a microphone array, such as Figure 1 As shown, it includes a peripheral hardware module, a microprocessor, an Ethernet interface, a host computer and a voltage conversion module. The peripheral hardware module, the microprocessor, the Ethernet interface and the host computer are connected in sequence. The host computer sends a control signal to the microprocessor through the Ethernet interface. The microprocessor drives the peripheral hardware module according to the control signal to collect the analog signal of the microphone array, and generates a digital signal through analog-to-digital conversion. The microprocessor asynchronously caches the digital signal and then uploads it to the host computer through the Ethernet interface for analysis and display. The voltage conversion module converts the system power supply into an adaptive voltage and then supplies power to the peripheral hardware module, the microprocessor and the Ethernet interface respectively.

[0026] like Figure 1 As shown, the working principle and process of the present invention are as follows: first, the power supply of the data acquisition system is stepped down into different levels to power different devices through the voltage conversion module. After the system is powered on, the host computer sends control instructions through the Ethernet interface, and the microprocessor receives the instruction information. Then, 16 AD7606s are driven at the same time to collect the analog signals of the microphone array input. After analog-to-digital conversion, the actual digital signal is output to the asynchronous FIFO buffer module in the microprocessor. The asynchronous FIFO buffer module is used because under the condition of crossing the clock domain, the Ethernet data is sent too fast, which will cause data loss. The asynchronous FIFO buffer module solves this problem very well. Finally, the data is sent to the host computer software through the Ethernet interface for parsing. In order to integrate all functional modules on a circuit board, all functional modules will be designed with chips with small package size and high integration when selecting.

[0027] In the embodiment of the present invention, the parameters considered include sampling rate, resolution, dynamic range, etc. The Nyquist sampling theorem points out that if the sampling frequency is greater than twice the highest frequency of the signal, the analog signal can be converted into a digital signal without distortion, and the original signal can be perfectly reconstructed from the sampled digital signal. Usually during design, a higher multiple is selected to achieve better results, usually 3-5 times. The dynamic range of chip acquisition depends on the number of bits. The number of chip bits is determined according to the dynamic range of the MEMS microphone used in the embodiment of the present invention. The frequency range of SPV0842LR5H-1 is 100Hz~10KHz, so the sampling rate of the analog-to-digital conversion chip must at least meet f s ≥20KHz. The dynamic range DR of the microphone is calculated as follows:

[0028] DR=AOP-94+SNR

[0029] Where AOP represents the acoustic overload point of the MEMS microphone, and SNR represents its signal-to-noise ratio.

[0030] The relationship between DR and the number of bits N of the ADC chip is as follows:

[0031] DR≤6.02N+1.76

[0032] By calculation, it can be obtained that N≥15. Finally, the embodiment of the present invention adopts the AD7606 chip with a bit number of 16. The chip supports a serial interface (and an optional parallel interface). Its serial interface has strong compatibility and is easy to integrate into various embedded systems, reducing the complexity of hardware connection. The chip can sample 8 channels synchronously, and all channels can sample signals at a rate of up to 200KSPS, meeting the high-speed acquisition of pulsating pressure.

[0033] The peripheral hardware module includes 16 AD7606 chips, each of which has the same structure. Figure 2As shown, the AVCC1 pin of the AD7606 chip is respectively connected to its AVCC2 pin, AVCC3 pin, AVCC4 pin, grounding capacitor C1_16, grounding capacitor C2_16, grounding capacitor C3_16, grounding capacitor C4_16 and 5V voltage, the REGCAP1 pin of the AD7606 chip is connected to the grounding capacitor C10_16, the REGCAP2 pin of the AD7606 chip is connected to the grounding capacitor C11_16, the REFIN / REFOUT pins of the AD7606 chip are respectively connected to the grounding capacitor C12_16, the grounding capacitor C16_16 and the grounding capacitor C17_16, the REFCAPA pin and the REFCAPB pin of the AD7606 chip are both connected to the grounding capacitor C18_16, the REFGND1 pin~REFGND2 pin, the V1GND pin~V8GND pin, AGND1 to AGND6, DB0 to DB6, and DB9 to DB15 are all grounded, the RANGE pin of the AD7606 chip is connected to the 8th pin of the resistor array RN1_16, the CONVSTA pin and CONVSTB pin of the AD7606 chip are both connected to the 7th pin of the resistor array RN1_16, the RESET pin of the AD7606 chip is connected to the 6th pin of the resistor array RN1_16, the RD pin of the AD7606 chip is connected to the 5th pin of the resistor array RN1_16, the CS pin of the AD7606 chip is connected to the 8th pin of the resistor array RN2_16, the BUSY pin of the AD7606 chip is connected to the 7th pin of the resistor array RN2_16, the DB7 pin of the AD7606 chip is connected to the 6th pin of the resistor array RN2_16, and the DB8 pin of the AD7606 chip is connected to the 5th pin of the resistor array RN2_16. In the embodiment of the present invention, resistor array RN1_16 and resistor array RN2_16 jointly play the role of isolating and protecting digital pins, pins 1 to 4 of resistor array RN1_16 and pins 1 to 4 of resistor array RN2_16 jointly constitute 8 I / O channels connected to the microprocessor, and the resistor arrays of 16 AD7606 chips jointly constitute 128 I / O channels. The OS0 pin, OS1 pin and OS2 pin of the AD7606 chip are all connected to the ground resistor R1_16, the REF SELECT pin of the AD7606 chip is connected to one end of the resistor R2_16, the PAR / SER / BYTE_SEL pin of the AD7606 chip is connected to one end of the resistor R3_16, the / STBY pin of the AD7606 chip is connected to one end of the resistor R4_16, the other end of the resistor R2_16, the other end of the resistor R3_16 and the other end of R4_16 are all connected to a 3.3V voltage, and the VDRIVE pin of the AD7606 chip is respectively connected to a 3.3V voltage and a ground capacitor C14_16.

[0034] In the embodiment of the present invention, the microprocessor is implemented by an FPGA chip. By comparing the commonly used main control chips on the market, the FPGA chip that is most suitable for this data acquisition system is selected. The number of I / Os of the ALINX series FPGA device can meet the system requirements, and it has many advantages such as high integration, low power consumption, and stable performance. It is suitable for implementing complex digital circuit designs. In summary, the embodiment of the present invention selects the XC7A35T chip of the Xilinx Artix-7 series as the main control chip of the data acquisition system. Compared with other FPGAs, it provides a higher degree of integration and has a relatively small package size.

[0035] In the embodiment of the present invention, the Ethernet interface uses the KSZ9031 Ethernet chip, which integrates complete Ethernet physical layer functions, reduces the need for external components, and helps to simplify the design and reduce the PCB area. When the chip transmission mode is gigabit, the clock frequency between the FPGA and it is set to 125MHZ, and the RGMII interface is used for transmission, which can perform data transmission on both the rising and falling edges of the clock, thereby improving the data transmission rate.

[0036] like Figure 3As shown, the XI pin of the Ethernet chip is connected to the grounding capacitor C23 and one end of the crystal oscillator respectively, the XO pin of the Ethernet chip is connected to the grounding capacitor C26 and the other end of the crystal oscillator respectively, the CLK125_NDO / LED_MODE pin of the Ethernet chip is connected to one end of the resistor R4, the RX_CLK / PHYAD2 pin of the Ethernet chip is connected to the grounding resistor R6, the RX_DV / CLK125_EN pin of the Ethernet chip is connected to one end of the resistor R7, the RXD3 / MODE3 pin of the Ethernet chip is connected to one end of the resistor R11, the RXD2 / MODE2 pin of the Ethernet chip is connected to one end of the resistor R12, and the RXD1 / MODE1 pin of the Ethernet chip is connected to One end of resistor R13 is connected, the RXD0 / MODE0 pin of the Ethernet chip is connected to one end of resistor R14, the MDC pin of the Ethernet chip is connected to one end of resistor R8, the MDIO pin of the Ethernet chip is connected to one end of resistor R9, the INT_N / PME_N2 pin of the Ethernet chip is connected to one end of resistor R10, the other end of resistor R4, the other end of resistor R6, the other end of resistor R7, the other end of resistor R8, the other end of resistor R9, the other end of resistor R10, the other end of resistor R11, the other end of resistor R12, the other end of resistor R13 and the other end of resistor R14 are all connected to 3.3V voltage, and the EP pin, VSS pin and NC pin of the Ethernet chip are all connected to The ISET pin of the Ethernet chip is connected to the ground resistor R15, the TXRXP_A pin of the Ethernet chip is respectively connected to its TXRXM_A pin, the P2 pin of the network cable seat and the P3 pin of the network cable seat, the TXRXP_B pin of the Ethernet chip is connected to the P4 pin of the network cable seat, the TXRXM_B pin of the Ethernet chip is connected to the P7 pin of the network cable seat, the TXRXP_C pin of the Ethernet chip is connected to the P5 pin of the network cable seat, the TXRXM_C pin of the Ethernet chip is respectively connected to its TXRXP_D pin, the P6 pin of the network cable seat and the P8 pin of the network cable seat, the TXRXM_D pin of the Ethernet chip is connected to the P9 pin of the network cable seat, and the P The 10 pin, SHIELD0 pin and SHIELD1 pin are all grounded, the LED1 / PHYAD0 / PME_N1 pin of the Ethernet chip is connected to one end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R2 is connected to the 3.3V voltage, the other end of the resistor R3 is connected to the grounded capacitor C24 and the cathode of the yellow LED in the network cable holder respectively, the LED2 / PHYAD1 pin of the Ethernet chip is connected to the grounded resistor R1 and one end of the resistor R5 respectively, the other end of the resistor R5 is connected to the grounded capacitor C25 and the cathode of the green LED in the network cable holder respectively, the anode of the yellow LED and the anode of the green LED are both connected to 3.3V.3V voltage is connected, the AVDDH pin of the Ethernet chip is respectively connected to its NC pin, grounding capacitor C10, grounding capacitor C11, grounding capacitor C12 and one end of the first inductor, the other end of the first inductor is respectively connected to grounding capacitor C9 and 3.3V voltage, the AVDDL_PLL pin of the Ethernet chip is respectively connected to grounding capacitor C2, grounding capacitor C3, grounding capacitor C4 and one end of the second inductor, the other end of the second inductor is respectively connected to grounding capacitor C1 and 1.2V voltage, the AVDDL pin of the Ethernet chip is respectively connected to grounding capacitor C6, grounding capacitor C7, grounding capacitor C8 and one end of the third inductor, the other end of the third inductor is respectively connected to grounding capacitor C5 and 1.2V voltage, the DVDDL pin of the Ethernet chip is connected to 1.2V voltage, and the DVDDH pin of the Ethernet chip is connected to 3.3V voltage. .

[0037] In the embodiment of the present invention, Figure 4 As shown, the voltage conversion module includes a power adapter and a step-down chip. The power adapter converts the 220V system power supply into a 5V voltage and powers the AD7606 chip in the peripheral hardware module. The step-down chip converts the 5V voltage into the adaptation voltage of different devices in the multi-channel data acquisition system.

[0038] like Figure 4 As shown in FIG. 1 , the step-down chip includes a 3.3V step-down chip, a 1.8V step-down chip, a 1.2V step-down chip, and a 1V step-down chip. The 3.3V step-down chip provides power for the I / O channel of the microprocessor and the Ethernet chip, the 1.8V step-down chip provides auxiliary voltage for the microprocessor, the 1.2V step-down chip provides core voltage for the Ethernet chip, and the 1V step-down chip provides core voltage for the microprocessor.

[0039] During the operation of the multi-channel data acquisition system, different levels of voltage need to be provided for different components, especially in high-precision applications, where higher requirements are placed on the accuracy and stability of the input voltage. Therefore, when designing the hardware circuit board, different buck conversion circuits must be designed, appropriate power supply voltage regulator chips must be selected, and voltage protection measures must be added to prevent damage to components caused by excessive input voltage. In the embodiment of the present invention, the buck chip TLV62130RGTR is selected because it has the characteristics of high efficiency, low loss and small package, and its simple external components can save PCB space.

[0040] like Figure 5As shown, the AVIN1 pin of the buck chip is respectively connected to its PVIN2 pin, PVIN3 pin, EN pin, grounding capacitor C210 and 5V voltage, the SS / TR pin of the buck chip is connected to the grounding capacitor C211, the DEF pin, TPAD pin, PGND1 pin, PGND2 pin, AGND3 pin and FSW pin of the buck chip are all grounded, the FB pin of the buck chip is respectively connected to one end of the resistor R153 and the grounding resistor R156, the PG pin of the buck chip is connected to one end of the resistor R152, the VOS pin of the buck chip is respectively connected to the other end of the resistor R152, the other end of the resistor R153, one end of the inductor L13, the grounding capacitor C206 and the grounding capacitor C207, and outputs an adaptation voltage, and the other end of the inductor L13 is respectively connected to the SW1 pin, SW2 pin and SW3 pin of the buck chip. In the embodiment of the present invention, by adjusting the resistance values ​​of the resistor R152 and the resistor R153, different levels of voltage can be output at the VOS pin of the buck chip, such as Figure 5 Shown is a schematic diagram of outputting 1V voltage.

[0041] In the embodiment of the present invention, the circuit board function diagram is designed according to the determined chip model, and finally the circuit board PCB is designed using the Altium Designer tool. In order to facilitate the routing of components on the PCB board, a PCB stacking design is adopted, and the circuit board is designed as a 6-layer board, which is divided into a TOP layer, a BOTTOM layer, a SIGNAL1 layer, a SIGNAL2 layer, a VCC layer, and a GND layer. The components are located in the TOP layer and the BOTTOM layer, and the power supply is located in the VCC layer.

[0042] The completed object was tested and verified. The size of the final circuit board was 18cm×12cm. To verify whether the function of the circuit board was normal, a Gigabit Ethernet data parsing and multi-channel synchronous acquisition program was designed based on LabVIEW. Then the acquisition board was connected to the PC, and a DC voltage source was used to output a 2V voltage. The waveform voltage value displayed by the host computer was between 1.993V-1.999V, proving that the acquisition card functioned normally.

[0043] Use the waveform tool to capture the waveform, and AD7606 starts collecting. One cycle is 456 units, each unit is 20ns, that is, 9120ns is required for AD7606 to collect signals. Because time and cycle are reciprocals of each other, the sampling frequency is 110KSPS. The designed multi-channel data acquisition system can realize real-time acquisition and transmission of high sampling frequency signals.

[0044] Using Dahua DH1766-2 high-precision adjustable DC power supply as voltage source, the commercial Smacq USB-1252A data acquisition system and the data acquisition system provided by the embodiment of the present invention are used to measure the 0-5V voltage. The sampling rate of the Smacq data acquisition system is set to 110KSPS. To ensure the accuracy of the experimental results, each experiment is repeated three times, and 100 groups of data are taken as the average value for comparison each time. It can be seen from Table 1 that the maximum difference between the measured values ​​of the data acquisition system of the embodiment of the present invention and the Smacq acquisition card is 0.0036V, and the minimum difference is 0.0001V. Compared with the Smacq acquisition card, the amplitude difference of the designed DAQ system is less than 0.18%, which meets the actual application requirements.

[0045] Table 1

[0046]

[0047] The basic idea of ​​the present invention is to use FPGA as the core control device of the data acquisition system, and use the AD7606 chip and Ethernet interface communication to complete the acquisition of the analog voltage signal output by the microphone array, thereby improving the speed and accuracy of the data acquisition system. The data acquisition system synchronously acquires the analog voltage signal through the analog-to-digital conversion chip, and the FPGA sends the acquired signal to the host computer through the Ethernet interface for real-time display. The system has the advantages of fast acquisition speed, high acquisition accuracy, integration, small size and low cost.

[0048] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A multi-channel data acquisition system of a microphone array, characterized in that: The system comprises a peripheral hardware module, a microprocessor, an Ethernet interface, a host computer and a voltage conversion module, wherein the peripheral hardware module, the microprocessor, the Ethernet interface and the host computer are connected in sequence, the host computer sends a control signal to the microprocessor through the Ethernet interface, the microprocessor drives the peripheral hardware module to collect analog signals of the microphone array according to the control signal, and generates digital signals through analog-to-digital conversion, the microprocessor asynchronously caches the digital signals and then uploads them to the host computer through the Ethernet interface for analysis and display, and the voltage conversion module converts the system power supply into an adaptive voltage and then supplies power to the peripheral hardware module, the microprocessor and the Ethernet interface respectively.

2. The multi-channel data acquisition system of microphone array according to claim 1, characterized in that: The peripheral hardware module includes 16 AD7606 chips, each of which has the same structure. The AVCC1 pin of the AD7606 chip is respectively connected to its AVCC2 pin, AVCC3 pin, AVCC4 pin, grounding capacitor C1_16, grounding capacitor C2_16, grounding capacitor C3_16, grounding capacitor C4_16 and 5V voltage, the REGCAP1 pin of the AD7606 chip is connected to the grounding capacitor C10_16, the REGCAP2 pin of the AD7606 chip is connected to the grounding capacitor C11_16 The REFIN / REFOUT pins of the AD7606 chip are connected to the ground capacitor C12_16, the ground capacitor C16_16 and the ground capacitor C17_16 respectively, the REFCAPA pin and the REFCAPB pin of the AD7606 chip are connected to the ground capacitor C18_16, and the REFGND1 pin to REFGND2 pin, V1GND pin to V8GND pin, AGND1 pin to AGND6 pin, DB0 pin to DB6 pin, DB9 pin to DB15 pin of the AD7606 chip are connected to the ground capacitor C18_16. The RANGE pin of the AD7606 chip is connected to the 8th pin of the resistor row RN1_16, the CONVSTA pin and the CONVSTB pin of the AD7606 chip are both connected to the 7th pin of the resistor row RN1_16, the RESET pin of the AD7606 chip is connected to the 6th pin of the resistor row RN1_16, the RD pin of the AD7606 chip is connected to the 5th pin of the resistor row RN1_16, the CS pin of the AD7606 chip is connected to the 8th pin of the resistor row RN2_16, and the BUSY pin of the AD7606 chip is connected to the 4th pin of the resistor row RN2_16. The pin is connected to the 7th pin of the resistor RN2_16, the DB7 pin of the AD7606 chip is connected to the 6th pin of the resistor RN2_16, the DB8 pin of the AD7606 chip is connected to the 5th pin of the resistor RN2_16, the 1st to 4th pins of the resistor RN1_16 and the 1st to 4th pins of the resistor RN2_16 together constitute 8 I / O channels connected to the microprocessor, the OS0 pin, OS1 pin and OS2 pin of the AD7606 chip are all connected to the ground resistor R1_16, the REF The SELECT pin is connected to one end of the resistor R2_16, the PAR / SER / BYTE_SEL pin of the AD7606 chip is connected to one end of the resistor R3_16, the / STBY pin of the AD7606 chip is connected to one end of the resistor R4_16, the other end of the resistor R2_16, the other end of the resistor R3_16 and the other end of R4_16 are all connected to a 3.3V voltage, and the VDRIVE pin of the AD7606 chip is respectively connected to a 3.3V voltage and a ground capacitor C14_16.

3. The multi-channel data acquisition system of microphone array according to claim 2, characterized in that: The Ethernet interface includes an Ethernet chip, wherein the XI pin of the Ethernet chip is respectively connected to a ground capacitor C23 and one end of a crystal oscillator, the XO pin of the Ethernet chip is respectively connected to a ground capacitor C26 and the other end of the crystal oscillator, the CLK125_NDO / LED_MODE pin of the Ethernet chip is connected to one end of a resistor R4, the RX_CLK / PHYAD2 pin of the Ethernet chip is connected to a ground resistor R6, the RX_DV / CLK125_EN pin of the Ethernet chip is connected to one end of a resistor R7, and the RXD3 / MODE3 pin of the Ethernet chip is connected to one end of a resistor R11. The RXD2 / MODE2 pin of the Ethernet chip is connected to one end of the resistor R12, the RXD1 / MODE1 pin of the Ethernet chip is connected to one end of the resistor R13, the RXD0 / MODE0 pin of the Ethernet chip is connected to one end of the resistor R14, the MDC pin of the Ethernet chip is connected to one end of the resistor R8, the MDIO pin of the Ethernet chip is connected to one end of the resistor R9, the INT_N / PME_N2 pin of the Ethernet chip is connected to one end of the resistor R10, the other end of the resistor R4, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8, and the other end of the resistor R9. The other end of the resistor R10, the other end of the resistor R11, the other end of the resistor R12, the other end of the resistor R13 and the other end of the resistor R14 are all connected to a 3.3V voltage, the EP pin, the VSS pin and the NC pin of the Ethernet chip are all grounded, the ISET pin of the Ethernet chip is connected to the grounding resistor R15, the TXRXP_A pin of the Ethernet chip is respectively connected to its TXRXM_A pin, the P2 pin of the network cable seat and the P3 pin of the network cable seat, the TXRXP_B pin of the Ethernet chip is connected to the P4 pin of the network cable seat, and the TXRXM_B pin of the Ethernet chip is connected to the network cable seat The P7 pin of the cable holder is connected, the TXRXP_C pin of the Ethernet chip is connected to the P5 pin of the cable holder, the TXRXM_C pin of the Ethernet chip is respectively connected to its TXRXP_D pin, the P6 pin of the cable holder and the P8 pin of the cable holder, the TXRXM_D pin of the Ethernet chip is connected to the P9 pin of the cable holder, the P10 pin, the SHIELD0 pin and the SHIELD1 pin of the cable holder are all grounded, the LED1 / PHYAD0 / PME_N1 pin of the Ethernet chip is respectively connected to one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected to 3.The 3.3V voltage is connected, the other end of the resistor R3 is respectively connected to the grounding capacitor C24 and the cathode of the yellow LED light emitting diode in the network cable seat, the LED2 / PHYAD1 pin of the Ethernet chip is respectively connected to the grounding resistor R1 and one end of the resistor R5, the other end of the resistor R5 is respectively connected to the grounding capacitor C25 and the cathode of the green LED light emitting diode in the network cable seat, the anode of the yellow LED light emitting diode and the anode of the green LED light emitting diode are both connected to the 3.3V voltage, the AVDDH pin of the Ethernet chip is respectively connected to its NC pin, the grounding capacitor C10, the grounding capacitor C11, the grounding capacitor C12 and one end of the first inductor, the first capacitor The other end of the inductor is connected to the ground capacitor C9 and the 3.3V voltage respectively, the AVDDL_PLL pin of the Ethernet chip is connected to the ground capacitor C2, the ground capacitor C3, the ground capacitor C4 and one end of the second inductor respectively, the other end of the second inductor is connected to the ground capacitor C1 and the 1.2V voltage respectively, the AVDDL pin of the Ethernet chip is connected to the ground capacitor C6, the ground capacitor C7, the ground capacitor C8 and one end of the third inductor respectively, the other end of the third inductor is connected to the ground capacitor C5 and the 1.2V voltage respectively, the DVDDL pin of the Ethernet chip is connected to the 1.2V voltage, and the DVDDH pin of the Ethernet chip is connected to the 3.3V voltage. .

4. The multi-channel data acquisition system of microphone array according to claim 3, characterized in that: The voltage conversion module includes a power adapter and a step-down chip. The power adapter converts the 220V system power into a 5V voltage and supplies power to the AD7606 chip in the peripheral hardware module. The step-down chip converts the 5V voltage into the adaptation voltage of different devices in the multi-channel data acquisition system.

5. The multi-channel data acquisition system of microphone array according to claim 4, characterized in that: The step-down chip includes a 3.3V step-down chip, a 1.8V step-down chip, a 1.2V step-down chip and a 1V step-down chip.

6. The multi-channel data acquisition system of microphone array according to claim 5, characterized in that: The 3.3V step-down chip supplies power to the I / O channels of the microprocessor and the Ethernet chip.

7. The multi-channel data acquisition system of microphone array according to claim 5, characterized in that: The 1.8V step-down chip provides auxiliary voltage for the microprocessor.

8. The multi-channel data acquisition system of microphone array according to claim 5, characterized in that: The 1.2V step-down chip provides a core voltage for the Ethernet chip.

9. The multi-channel data acquisition system of microphone array according to claim 5, characterized in that: The 1V step-down chip provides a core voltage for the microprocessor.

10. The multi-channel data acquisition system of microphone array according to claim 5, characterized in that: The AVIN1 pin of the buck chip is respectively connected to its PVIN2 pin, PVIN3 pin, EN pin, grounding capacitor C210 and 5V voltage, the SS / TR pin of the buck chip is connected to the grounding capacitor C211, the DEF pin, TPAD pin, PGND1 pin, PGND2 pin, AGND3 pin and FSW pin of the buck chip are all grounded, the FB pin of the buck chip is respectively connected to one end of the resistor R153 and the grounding resistor R156, the PG pin of the buck chip is connected to one end of the resistor R152, the VOS pin of the buck chip is respectively connected to the other end of the resistor R152, the other end of the resistor R153, one end of the inductor L13, the grounding capacitor C206 and the grounding capacitor C207, and outputs an adaptation voltage, and the other end of the inductor L13 is respectively connected to the SW1 pin, SW2 pin and SW3 pin of the buck chip.

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