Substrate integrated with passive device

Abstract

The invention provides a substrate integrated with a passive device, belongs to the technical field of mobile communication, and can solve the problem that an existing integrated passive device has a temperature drift effect. The substrate comprises a dielectric substrate, a first conductive layer and a temperature compensation layer. Wherein the dielectric substrate is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the dielectric substrate; the first conductive layer is arranged on the first surface of the dielectric substrate and at least comprises a first substrate of the capacitor and / or a first conductive structure of the inductor, and the temperature compensation layer is arranged on the first surface of the dielectric substrate and / or one side, far away from the dielectric substrate, of the first conductive layer. The temperature compensation layer is made of materials with negative temperature characteristics, such as silicon dioxide, aluminum oxide, diamond and the like, and when the characteristics of the dielectric materials are changed, the temperature compensation layer can perform compensation, so that the temperature drift effect of the device is inhibited, the performance consistency of the passive device during working is ensured, and the device can be conveniently applied to wider scenes.

Description

Technical Field

[0001] The present disclosure belongs to the field of mobile communication technology, and in particular relates to a substrate integrated with passive devices. Background Art

[0002] Integrated Product Development (IPD) technology is a technology that uses semiconductor process technology to manufacture passive components such as resistors, capacitors, and inductors and integrates them into one to prepare various electronic devices. This technology has a short R&D cycle and low product cost. The high-quality electronic devices prepared by IPD technology can be applied to radio frequency communication systems and wirelessly connected micro-electromechanical systems, etc.

[0003] However, the inventors have found that there are at least the following problems in the prior art: traditional IPD technology usually uses dielectric materials with positive temperature characteristics as substrate materials and dielectric layer materials for inductors and capacitors, such as glass, ceramics, etc. This material has a temperature drift effect, and its parameters will increase when the temperature rises, thereby affecting the performance of the entire device.

[0004] Based on the above problems, the inventors proposed a substrate with integrated passive devices and a temperature compensation layer, wherein the temperature compensation layer is arranged on a dielectric substrate and / or a dielectric layer, wherein the temperature compensation layer is composed of a material with negative temperature characteristics, such as silicon dioxide, aluminum oxide, diamond, etc. When the characteristics of the dielectric material change, the temperature compensation layer can compensate, thereby suppressing the temperature drift effect of the device and ensuring the consistency of the performance of the passive device when it is working, so that the device can be applied to a wider range of scenarios. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. In a first aspect, the present invention provides a substrate with integrated passive devices capable of suppressing temperature drift, comprising:

[0006] A dielectric substrate having a first surface and a second surface disposed opposite to each other along a thickness direction thereof;

[0007] A first conductive layer, disposed on a first surface of the dielectric substrate, the first conductive layer at least comprising a first substrate of a capacitor and / or a first conductive structure of an inductor;

[0008] The temperature compensation layer is arranged on the first surface of the dielectric substrate and / or on a side of the first conductive layer away from the dielectric substrate.

[0009] Preferably, the second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate;

[0010] When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the first electrode plate.

[0011] Preferably, the second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate;

[0012] When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the second electrode plate.

[0013] Preferably, the second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate;

[0014] When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the first electrode plate and between the dielectric layer and the second electrode plate.

[0015] Preferably, an orthographic projection of the temperature compensation layer on the dielectric substrate has no overlap with an orthographic projection of the first conductive structure on the dielectric substrate.

[0016] Preferably, it further comprises a first insulating layer and a first lead wire which are sequentially arranged on a side of the second electrode plate away from the dielectric substrate;

[0017] The first lead-out wiring is connected to the second electrode through a first via hole penetrating the first insulating layer.

[0018] Preferably, it further comprises a second insulating layer and a first connecting pad which are sequentially arranged on a side of the first lead-out wiring away from the dielectric substrate;

[0019] The first connection pad is connected to the first lead trace through a second via hole penetrating the second insulating layer.

[0020] Preferably, the second conductive structure of the inductor is arranged on the second surface of the dielectric substrate; the second conductive structure is connected to the first conductive structure via a third via hole penetrating the dielectric substrate;

[0021] The temperature compensation portion is disposed on the first surface of the dielectric substrate.

[0022] Preferably, it further comprises a first insulating layer and a second lead-out wiring which are sequentially arranged on a side of the first conductive structure away from the dielectric substrate;

[0023] The second lead-out wiring is connected to the first conductive structure through a fourth via hole penetrating the first insulating layer.

[0024] Preferably, it further comprises a second insulating layer and a second connecting pad which are sequentially arranged on a side of the second lead-out wiring away from the dielectric substrate;

[0025] The second connection pad is connected to the second lead trace through a fifth via hole penetrating the second insulating layer.

[0026] Preferably, the material of the temperature compensation layer includes a dielectric material having a negative temperature characteristic.

[0027] Preferably, the material of the dielectric substrate includes any one of glass, silicon, ceramic and the like.

[0028] Preferably, the material of the dielectric layer of the capacitor includes silicon nitride.

[0029] In a second aspect, the present disclosure provides an electronic device comprising the above-mentioned substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 For existing substrates prepared by integrated product development technology;

[0031] Figure 2a It is a structural schematic diagram of a substrate disclosed in the present invention;

[0032] Figure 2b for Figure 2a A deformation of the substrate in;

[0033] Figure 2c for Figure 2a Another deformation of the substrate in;

[0034] Figure 2d for Figure 2a Another deformation of the substrate in;

[0035] Figure 2e for Figure 2a Another deformation of the substrate in;

[0036] Figure 2f for Figure 2a Another deformation of the substrate in;

[0037] Figure 3a It is a structural schematic diagram of another substrate disclosed in the present invention;

[0038] Figure 3b for Figure 3a A deformation of the substrate in;

[0039] Figure 3c for Figure 3a Another deformation of the substrate in;

[0040] Figure 4a It is a structural schematic diagram of another substrate disclosed in the present invention;

[0041] Figure 4b for Figure 4a A deformation of the substrate in;

[0042] Figure 4c for Figure 4a Another deformation of the substrate in;

[0043] Figure 4d for Figure 4a Another deformation of the substrate in;

[0044] Figure 4e for Figure 4a Another deformation of the substrate in;

[0045] Figure 4f for Figure 4a Yet another variation of the substrate in FIG. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0049] Figure 1 For existing substrates prepared by integrated product development technology, such as Figure 1 As shown, the substrate includes: a dielectric substrate 1, which has a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and a first conductive layer, which is arranged on the first surface of the dielectric substrate 1. The first conductive layer includes a first plate 201 of a capacitor and a first conductive structure 301 of an inductor integrated on the substrate. Further, the dielectric layer 203 and the second plate 202 of the capacitor are arranged in sequence on the side of the first plate 201 away from the dielectric substrate 1, and the second conductive structure 302 of the inductor is arranged on the second surface of the dielectric substrate 1, and is connected to the first conductive structure 301 of the inductor through a third via 403 penetrating the dielectric substrate 1. A first insulating layer 501, a lead wiring layer, a second insulating layer 502 and a connecting pad are arranged in sequence on the side of the first conductive layer away from the dielectric substrate 1, and a third insulating layer is arranged on the side of the second conductive structure 302 away from the dielectric substrate 1. The lead wiring layer includes a first lead wiring 601 and a second lead wiring 602, and the connecting pad includes a first connecting pad 701 and a second connecting pad 702. The first lead-out trace 601 is connected to the second electrode plate 202 of the capacitor through the first via hole 401 penetrating the first insulating layer 501, the second lead-out trace 602 is connected to the first conductive structure 301 of the inductor through the fourth via hole 404 penetrating the first insulating layer 501, the first connection pad 701 is connected to the first lead-out trace 601 through the second via hole 402 penetrating the second insulating layer 502, and the second connection pad 702 is connected to the second lead-out trace 602 through the fifth via hole 405 penetrating the second insulating layer 502. Among them, the material of the dielectric substrate 1 is a dielectric material with positive temperature characteristics (PTC) such as glass and ceramic, and the material of the dielectric layer 203 of the capacitor is silicon nitride. When the temperature rises, the resistance of both will increase, thereby affecting the stability of the device performance.

[0050] Based on the above problems, an embodiment of the present disclosure provides a substrate integrated with passive devices, which includes: a dielectric substrate 1, a first conductive layer and a temperature compensation layer 8, wherein the temperature compensation layer 8 is arranged on the first surface of the dielectric substrate 1, and / or the first conductive layer is on a side away from the dielectric substrate 1. Dielectric substrate 1 In some examples, the passive devices integrated on the dielectric substrate 1 may include capacitors, resistors and inductors. The capacitor has a first electrode plate 201 and a second electrode plate 202 that are arranged opposite to each other, and the inductor has a first conductive structure 301 and a second conductive structure 302 that are arranged opposite to each other. The first conductive layer is arranged on the first surface of the dielectric substrate 1, and the first conductive layer at least includes the first substrate of the capacitor, and / or the first conductive structure 301 of the inductor. Temperature compensation layer 8 Dielectric substrate 1 Dielectric substrate 1

[0051] In some examples, the material constituting the dielectric substrate 1 includes, but is not limited to, glass, silicon, ceramic, germanium silicon, diamond, etc., the material constituting the dielectric layer 203 of the capacitor may include silicon nitride, ceramic, mica, etc., the material constituting the temperature compensation layer 8 may include oxides with negative temperature characteristics (NTC) such as silicon dioxide, aluminum oxide, zirconium dioxide, etc., and the material constituting each plate of the capacitor, each conductive structure of the inductor, the first lead wire 601 and the second lead wire 602 may include one or any of metals such as aluminum, copper, titanium, chromium, nickel, etc. The setting of the temperature compensation layer 8 can perform temperature compensation on the dielectric substrate 1 and the dielectric layer 203 to ensure the stability of the device during operation.

[0052] For example, Figure 2a As shown, the first conductive layer includes a first electrode of the capacitor and a first conductive structure 301, and a dielectric layer 203, a second electrode plate 202, a first insulating layer 501, a first lead-out wiring 601 lead-out wiring layer, a second insulating layer 502 and a first connecting pad 701 are sequentially arranged on the side of the first electrode away from the dielectric substrate 1. Among them, the lead-out wiring layer includes a first lead-out wiring 601 and a second lead-out wiring 602, and the connecting pad includes a first connecting pad 701 and a second connecting pad 702. The first lead-out wiring 601 is connected to the second electrode plate 202 of the capacitor through a first via 401 penetrating the first insulating layer 501, and the first connecting pad 701 is connected to the first lead-out wiring 601 through a second via 402 penetrating the second insulating layer 502. The second lead-out trace 602 is connected to the first conductive structure 301 through the fourth via 404 penetrating the first insulating layer 501, and the second connection pad 702 is connected to the second lead-out trace 602 through the fifth via 405 penetrating the second insulating layer 502. It should be understood that the first conductive structure 301 in this embodiment is equivalent to a resistor.

[0053] Optionally, in this embodiment, the temperature compensation layer 8 may be disposed between the dielectric layer 203 and the first electrode plate 201 and between the dielectric layer 203 and the second electrode plate 202, such as Figure 2a Alternatively, the temperature compensation layer 8 is disposed separately between the dielectric layer 203 and the first electrode plate 201, as shown in FIG. Figure 2b Alternatively, the temperature compensation layer 8 is disposed separately between the dielectric layer 203 and the second electrode plate 202, as shown in FIG. Figure 2c Alternatively, the temperature compensation layer 8 is disposed separately between the first conductive layer and the first surface of the dielectric substrate 1, as shown in Figure 2d Alternatively, a temperature compensation layer 8 is disposed between the dielectric layer 203 and the first electrode 201, between the dielectric layer 203 and the second electrode 202, and between the first conductive layer and the first surface of the dielectric substrate 1. Figure 2eAs shown. It can be understood that, compared with a substrate with only one temperature compensation layer 8, a substrate with multiple temperature compensation layers 8 can compensate multiple components at the same time, has a better temperature compensation effect, and the temperature drift coefficient of the entire passive device is higher. However, the increase in the number of layers also increases the contact area of ​​the medium, causing more contact problems and increasing the process difficulty. In actual use, it can be selected according to needs.

[0054] Specifically, the dielectric layer 203 of the capacitor and the orthographic projection of the temperature compensation layer 8 on the dielectric substrate 1 at least partially overlap. That is, the temperature compensation layer 8 can be set to cover the entire dielectric layer of the first surface of the dielectric substrate 1, or the dielectric layer can be patterned, which can also achieve the effect of suppressing temperature drift, such as Figure 2f shown.

[0055] In another exemplary embodiment, the first conductive layer of the substrate includes a first conductive structure 301 of the inductor, and the temperature compensation layer 8 is disposed on the first surface and the second surface of the dielectric substrate 1, such as Figure 3a Alternatively, the temperature compensation layer 8 is only disposed on the first surface of the dielectric substrate 1, as shown in Figure 3b Alternatively, the temperature compensation layer 8 is only arranged on the second surface of the dielectric substrate 1, as shown in Figure 3c As shown. On the side of the first conductive structure 301 away from the dielectric substrate 1, the first insulating layer 501, the second lead-out wiring 602, the second insulating layer 502 and the second connecting pad 702 are sequentially arranged. The second lead-out wiring 602 is connected to the first conductive structure 301 through the fourth via 404 penetrating the first insulating layer 501, and the second connecting pad 702 is connected to the second lead-out wiring 602 through the fifth via 405 penetrating the second insulating layer 502. Correspondingly, the second conductive structure 302 of the inductor is arranged on the second surface of the dielectric substrate 1, and the second conductive structure 302 is connected to the first conductive structure 301 through the third via 403 penetrating the dielectric substrate 1. On the side of the second conductive structure 302 away from the dielectric substrate 1, the third insulating layer, the third lead-out wiring 603, the fourth insulating layer and the third connecting pad are arranged in sequence. The third lead-out trace 603 is connected to the second conductive structure 302 through the sixth via 406 penetrating the third insulating layer, and the third connection pad 703 is connected to the third lead-out trace 603 through the seventh via 407 penetrating the fourth insulating layer. In this embodiment, the dielectric substrate 1 is used as the magnetic core of the inductor, so the temperature compensation layer 8 is arranged on the first surface and / or the second surface of the dielectric substrate 1 to compensate for the dielectric substrate 1, thereby effectively suppressing the temperature drift, improving the stability of the inductor operation, and improving the consistency of the device operation.

[0056] In another exemplary embodiment, the first conductive layer includes a first conductive structure 301 of an inductor and a first plate 201 of a capacitor. The second plate 202 of the capacitor is disposed on a side of the first substrate away from the dielectric substrate 1, the dielectric layer 203 of the capacitor is sandwiched between the first plate 201 and the second plate 202, the second conductive structure 302 of the inductor is disposed on the second surface of the dielectric substrate 1, and is connected to the first conductive structure 301 of the inductor through a third via 403 penetrating the dielectric substrate 1. The orthographic projection of the dielectric layer 203 on the dielectric substrate 1 and the orthographic projection of the first conductive structure 301 of the inductor on the dielectric substrate 1 may have overlapping parts, or the two may not overlap at all. A first insulating layer 501 is disposed on a side of the second plate 202 away from the dielectric substrate 1 to isolate adjacent components. A lead-out wiring layer, a second insulating layer 502, and a connection pad layer are sequentially disposed on a side of the first insulating layer 501 away from the dielectric substrate 1. The lead-out wiring layer includes a first lead-out wiring 601 and a second lead-out wiring 602. The first lead-out wiring 601 is connected to the second electrode plate 202 of the capacitor through a first via hole 401 penetrating the first insulating layer 501. The second lead-out wiring 602 is connected to the first conductive structure 301 of the inductor through a fourth via hole 404 penetrating the first insulating layer 501. The connection pad layer includes a first connection pad 701 and a second connection pad 702. The first connection pad 701 is connected to the first lead-out wiring 601 through a second via hole 402 penetrating the second insulating layer 502. The second connection pad 702 is connected to the second lead-out wiring 602 through a fifth via hole 405 penetrating the second insulating layer 502.

[0057] Optionally, the temperature compensation layer 8 in this embodiment is disposed on the first surface of the dielectric substrate 1, and / or between the first plate 201 of the capacitor and the dielectric layer 203, and / or between the second plate 202 of the capacitor and the dielectric layer 203. For example, Figure 4a As shown, the temperature compensation layer 8 is arranged between the dielectric layer 203 and the first electrode plate 201, between the dielectric layer 203 and the second electrode plate 202, and between the first conductive layer and the dielectric substrate 1; Figure 4b As shown, the temperature compensation layer 8 is arranged between the first conductive layer and the dielectric substrate 1; Figure 4c As shown, the temperature compensation layer 8 is arranged between the dielectric layer 203 and the first electrode plate 201 and between the dielectric layer 203 and the second electrode plate 202; Figure 4d As shown, the temperature compensation layer 8 is disposed between the dielectric layer 203 and the second electrode plate 202; Figure 4eAs shown, the temperature compensation layer 8 is disposed between the dielectric layer 203 and the first electrode plate 201. In addition, the orthographic projection of the portion of the temperature compensation layer 8 for compensating the capacitor on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the dielectric layer of the capacitor on the dielectric substrate 1, and the orthographic projection of the temperature compensation layer 8 on the dielectric substrate 1 and the orthographic projection of the dielectric layer 203 on the dielectric substrate 1 may not overlap with the orthographic projection of the first conductive structure 301 of the inductor on the dielectric substrate 1, as shown in FIG. Figure 4f Such a configuration can compensate the dielectric layer and dielectric substrate 1 of the capacitor through the temperature compensation layer 8, suppress the temperature drift effect of the device, and ensure the stability and consistency of the device operation.

[0058] In a second aspect, an embodiment of the present disclosure provides an electronic device, which includes the substrate in any of the above embodiments.

[0059] In some examples, the electronic device further includes a processor module, a communication module, a power module, a drive module, a sensor module, a display module, an input module, an output module, etc. Among them, the processor module is used to control the operation and action of each component and respond to the command of the input device, the communication module is used to establish a communication connection between different modules, the power module is used to provide a stable voltage, the drive module is used to control the electric or electromagnetic drive of each device, and the common ones are stepper motor drive module, DC motor drive module, relay, etc., the sensor module is used to sense the environment and object information and feed it back to the processor, usually including temperature sensor, photoelectric sensor, sound sensor, etc., the display module is used to display the system operation status, operation results and other information, and the common display modules are LCD, LED, OLED, etc., the input module is used to receive the user's control instructions, such as buttons, touch screens, etc., and the output module is used to output instructions.

[0060] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A substrate integrated with passive devices, comprising: A dielectric substrate having a first surface and a second surface disposed opposite to each other along a thickness direction thereof; A first conductive layer, disposed on a first surface of the dielectric substrate, the first conductive layer at least comprising a first plate of a capacitor and / or a first conductive structure of an inductor; The temperature compensation layer is arranged on the first surface of the dielectric substrate and / or on a side of the first conductive layer away from the dielectric substrate.

2. The substrate according to claim 1, wherein The second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate; When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the first electrode plate.

3. The substrate according to claim 1, wherein The second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate; When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the second electrode plate.

4. The substrate according to claim 1, wherein The second electrode plate of the capacitor is located on a side of the first electrode plate away from the dielectric substrate, and a dielectric layer is provided between the first electrode plate and the second electrode plate; When the temperature compensation layer is located on a side of the first conductive layer away from the dielectric substrate, the temperature compensation layer is located between the dielectric layer and the first electrode plate and between the dielectric layer and the second electrode plate.

5. The substrate according to any one of claims 2 to 4, wherein The orthographic projection of the temperature compensation layer on the dielectric substrate has no overlap with the orthographic projection of the first conductive structure on the dielectric substrate.

6. The substrate according to any one of claims 2 to 4, wherein It also includes a first insulating layer and a first lead wire which are sequentially arranged on a side of the second electrode plate away from the dielectric substrate; The first lead-out wiring is connected to the second electrode through a first via hole penetrating the first insulating layer.

7. The substrate according to claim 6, wherein It also includes a second insulating layer and a first connecting pad which are sequentially arranged on a side of the first lead-out wiring away from the dielectric substrate; The first connection pad is connected to the first lead trace through a second via hole penetrating the second insulating layer.

8. The substrate according to claim 1, wherein The second conductive structure of the inductor is disposed on the second surface of the dielectric substrate; the second conductive structure is connected to the first conductive structure via a third via hole penetrating the dielectric substrate; The temperature compensation portion is disposed on the first surface of the dielectric substrate.

9. The substrate according to claim 8, wherein It also includes a first insulating layer and a second lead-out wiring which are sequentially arranged on a side of the first conductive structure away from the dielectric substrate; The second lead-out wiring is connected to the first conductive structure through a fourth via hole penetrating the first insulating layer.

10. The substrate according to claim 9, wherein It also includes a second insulating layer and a second connecting pad which are sequentially arranged on a side of the second lead-out wiring away from the dielectric substrate; The second connection pad is connected to the second lead trace through a fifth via hole penetrating the second insulating layer.

11. The substrate according to claim 1, wherein The material of the temperature compensation layer includes a dielectric material having a negative temperature characteristic.

12. The substrate according to claim 1, wherein The material of the dielectric substrate includes any one of glass, silicon, ceramic and the like.

13. The substrate according to claim 2, wherein The material of the dielectric layer of the capacitor includes silicon nitride.

14. An electronic device comprising the substrate according to any one of claims 1 to 13.

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