Memory and method of manufacturing the same, electronic device

Abstract

The application relates to a memory and a preparation method thereof and an electronic device. The memory comprises a substrate, a plurality of first word lines extending along a first direction perpendicular to the substrate, a plurality of storage units, the storage unit comprising a first gate insulating layer surrounding an outer sidewall of the first word line, a plurality of bit lines extending along a third direction parallel to the substrate and being spaced apart along a second direction, the second direction and the third direction intersecting and both being perpendicular to the first direction, a plurality of reference signal lines extending along the first direction, the storage unit further comprising a second gate insulating layer covering an outer sidewall of the reference signal line, the first gate insulating layer and the second gate insulating layer both comprising ferroelectric material, and a plurality of second word lines located on a side of the second gate insulating layer away from the reference signal line, the second word lines extending along the first direction. The memory provided by the application can increase the storage density.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a memory, a preparation method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of a device is increasingly reduced, and the types and number of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. However, the storage density of the memory in the related art is still low. SUMMARY

[0004] Therefore, it is necessary to provide a memory, a preparation method thereof, and an electronic device to solve the problem of low storage density of the memory in the related art.

[0005] To achieve the above object, in a first aspect, the present application provides a memory, comprising:

[0006] a substrate;

[0007] a plurality of first word lines extending along a first direction perpendicular to the substrate;

[0008] a plurality of storage units, the storage units comprising a first gate insulating layer surrounding an outer wall of the first word line;

[0009] a plurality of bit lines extending along a third direction parallel to the substrate and spaced apart along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction;

[0010] a plurality of reference signal lines extending along the first direction; the storage units further comprise a second gate insulating layer covering an outer wall of the reference signal line; the first gate insulating layer and the second gate insulating layer both comprise ferroelectric material;

[0011] a plurality of second word lines located on a side of the second gate insulating layer away from the reference signal line, the second word lines extending along the first direction.

[0012] The memory includes a substrate, a plurality of first word lines, a plurality of memory cells, a plurality of bit lines, a plurality of reference signal lines, and a plurality of second word lines. The plurality of first word lines extend along a first direction perpendicular to the substrate. The memory cell includes a first gate insulating layer surrounding an outer wall of the first word line. The plurality of bit lines extend along a third direction parallel to the substrate and are spaced apart along a second direction. The second direction and the third direction intersect and are both perpendicular to the first direction. The plurality of reference signal lines extend along the first direction. The memory cell further includes a second gate insulating layer covering an outer wall of the reference signal line. The first gate insulating layer and the second gate insulating layer both include ferroelectric material. The plurality of second word lines are located on a side of the second gate insulating layer away from the reference signal line and extend along the first direction. Since the material of the gate insulating layer is ferroelectric material, no additional capacitor needs to be formed, thereby effectively improving the storage density of the memory and realizing high-density storage. In addition, the memory cell is a double-gate ferroelectric field effect transistor, which can store at least 1.5 bits of data, thereby further improving the storage density relative to the case in the related art in which one memory cell can only store 1 bit of data. In addition, the memory in the embodiment can be stacked into multiple layers along the third direction perpendicular to the substrate, and each layer of the memory array can further include a plurality of arrayed memory cells, thereby realizing a 3D stacked memory and further improving the storage density.

[0013] In some embodiments, a side wall portion of the first gate insulating layer in contact with the bit line serves as a bit line contact area of each memory cell, and a side wall portion of the first gate insulating layer in contact with the reference signal line serves as a reference signal line contact area of each memory cell. The bit line contact areas of a plurality of memory cells sharing the same first word line are spaced apart along the first direction.

[0014] In some embodiments, the second word line, the reference signal line, and the bit line of the memory cell are spaced apart along the second direction.

[0015] In some embodiments, the memory further includes a semiconductor layer connected to the bit line and located between the reference signal line and the second gate insulating layer covering an outer wall of the reference signal line, and between the bit line and the second gate insulating layer covering an outer wall of the bit line.

[0016] In some embodiments, the reference signal line is grounded and connected to the semiconductor layer.

[0017] In some embodiments, the semiconductor layer at least partially surrounds the first word line, and the first gate insulating layer is between the first word line and the semiconductor layer. The second word line is on a side of the semiconductor layer away from the first word line, and the second gate insulating layer is between the second word line and the semiconductor layer.

[0018] In some embodiments, the first gate insulating layer and the second gate insulating layer comprise different materials.

[0019] In some embodiments, among two storage units belonging to the same row and arranged adjacent to each other, two reference signal lines corresponding to the two storage units are connected, and the two storage units are connected to two first word lines between the two reference signal lines. The two storage units share the same second word line, and the second word line is between the two reference signal lines.

[0020] In some embodiments, the plurality of storage units are stacked into multiple layers along the first direction, and the memory further comprises:

[0021] A plurality of first isolation walls sequentially penetrate the spacing regions between the storage units in each layer along the first direction; wherein the plurality of storage units spaced along the first direction are in contact with the same first isolation wall.

[0022] In some embodiments, the reference signal line further comprises a plurality of extensions on a side away from the first word line, and each extension on the same reference signal line is spaced along the first direction; and the second gate insulating layer surrounds the outer sidewall of each extension.

[0023] In some embodiments, the memory further comprises a plurality of conductive layers, and each conductive layer is between each second word line and the second gate insulating layer.

[0024] In some embodiments, the ferroelectric material comprises ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0025] In some embodiments, the memory further comprises a plurality of second isolation walls, and the second isolation walls sequentially penetrate each layer of the storage units along the first direction and extend along the second direction, and are between two adjacent bit lines.

[0026] In some embodiments, the memory further comprises a dielectric layer, and the bit line is between two adjacent layers of the dielectric layer. The semiconductor layer and the second gate insulating layer are sequentially arranged between the bit line and the dielectric layer.

[0027] In a second aspect, the present application also provides an electronic device comprising the memory as in any one of the preceding embodiments.

[0028] In the above embodiments, the electronic device includes the memory as described above, and high-density and large-capacity data storage can be achieved.

[0029] In a third aspect, the present application provides a method for preparing a memory, the method comprising:

[0030] providing a substrate;

[0031] forming a stack structure on the substrate, the stack structure comprising conductive layers and dielectric layers alternately stacked;

[0032] forming a plurality of first trenches in the stack structure, side walls of the first trenches exposing end surfaces of the conductive layers and the dielectric layers alternately stacked;

[0033] performing lateral etching on the conductive layers exposed in the first trenches to form a plurality of second trenches, the second trenches extending along a second direction parallel to the substrate;

[0034] forming a plurality of third trenches in the stack structure;

[0035] forming a second gate insulating layer, a semiconductor layer and a bit line in the second trench, the second gate insulating layer covering an outer sidewall of the bit line, the semiconductor layer being located between the second gate insulating layer and the bit line;

[0036] forming a first gate insulating layer, a first word line and a reference signal line in each of the third trenches;

[0037] forming a plurality of second word lines in the stack structure, each of the second word lines extending along the first direction and being located on a side of the second gate insulating layer away from the reference signal line.

[0038] The preparation method of the memory includes: forming a stack structure on the substrate, the stack structure including conductive layers and dielectric layers alternately stacked; forming a plurality of first grooves in the stack structure, the side walls of the first grooves exposing end surfaces of the conductive layers and the dielectric layers alternately stacked; performing lateral etching on the conductive layers exposed in the first grooves to form a plurality of second grooves, the second grooves extending along a second direction parallel to the substrate; forming a plurality of third grooves in the stack structure; forming a second gate insulating layer, a semiconductor layer and a bit line in the second grooves correspondingly, the second gate insulating layer covering the outer side walls of the bit line, and the semiconductor layer being located between the second gate insulating layer and the bit line; forming a first gate insulating layer, a first word line and a reference signal line in each of the third grooves; and forming a plurality of second word lines in the stack structure, each of the second word lines extending along the first direction and being located on a side of the second gate insulating layer away from the reference signal line. Since the material of the gate insulating layer is a ferroelectric material, a capacitor does not need to be additionally formed, so that the storage density of the memory can be effectively improved, and a high-density storage can be realized. In addition, each of the storage units is a double-gate ferroelectric field effect transistor, which can store at least 1.5 bits of data, so that the storage density can be further improved compared with the case that one storage unit can only store 1 bit of data in the related art. In addition, the memory in the embodiment can be stacked into multiple layers along a third direction Z perpendicular to the substrate, and each layer of the memory array can further include a plurality of storage units arranged in an array, so that a 3D stacked memory can be realized, and the storage density can be further improved.

[0039] In some embodiments, the side wall part of the first gate insulating layer in contact with the bit line serves as a bit line contact area of each of the storage units, and the side wall part of the first gate insulating layer in contact with the reference signal line serves as a reference signal line contact area of each of the storage units; the bit line contact areas of a plurality of the storage units sharing the same first word line are arranged at intervals along the first direction.

[0040] In some embodiments, each of the reference signal lines is connected to the reference signal line contact area of the storage unit; the second gate insulating layer further covers the outer side wall of the reference signal line, and the part of the second gate insulating layer in contact with the conductive layer away from the outer side wall of the reference signal line serves as a second word line contact area of each of the storage units.

[0041] In some embodiments, the forming of the second gate insulating layer, the semiconductor layer and the bit line in the second groove includes:

[0042] The inner walls of the first grooves, the inner walls of the second grooves and the inner walls of the third grooves form the second gate insulating layer distributed continuously;

[0043] forming the semiconductor layer on the second gate insulating layer;

[0044] forming a conductive material layer in the first trench and in the second trench;

[0045] removing the conductive material layer in the first trench, and the conductive material layer in the second trench is reserved as the bit line. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0047] Figure 1 a schematic diagram of polarization of ferroelectric dielectric under the action of electric field in an embodiment;

[0048] Figure 2 a structural schematic diagram of ferroelectric field effect transistor in an embodiment;

[0049] Figure 3 a corresponding diagram of polarization direction of two ferroelectric dielectrics and stored data in a ferroelectric field effect transistor in an embodiment;

[0050] Figure 4 a curve diagram of gate voltage and drain current of a ferroelectric field effect transistor in an embodiment;

[0051] Figure 5 a circuit diagram of a basic memory cell of a memory in an embodiment;

[0052] Figure 6 a top view of a memory in an embodiment;

[0053] Figure 7 a cross-sectional view of a memory in an embodiment; Figure 6 a cross-sectional view in A-A' direction;

[0054] Figure 8 a cross-sectional view of a memory in an embodiment; Figure 7 a top cross-sectional view in C-C' direction;

[0055] Figure 9 a cross-sectional view of a memory in an embodiment; Figure 6 a cross-sectional view in B-B' direction;

[0056] Figure 10 a flow chart of a preparation method of a memory in an embodiment;

[0057] Figure 11 Top view of the structure obtained in step S102 of the method for manufacturing a memory provided in one embodiment;

[0058] Figure 12 Top view of the structure obtained in step S104 of the method for manufacturing a memory provided in one embodiment; Figure 11 Cross-sectional view in the A-A' direction;

[0059] Figure 13 Top view of the structure obtained in step S105 of the method for manufacturing a memory provided in one embodiment;

[0060] Figure 14 Top view of the structure obtained in step S106 of the method for manufacturing a memory provided in one embodiment; Figure 13 Cross-sectional view in the A-A' direction;

[0061] Figure 15 Top view of the structure obtained in step S1062 of the method for manufacturing a memory provided in one embodiment;

[0062] Figure 16 Top view of the structure obtained in step S1063 of the method for manufacturing a memory provided in one embodiment; Figure 15 Cross-sectional view in the A-A' direction;

[0063] Figure 17 Top view of the structure obtained in step S1063a of the method for manufacturing a memory provided in one embodiment; Figure 15 Cross-sectional view in the A-A' direction;

[0064] Figure 18 Flowchart of the steps of step S106 of the method for manufacturing a memory provided in one embodiment;

[0065] Figure 19 Top view of the structure obtained in step S1062 of the method for manufacturing a memory provided in one embodiment;

[0066] Figure 20 Top view of the structure obtained in step S1063 of the method for manufacturing a memory provided in one embodiment; Figure 19 Cross-sectional view in the A-A' direction;

[0067] Figure 21 Flowchart of the steps of step S1063a of the method for manufacturing a memory provided in one embodiment;

[0068] Figure 22 Top view of the structure obtained in step S1063a of the method for manufacturing a memory provided in one embodiment;

[0069] Figure 23 Top view of the structure obtained in step S1063 of the method for manufacturing a memory provided in one embodiment; Figure 22 Cross-sectional view in the A-A' direction;

[0070] Figure 24A top view of the structure obtained in step S1063c in the method for manufacturing a memory provided in an embodiment;

[0071] Figure 25 A top view of the structure obtained in step S1063c in the method for manufacturing a memory provided in an embodiment; Figure 24 A cross-sectional view in the A-A' direction;

[0072] Figure 26 A top view of the structure obtained in step S1063e in the method for manufacturing a memory provided in an embodiment;

[0073] Figure 27 A top view of the structure obtained in step S1063e in the method for manufacturing a memory provided in an embodiment; Figure 26 A cross-sectional view in the A-A' direction;

[0074] Figure 28 A top view of the structure obtained in step S1064 in the method for manufacturing a memory provided in an embodiment;

[0075] Figure 29 A top view of the structure obtained in step S1064 in the method for manufacturing a memory provided in an embodiment; Figure 28 A cross-sectional view in the A-A' direction;

[0076] Figure 30 A flowchart of the steps in step S107 in the method for manufacturing a memory provided in an embodiment;

[0077] Figure 31 A top view of the structure obtained in step S1071 in the method for manufacturing a memory provided in an embodiment;

[0078] Figure 32 A top view of the structure obtained in step S1071 in the method for manufacturing a memory provided in an embodiment; Figure 30 A cross-sectional view in the A-A' direction;

[0079] Figure 33 A top view of the structure obtained in step S1072 in the method for manufacturing a memory provided in an embodiment;

[0080] Figure 34 A top view of the structure obtained in step S1072 in the method for manufacturing a memory provided in an embodiment; Figure 33 A cross-sectional view in the A-A' direction;

[0081] Figure 35 A top view of the structure obtained in step S1073 in the method for manufacturing a memory provided in an embodiment;

[0082] Figure 36 A top view of the structure obtained in step S1073 in the method for manufacturing a memory provided in an embodiment; Figure 33 A cross-sectional view in the A-A' direction.

[0083] Explanation of reference signs: 100 - channel layer, 110 - first ferroelectric layer, 120 - first gate structure, 130 - second ferroelectric layer, 140 - second gate structure, 150 - first doped region, 160 - second doped region, 200 - ferroelectric field effect transistor, 310 - dielectric layer, 320 - conductive layer, 330 - second isolation wall, 400 - substrate, 610 - first trench, 620 - second trench, 630 - third trench, 10 - second gate insulating layer, 20 - semiconductor layer, 30 - first sacrificial layer, 40 - second sacrificial layer, 50 - conductive layer, 510 - bit line, 60 - third sacrificial layer, 70 - first gate insulating layer, 710 - first isolation wall, 80 - first word line, 90 - reference signal line, 11 - second word line. DETAILED DESCRIPTION

[0084] For the purposes of this application, reference will be made to the accompanying drawings in which embodiments of the application are illustrated. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0086] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0087] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0088] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0089] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implant formed by a continuous process will not have sharp or discrete boundaries. Thus, the regions illustrated in the figures are schematic and not drawn to scale. As used herein, the term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations and / or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art.

[0090] Ferroelectric memory is a kind of non-volatile memory, which uses the ferroelectric effect of ferroelectric dielectric to realize the storage of data and its non-volatility. The ferroelectric effect refers to that when a certain electric field is applied to the ferroelectric dielectric, the central atoms of the ferroelectric dielectric move under the action of the electric field and reach a stable state; when the electric field is removed from the ferroelectric dielectric, the central atoms remain at the original position.

[0091] Figure 1 A schematic diagram of the polarization of the ferroelectric dielectric under the action of the electric field is as follows: Figure 1As shown, ferroelectric dielectrics exhibit polarization hysteresis and possess two distinct polarization directions, which can correspond to the storage of a single bit of data. Specifically, when an electric field is applied to a ferroelectric dielectric, the central atoms of the ferroelectric dielectric move within the crystal along the direction of the electric field and reside in a low-energy state. When the electric field is reversed and applied to the ferroelectric dielectric, the central atoms of the ferroelectric dielectric move within the crystal along the direction of the reversed electric field and reside in another low-energy state. The movement of a large number of central atoms within the crystal forms ferroelectric domains, which, under the influence of the electric field, generate polarization charges.

[0092] In traditional memory technology, a basic storage cell typically consists of a capacitor and a field-effect transistor, with a layer of crystalline ferroelectric dielectric deposited between the two electrode plates of the capacitor. However, traditional memory technologies have low storage density.

[0093] like Figure 2 As shown, in designing a basic memory cell, this application forms a ferroelectric field-effect transistor with dual gates by forming two gate insulating layers made of ferroelectric dielectrics on the upper and lower surfaces of a channel layer. This transistor simultaneously performs the functions of selecting the memory cell and storing the capacitor, thus constituting a basic memory cell of the memory provided by this application.

[0094] To facilitate understanding of the function of simultaneously selecting memory cells and memory capacitors, Figure 2 The following explanation uses a dual-gate ferroelectric field-effect transistor formed on the upper and lower surfaces of the channel layer as an example. Figure 2 As shown, a first ferroelectric layer 110 and a first gate structure 120 are sequentially formed on the upper surface of the channel layer 100. A second ferroelectric layer 130 and a second gate structure 140 are sequentially formed on the lower surface of the channel layer 100, with the channel layer 100 serving as the semiconductor layer of the transistor. Subsequently, a first doped region 150 and a second doped region 160 are formed on the exposed surface of the channel layer 100 to serve as the source and drain regions of the ferroelectric field-effect transistor, respectively, thus constituting a complete dual-gate ferroelectric field-effect transistor.

[0095] Figure 3 This is a diagram showing the correspondence between the polarization directions of the two ferroelectric dielectric layers in a dual-gate ferroelectric field-effect transistor and the data they represent, as shown below. Figure 3As shown, assuming that neither the upper ferroelectric dielectric nor the lower dielectric has undergone electric field reversal, it can represent data "00"; assuming that both the upper ferroelectric dielectric and the lower dielectric have undergone electric field reversal, it can represent data "11"; assuming that the upper ferroelectric dielectric has not undergone electric field reversal and the lower dielectric has undergone electric field reversal, it can represent data "01". (Similarly, assuming that the upper ferroelectric dielectric has undergone electric field reversal and the lower dielectric has not undergone electric field reversal, it can represent data "10"). In addition, since the naming of the upper dielectric and the lower dielectric can be flexibly interchanged in actual application scenarios, the case where one layer of ferroelectric dielectric has undergone electric field reversal and the other layer of ferroelectric dielectric has not undergone electric field reversal can represent data "01 / 10". When the electric field is removed, the center atoms of the two layers of ferroelectric dielectric are both in a low-energy state, so that the positions of the center atoms remain unchanged, so that the stored data will not be lost even in the case of power failure, and thus non-volatility of the stored data can be achieved.

[0096] By using such a ferroelectric dielectric as a gate insulating layer, one gate of the dual-gate ferroelectric field effect transistor will exhibit two channel current (I th ) - gate voltage (V GS ) curves with varying threshold voltages (V D ), that is, one gate has two states for representing data "1" and "0", and the two states can be obtained by applying a large enough positive voltage or a large enough negative voltage to one gate of the dual-gate ferroelectric field effect transistor. Therefore, as shown, the data information stored in the dual-gate ferroelectric field effect transistor can be read by the intermediate voltage V r (corresponding to the dashed line in the figure), and at least three states (i.e., at least 1.5 bits of data can be stored) can be achieved by one dual-gate transistor. That is, for a basic storage unit of the memory designed in the present application, it can store at least 1.5 bits of data. Figure 4

[0097] Figure 5 A circuit diagram corresponding to a basic storage unit of the memory provided in the present application is shown in FIG. 2. As shown, the first gate structure of the ferroelectric field effect transistor 200 is connected with the first word line WL1, the second gate structure of the ferroelectric field effect transistor 200 is connected with the second word line WL2, the drain of the ferroelectric field effect transistor 200 is connected with the bit line BL, and the source of the ferroelectric field effect transistor 200 is grounded. Alternatively, the first gate structure of the ferroelectric field effect transistor 200 is connected with the first word line WL1, the second gate structure of the ferroelectric field effect transistor 200 is connected with the second word line WL2, the source of the ferroelectric field effect transistor 200 is connected with the bit line BL, and the drain of the ferroelectric field effect transistor 200 is grounded. Figure 5

[0098] ​​The data writing process can be completed by applying appropriate voltages on the first word line WL1, the second word line WL2 and the bit line BL corresponding to the storage unit, so that the first ferroelectric layer and the second ferroelectric layer have the same or different polarization directions. When reading the data stored in the storage unit, only appropriate intermediate voltages V R intermediate voltages V

[0099] In order to realize the memory composed of multiple storage units in physical structure, the application provides a memory. Figure 6 The top view of the memory in the application is shown in Figure 7 The cross-sectional structure schematic diagram of the memory in the application along the direction of A-A' is shown in Figure 6 The cross-sectional structure schematic diagram of the memory in the application along the direction of C-C' is shown in Figure 8 The cross-sectional structure schematic diagram of the memory in the application along the direction of B-B' is shown in Figure 7 The cross-sectional structure schematic diagram of the memory in the application along the direction of C-C' is shown in Figure 9 The cross-sectional structure schematic diagram of the memory in the application along the direction of B-B' is shown in Figure 6 The cross-sectional structure schematic diagram of the memory in the application along the direction of B-B' is shown in Figures 6-9 The memory includes a substrate 400, a plurality of first word lines 80, a plurality of storage units, a plurality of bit lines 510, a plurality of reference signal lines 90 and a plurality of second word lines 11. The plurality of first word lines 80 extends along the first direction perpendicular to the substrate 400. The storage unit includes a first gate insulating layer 70 surrounding the outer wall of the first word line 80. The plurality of bit lines 510 extends along the third direction parallel to the substrate 400 and is spaced along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction. The plurality of reference signal lines 90 extends along the first direction, and the storage unit further includes a second gate insulating layer 10 covering the outer wall of the reference signal line 90 and the outer wall of the bit line 510; the first gate insulating layer 70 and the second gate insulating layer 10 both include ferroelectric material. The plurality of second word lines 11 is located on the side of the second gate insulating layer 10 away from the reference signal line 90, and the second word line 11 extends along the first direction.

[0100] As shown in Figures 6-9 , wherein the first direction can be the X direction, the second direction can be the Y direction, and the third direction can be the Z direction. In addition, in order to facilitate the understanding of the scheme, Figure 6 the dashed box in the application can be regarded as a storage unit, and the semiconductor layer 20 included in the storage unit of the memory provided in the application can be regarded as the channel layer as shown in Figure 2 , the first gate insulating layer 70 can be regarded as the first ferroelectric layer as shown in Figure 2 , and the second gate insulating layer 10 can be regarded as the second ferroelectric layer as shown in Figure 2The second ferroelectric layer is shown. Optionally, the first direction and the second direction are intersected, preferably perpendicular to each other.

[0101] In one implementation, in combination Figures 6-9 In one implementation, in combination In another implementation, in combination

[0102] In another implementation, in combination Figures 6-9 In another implementation, in combination In another implementation, in combination

[0103] In another implementation, in combination Figures 6-9The plurality of memory cells are also spaced along the first direction X and the second direction Y, and the plurality of memory cells are stacked along the first direction X to form a plurality of layers of memory cells, and each layer of memory cells includes a plurality of memory cells spaced along the third direction Z. The plurality of first word lines 80, the plurality of second word lines 11, the plurality of bit lines 510, and the plurality of reference signal lines 90 are arranged in a manner similar to the two implementation manners described above.

[0104] For example, the first word lines 80, the second word lines 11, and the reference signal lines 90 are arranged on the same surface of the vertical substrate 400, the first direction X and the second direction Y are parallel to the surface, and the third direction Z is perpendicular to the surface.

[0105] Optionally, a ground layer can also be arranged in the substrate 400, and each reference signal line 90 is connected to the ground layer, and the potentials of the reference signal lines 90 can be kept consistent.

[0106] The memory includes the substrate 400, the plurality of first word lines 80, the plurality of memory cells, the plurality of bit lines 510, the plurality of reference signal lines 90, and the plurality of second word lines 11. The plurality of first word lines 80 extends along the first direction of the vertical substrate 400. The memory cell includes a first gate insulating layer 70 surrounding the outer sidewall of the first word line 80. The plurality of bit lines 510 extends along the third direction parallel to the substrate 400 and is spaced along the second direction; the second direction and the third direction intersect and are both perpendicular to the first direction. The plurality of reference signal lines 90 extends along the first direction, and the memory cell further includes a second gate insulating layer 10 covering the outer sidewall of the reference signal line 90 and the outer sidewall of the bit line 510, and the first gate insulating layer 70 and the second gate insulating layer 10 both include ferroelectric material. The plurality of second word lines 11 is located on the side of the second gate insulating layer 10 away from the reference signal line 90, and the second word line 11 extends along the first direction. Since the material of the gate insulating layer is ferroelectric material, no additional capacitor needs to be formed, thereby effectively improving the storage density of the memory and realizing high-density storage. In addition, the memory cell is a double-gate ferroelectric field effect transistor, which can store at least 1.5 bits of data, thereby further improving the storage density compared to the case in the related art where one memory cell can only store 1 bit of data. In addition, the memory in the embodiment can be stacked into multiple layers along the first direction X of the vertical substrate 400, and each layer of the memory array can further include a plurality of array-arranged memory cells, thereby realizing a 3D stacked memory and further improving the storage density.

[0107] In some embodiments, the sidewall part of the first gate insulating layer 70 in contact with the bit line 510 serves as a bit line contact area of each memory cell, the sidewall part in contact with the reference signal line 90 serves as a reference signal line contact area of each memory cell, and the bit line contact areas of the plurality of memory cells sharing the same first word line 80 are arranged along the first direction.

[0108] In some embodiments, as shown in Figures 6-9 The reference signal line 90 is also provided with a plurality of extensions away from one side of the first word line 80, and the extensions on the same reference signal line 90 are spaced along the first direction; the second gate insulating layer 10 surrounds the outer sidewall of each extension.

[0109] In some embodiments, the second word line 11, the reference signal line 90 and the bit line 510 of the memory cell are spaced along the second direction.

[0110] In some embodiments, the memory further comprises a semiconductor layer 20, which is connected to the bit line 510 and located between the reference signal line 90 and the second gate insulating layer 10 covering the outer sidewall of the reference signal line 90, and between the bit line 510 and the second gate insulating layer 10 covering the outer sidewall of the bit line 510.

[0111] Since the semiconductor layer 20 is located between the reference signal line 90 and the second gate insulating layer 10 covering the outer sidewall of the reference signal line 90, and between the bit line 510 and the second gate insulating layer 10 covering the outer sidewall of the bit line 510, the contact area between the semiconductor layer 20 and the second gate insulating layer 10 can be increased, so that the adhesion between them is greater, the structure is compact, and it is also beneficial to improve the storage density of the memory and realize a high-density memory structure.

[0112] In some embodiments, the reference signal line 90 is grounded, and the reference signal line 90 is connected to the semiconductor layer 20.

[0113] In some embodiments, the semiconductor layer 20 at least partially surrounds the first word line 80, and the first gate insulating layer 70 is between the first word line 80 and the semiconductor layer 20; the second word line 11 is located on the side of the semiconductor layer 20 away from the first word line 80, and the second gate insulating layer 10 is between the second word line 11 and the semiconductor layer 20.

[0114] In some embodiments, as shown in Figures 6-9 The plurality of memory cells are stacked into multiple layers along the first direction, and the memory further comprises a plurality of first isolation walls 710, which sequentially penetrate the spacing regions between the memory cells in each layer along the first direction, wherein the plurality of memory cells spaced along the first direction contact the same first isolation wall 710.

[0115] In the above embodiments, by providing the first isolation wall 710, insulation can be formed between many adjacent memory cells at the same time, thereby reducing the process steps and reducing the implementation cost.

[0116] In some embodiments, as shown in Figures 6-9As shown, the memory further includes a plurality of conductive layers 320, each conductive layer 320 being located between each second word line 11 and the second word line contact region.

[0117] The material of the conductive layer 320 can include polysilicon, monocrystalline silicon or a metal material, and the metal material can include copper, gold, titanium, silver, aluminum or the like, or a multi-layer metal composed of the above-mentioned metal materials, or a metal alloy, and the like, which are not limited in the present embodiment.

[0118] In some embodiments, the ferroelectric material includes ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0119] In some embodiments, as shown in FIG. 1B, the memory further includes a plurality of second isolation walls 330, each second isolation wall 330 extending through each layer of the memory unit along the first direction and extending along the second direction, and being located between two adjacent bit lines 510. Figures 6-9

[0120] In some embodiments, as shown in FIG. 1B, the memory further includes a plurality of second isolation walls 330, each second isolation wall 330 extending through each layer of the memory unit along the first direction and extending along the second direction, and being located between two adjacent bit lines 510. Figures 6-9

[0121] The material of the conductive layer 320 can include polysilicon, monocrystalline silicon or a metal material, and the metal material can include copper, gold, titanium, silver, aluminum or the like, or a multi-layer metal composed of the above-mentioned metal materials, or a metal alloy, and the like, which are not limited in the present embodiment.

[0122] Based on the same inventive concept, the present application further provides an electronic device, which can be a television, a mobile phone, a computer, a tablet, or the like, and the electronic device includes the memory as described above.

[0123] In the above embodiments, the electronic device includes the memory as described above, and can achieve high-density and large-capacity data storage.

[0124] Based on the same inventive concept, the present application further provides a preparation method of the memory, as shown in FIG. 1C, the preparation method includes the following steps. Figure 10

[0125] S101: providing a substrate.

[0126] ​​​The substrate material can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc., which are not limited in this embodiment.

[0127] S102: A stacked structure is formed on the substrate, the stacked structure including alternating conductive layers and dielectric layers.

[0128] The dielectric layer 310 can be made of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). The conductive layer 320 can be made of polycrystalline silicon, monocrystalline silicon, or a metal. Further, the metal can include metals such as copper, gold, titanium, silver, and aluminum, or multilayer metals composed of the aforementioned metals, or metal alloys, etc. This embodiment does not impose any limitations on these aspects.

[0129] like Figure 11 and Figure 12 As shown, a deposition process can be used to alternately deposit a conductive layer 320 and a dielectric layer 310 on a substrate 400 to ultimately form a stacked structure.

[0130] The deposition process may include, but is not limited to, one or more of the following: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD) coating of the dielectric layer 310. The specific deposition process used can be determined based on cost requirements and the materials of the conductive layer 320 and the dielectric layer 310; this embodiment does not impose any limitations on this.

[0131] In addition, to facilitate understanding of this solution, Figure 12It is to be understood that the number of layers of the conductive layer 320 and the dielectric layer 310 can be other suitable numbers in other suitable application scenarios, and the present embodiment is not limited thereto.

[0132] S103: Forming a plurality of first grooves in the stack structure, and the sidewalls of the first grooves expose the end faces of the conductive layers and the dielectric layers alternately stacked.

[0133] Optionally, the plurality of first grooves 610 can be formed in the stack structure by a photolithography and etching process. Further, a hard mask layer can be formed on the stack structure first, then a photoresist layer is formed on the hard mask layer, then part of the hard mask layer is removed by a photolithography and etching process to form a patterned hard mask layer, and finally the stack structure is etched based on the patterned hard mask layer to form the plurality of first grooves 610 in the stack structure.

[0134] S104: Lateral etching each layer of the conductive layer exposed in the first groove to form a plurality of second grooves, and the second grooves extend along a second direction parallel to the substrate.

[0135] As shown in Figure 13 and Figure 14 , wherein the first direction can be the X direction, the second direction can be the Y direction, and the third direction can be the Z direction.

[0136] Optionally, the second grooves 620 can be formed by etching each layer of the conductive layer 320 through the first grooves 610. The etching selectivity of the conductive layer 320 and the dielectric layer 310 is different, and the conductive layer 320 is selectively etched from the conductive layer 320 and the dielectric layer 310 exposed in the first grooves 610, thereby forming the second grooves 620.

[0137] Exemplarily, the removal process of removing the conductive layer 320 to form the second grooves 620 can include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).

[0138] Optionally, as shown in Figure 14 , during the formation of the second grooves 620, over-etching can also be performed to remove part of the substrate 400.

[0139] S105: Forming a plurality of third grooves in the stack structure.

[0140] As shown in Figures 15-16As shown, the plurality of third trenches 630 can be formed in the stack structure by using a lithography and etching process. Further, a hard mask layer can be formed on the stack structure first, then a photoresist layer is formed on the hard mask layer, then a part of the hard mask layer is removed by a lithography and etching process to form a patterned hard mask layer, and finally the stack structure is etched based on the patterned hard mask layer to form the plurality of third trenches 630 in the stack structure.

[0141] Further, in another embodiment of the preparation method of the memory provided in the present application, as shown in Figure 17 As shown, the positions of the third trenches 630 correspond to the positions of the second trenches 620 one by one, and the orthographic projection of each second trench 620 on the substrate 400 fully covers the orthographic projection of each third trench 630 on the substrate 400.

[0142] S106: corresponding second gate insulating layer, semiconductor layer and bit line are formed in the second trench, the second gate insulating layer covers the outer wall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line.

[0143] The material of the semiconductor layer 20 includes polycrystalline silicon, amorphous silicon, oxide material (for example, Indium Gallium Zinc Oxide (IGZO), IZO, ITO, zinc oxide and two-dimensional material (for example, graphene, molybdenum disulfide, etc.). The material of the second gate insulating layer 10 can be a ferroelectric material, which can include ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0144] The constituent material of the bit line 510 includes but is not limited to one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, and the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti) for example; the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0145] In some embodiments, as shown in Figure 18 The above step S106 includes:

[0146] S1061: a second gate insulating layer 10 is formed on the inner walls of the first trench 610, the second trench 620 and the third trench 630.

[0147] Optionally, the atomic layer deposition method can be used to form the second gate insulating layer 10 on the inner walls of the trenches.

[0148] S1062: Forming a semiconductor layer 20 on the second gate insulating layer 10.

[0149] Optionally, the semiconductor layer 20 can be formed on the second gate insulating layer 10 by atomic layer deposition.

[0150] As shown in Figure 19 and Figure 20 , the second gate insulating layer 10 is continuously distributed on the inner walls of the trenches, and the semiconductor layer 20 is also continuously distributed on the second gate insulating layer 10.

[0151] Optionally, in the process of forming the third trench 630, in order to ensure the integrity of the first trench 610 and the second trench 620, some trench filling material can also be filled first. After the third trench 630 is formed, before forming the second gate insulating layer 10, the semiconductor layer 20 and the bit line 510, the excess trench filling material is uniformly removed to form a structure as shown in Figure 16 . Then, as shown in Figure 19 , the second gate insulating layer 10 is formed continuously on the inner walls of the trenches.

[0152] S1063: Forming a conductive material layer 50 in the first trench 610 and the second trench 620.

[0153] In some embodiments, as shown in Figure 21 , the above step S1063 can include the following steps:

[0154] S1063a: Filling the first trench 610, the second trench 620 and the third trench 630 with a first sacrificial layer 30.

[0155] As shown in Figure 22 and Figure 23 , the first sacrificial layer 30 completely fills the inside of the trenches.

[0156] S1063b: Removing the first sacrificial layer 30 filled in the first trench 610 and the third trench 630, and removing the semiconductor layer 20 on the inner walls of the first trench 610 and the third trench 630.

[0157] S1063c: Filling the first trench 610 and the third trench 630 with a second sacrificial layer 40.

[0158] Optionally, the material of the second sacrificial layer 40 can be different from that of the first sacrificial layer 30.

[0159] As shown in Figure 24 and Figure 25 , the first sacrificial layer 30 completely fills the inside of the first trench 610 and the inside of the third trench 630.

[0160] S1063d: removing the second sacrificial layer 40 located in the first trench 610, and removing the first sacrificial layer 30 located in the second trench 620 close to the first trench 610.

[0161] Optionally, the second sacrificial layer 40 located in the first trench 610 can be removed first, and then the first sacrificial layer 30 located in the second trench 620 close to the first trench 610 can be removed by using the etching selectivity difference between the first sacrificial layer 30 filled in the second trench 620 and the semiconductor layer 20 of the sidewall of the second trench 620 and the second sacrificial layer 40 filled in the third trench 630, in a similar way to forming the second trench 620.

[0162] Exemplarily, the removing process of removing the first sacrificial layer 30 located in the second trench 620 close to the first trench 610 can include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).

[0163] S1063e: filling a conductive material layer 50 in the first trench 610 and the second trench 620 close to the first trench 610.

[0164] Figure 26 A top view of the structure obtained in step S1063e in the preparation method of the memory provided by an embodiment of the present application is shown in Figure 27 A cross-sectional structure schematic view in A-A' direction of the structure obtained in step S1063e in the preparation method of the memory provided by an embodiment of the present application is shown in Figure 26

[0165] S1064: removing the conductive material layer 50 and the semiconductor layer 20 located in the first trench 610, and retaining the conductive material layer 50 in the second trench 620 as the bit line 510.

[0166] As shown in Figure 28 and Figure 29 , the second gate insulating layer 10 covers the outer sidewall of the bit line 510, the semiconductor layer 20 is located between the second gate insulating layer 10 and the bit line 510, and the second gate insulating layer 10, the semiconductor layer 20, and the bit line 510 are sequentially arranged in a direction away from the inner wall of the second trench 620.

[0167] Optionally, as shown in Figure 29 , after removing the conductive material layer 50 and the semiconductor layer 20 located in the first trench 610, a third sacrificial layer 60 can also be formed to fill the first trench 610, so as to facilitate the subsequent process. The third sacrificial layer 60 can serve as the first isolation wall 710 after the memory is completed.

[0168] ​S107: Forming a first gate insulating layer 70, a first word line 80 and a reference signal line 90 in each third trench 630.

[0169] In some embodiments, as shown in FIG. 1 1, step S107 comprises: Figure 30

[0170] S1071: Filling a conductive material in the third trench 630 to form the reference signal line 90.

[0171] As shown in FIG. 12 and FIG. 13, the material of the reference signal line 90 can include but is not limited to one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (Ir02); the metal silicide includes tungsten silicide (WSi). Figure 31 Figure 32 As shown in FIG. 12 and FIG. 13, the material of the reference signal line 90 can include but is not limited to one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (Ir02); the metal silicide includes tungsten silicide (WSi).

[0172] S1072: Removing the second sacrificial layer 40 in the third trench 630.

[0173] As shown in FIG. 14 and FIG. 15, the structure obtained in step S1072 in the preparation method of the memory provided in an embodiment of the present application is a top view, Figure 33 Figure 34 As shown in FIG. 14 and FIG. 15, the structure obtained in step S1072 in the preparation method of the memory provided in an embodiment of the present application is a top view, Figure 33 is a sectional structure schematic diagram in A-A' direction of FIG. 14. Figure 34 is a sectional structure schematic diagram in A-A' direction of FIG. 14. Figure 33

[0174] S1073: Depositing a first gate insulating layer 70 and a first word line 80 in the third trench 630 in sequence.

[0175] As shown in FIG. 16 and FIG. 17, the structure obtained in step S1073 in the preparation method of the memory provided in an embodiment of the present application is a top view, Figure 35 Figure 36 As shown in FIG. 16 and FIG. 17, the structure obtained in step S1073 in the preparation method of the memory provided in an embodiment of the present application is a top view, Figure 35 is a sectional structure schematic diagram in A-A' direction of FIG. 16. Figure 36 is a sectional structure schematic diagram in A-A' direction of FIG. 16. Figure 35 Exemplarily, the material of the first gate insulating layer 70 can be a ferroelectric material, which can include ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

[0176] Optionally, the material of the first gate insulating layer 70 can be the same as the material of the second gate insulating layer 10, and the deposition process adopted by the first gate insulating layer 70 can also be the same as the deposition process adopted by the second gate insulating layer 10.

[0177] Optionally, the material of the first gate insulating layer 70 can be the same as the material of the second gate insulating layer 10, and the deposition process adopted by the first gate insulating layer 70 can also be the same as the deposition process adopted by the second gate insulating layer 10.​​​​​

[0178] Optionally, the first gate insulating layer 70 can be formed on the inner wall of each third groove 630 by atomic layer deposition.

[0179] The material of the first word line 80 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicide (WSi).

[0180] S108: forming a plurality of second word lines in the stack structure, each second word line extending along the first direction and being located on the side of the second gate insulating layer away from the reference signal line, as shown in FIG. 1C. Figures 6-9

[0181] In some embodiments, the sidewall part of the first gate insulating layer 70 in contact with the bit line 510 serves as the bit line contact area of each memory cell, and the sidewall part in contact with the reference signal line 90 serves as the reference signal line contact area of each memory cell. The bit line contact areas of the memory cells sharing the same first word line 80 are arranged at intervals along the first direction.

[0182] In some embodiments, each reference signal line 90 is connected with the reference signal line contact area of the memory cell; the second gate insulating layer 10 also covers the outer sidewall of the reference signal line 90, and the part of the second gate insulating layer 10 away from the outer sidewall of the reference signal line 90 and in contact with the conductive layer 320 serves as the second word line contact area of each memory cell.

[0183] Optionally, as shown in FIG. 1D, after the plurality of bit lines 510 and the plurality of reference signal lines 90 are formed, a second isolation wall 330 can be formed between each row of memory cells. Figure 30

[0184] Figure 6 A top view of the structure obtained in step S108 of the method for manufacturing a ferroelectric memory according to an embodiment of the present application is shown in FIG. 1E. Figure 7 A cross-sectional structure along the A-A' direction of FIG. 1E is shown in FIG. 1F. Figure 6 As shown in FIG. 1F, each second word line 11 extends along the first direction and is connected with the second gate insulating layer 10 of the memory cell through the conductive layer 320. Figure 6 Figure 7

[0185] ​​​​The preparation method of the memory includes the following steps: forming a stack structure on a substrate, the stack structure including conductive layers and dielectric layers alternately stacked; forming a plurality of first grooves in the stack structure, the side walls of the first grooves exposing end surfaces of the conductive layers and the dielectric layers alternately stacked; performing lateral etching on each layer of the conductive layers exposed in the first grooves to form a plurality of second grooves, the second grooves extending along a second direction parallel to the substrate; forming a plurality of third grooves in the stack structure; forming a second gate insulating layer, a semiconductor layer and a bit line in the second grooves correspondingly, the second gate insulating layer covering the outer side wall of the bit line, and the semiconductor layer being located between the second gate insulating layer and the bit line; forming a first gate insulating layer, a first word line and a reference signal line in each third groove; and forming a plurality of second word lines in the stack structure, each second word line extending along the first direction and being located on the side of the second gate insulating layer away from the reference signal line. Since the material of the gate insulating layer is a ferroelectric material, a capacitor does not need to be additionally formed, so that the storage density of the memory can be effectively improved, and high-density storage can be realized. In addition, each storage unit is a double-gate ferroelectric field effect transistor, which can store at least 1.5 bits of data, and the storage density can be further improved compared with the case that one storage unit can only store 1 bit of data in the related art. In addition, the memory in the embodiment can be stacked into multiple layers along the third direction Z perpendicular to the substrate 400, and each layer of the storage array can further include a plurality of storage units arranged in an array, so that a 3D stacked memory can be realized, and the storage density can be further improved.

[0186] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered as within the scope of the present disclosure.

[0187] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A memory, characterized in that, include: Substrate; Multiple first letter lines extend along a first direction perpendicular to the substrate; Multiple memory cells, each memory cell including a first gate insulating layer surrounding the outer wall of the first word line; Multiple bit lines extend along a third direction parallel to the substrate and are spaced apart along a second direction; the second direction and the third direction intersect and are both perpendicular to the first direction; Multiple reference signal lines extend along the first direction; the memory cell further includes a second gate insulating layer covering the outer wall of the reference signal lines; both the first gate insulating layer and the second gate insulating layer comprise ferroelectric materials. Multiple second word lines are located on the side of the second gate insulating layer away from the reference signal line, and the second word lines extend along the first direction.

2. The memory according to claim 1, characterized in that, The sidewall portion of the first gate insulating layer that contacts the bit line serves as the bit line contact area of ​​each memory cell, and the sidewall portion that contacts the reference signal line serves as the reference signal line contact area of ​​each memory cell. The bit line contact areas of multiple memory cells sharing the same first word line are arranged at intervals along the first direction.

3. The memory according to claim 1, characterized in that, The second word line, the reference signal line, and the bit line of the memory cell are arranged at intervals along the second direction.

4. The memory according to claim 1, characterized in that, The memory further includes a semiconductor layer connected to the bit line and located between the reference signal line and a second gate insulating layer covering the outer wall of the reference signal line, and between the bit line and the second gate insulating layer covering the outer wall of the bit line.

5. The memory according to claim 4, characterized in that, The reference signal line is grounded and connected to the semiconductor layer.

6. The memory according to claim 4, characterized in that, The semiconductor layer at least partially surrounds the first word line, and a first gate insulating layer is provided between the first word line and the semiconductor layer. The second word line is located on the side of the semiconductor layer away from the first word line, and a second gate insulating layer is provided between the second word line and the semiconductor layer.

7. The memory according to claim 1, characterized in that, The first gate insulating layer and the second gate insulating layer comprise different materials.

8. The memory according to claim 1, characterized in that, In two adjacent bit lines, two memory cells belonging to the same row are connected to two reference signal lines and two first word lines, which are located between the two bit lines. The two memory cells share the same second word line, which is located between the two reference signal lines.

9. The memory according to claim 1, characterized in that, The plurality of said storage cells are stacked in multiple layers along the first direction, and the memory further includes: Multiple first isolation walls sequentially penetrate the interval region between the storage cells in each layer along the first direction; wherein, multiple storage cells spaced apart along the first direction contact the same first isolation wall.

10. The memory according to claim 1, characterized in that, The reference signal line is further provided with a plurality of extensions on the side away from the first word line, and the extensions on the same reference signal line are spaced apart along the first direction; the second gate insulating layer surrounds the outer wall of each extension.

11. The memory according to claim 1, characterized in that, The memory also includes a plurality of conductive layers, each of which is located between each of the second word lines and the second gate insulating layer.

12. The memory according to claim 1, characterized in that, The ferroelectric material includes ferroelectric zirconium oxide or ferroelectric hafnium zirconium oxide.

13. The memory according to claim 1, characterized in that, The memory also includes a plurality of second isolation walls, which sequentially penetrate each layer of the memory cell along the first direction and extend along the second direction, and are located between two adjacent bit lines.

14. The memory according to claim 1, characterized in that, The memory further includes a dielectric layer, the bit line is located between two adjacent dielectric layers, and a semiconductor layer and a second gate insulating layer are sequentially disposed between the bit line and the dielectric layer.

15. An electronic device, characterized in that, The electronic device includes a memory as described in any one of claims 1-14.

16. A method for fabricating a memory, characterized in that, The method for fabricating the memory includes: Provide substrate; A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of conductive layers and dielectric layers; Multiple first trenches are formed within the stacked structure, and the sidewalls of the first trenches expose the end faces of the alternately stacked conductive and dielectric layers. Laterally etch each of the conductive layers exposed in the first trench to form a plurality of second trenches, the second trenches extending along a second direction parallel to the substrate; Multiple third trenches are formed within the stacked structure; A second gate insulating layer, a semiconductor layer, and a bit line are formed in the second trench. The second gate insulating layer covers the outer wall of the bit line, and the semiconductor layer is located between the second gate insulating layer and the bit line. A first gate insulating layer, a first word line, and a reference signal line are formed in each of the third trenches; Multiple second word lines are formed within the stacked structure, each second word line extending along a first direction and located on the side of the second gate insulating layer away from the reference signal line.

17. The method for fabricating a memory according to claim 16, characterized in that, The sidewall portion of the first gate insulating layer that contacts the bit line serves as the bit line contact area of ​​each memory cell, and the sidewall portion that contacts the reference signal line serves as the reference signal line contact area of ​​each memory cell. The bit line contact areas of multiple memory cells sharing the same first word line are arranged at intervals along the first direction.

18. The method for fabricating a memory according to claim 16, characterized in that, Each of the reference signal lines is connected to the reference signal line contact area of ​​the memory cell; the second gate insulating layer also covers the outer wall of the reference signal line, and the portion of the second gate insulating layer away from the outer wall of the reference signal line that contacts the conductive layer serves as the second word line contact area of ​​each of the memory cells.

19. The method for fabricating a memory according to claim 16, characterized in that, The formation of a second gate insulating layer, a semiconductor layer, and a bit line within the second trench includes: A second gate insulating layer is continuously distributed on the inner wall of the first trench, the inner wall of the second trench, and the inner wall of the third trench. The semiconductor layer is formed on the second gate insulating layer; A conductive material layer is formed in the first trench and the second trench; The conductive material layer located in the first trench is removed, and the remaining conductive material layer in the second trench is used as the bit line.

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