3D ferroelectric memory structure and method for reading out memory structure
By arranging metal layers with different work functions in the ferroelectric memory to form a 3D ferroelectric memory structure, the problems of destructive readout and high power consumption in FeRAM are solved, and non-destructive readout and high-density storage are realized.
Patent Information
- Application Number
- CN202411400567.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-20
- Filing Date
- 2024-10-09
- Publication Date
- 2025-04-22
AI Technical Summary
The existing ferroelectric random access memory (FeRAM) has destructive readout problems during the readout process, resulting in a reduced durability of the memory cell, high switching power and increased power consumption. At the same time, 3D stacking of memory cells is difficult to achieve.
A 3D ferroelectric memory structure is designed to form multiple capacitive memory cells by arranging metal layers with different work functions on both sides of the ferroelectric layer, and non-destructive reading is achieved by applying a small DC bias voltage or a zero bias voltage.
Non-destructive readout of memory cells is realized, power consumption is reduced, memory density is improved, and memory state can be read without switching the polarized state.
Smart Images
Figure CN119866016A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of capacitor-based ferroelectric memory. Specifically, the present disclosure provides a three-dimensional (3D) ferroelectric memory structure, a memory device including a plurality of 3D ferroelectric memory structures, and a method for reading out the 3D ferroelectric memory structure. Background Art
[0002] Ferroelectric random access memory (FeRAM) uses a ferroelectric memory structure with a ferroelectric layer to store information. FeRAM usually consists of a grid of memory cells, where each memory cell includes a ferroelectric capacitor and a select transistor (so-called 1T-1C device). The ferroelectric layer is thus arranged between the capacitor plates to form a ferroelectric capacitor.
[0003] In order to read out the current storage state of such a memory cell, the memory cell is forced into a known memory state, i.e. a specific net polarization of the ferroelectric layer (up or down). Based on the response of the memory cell, it can be inferred whether the memory state of the ferroelectric layer has been changed as a result. Thus, on average 50% of the time, the current memory state of the memory cell is overwritten during the readout and the memory cell needs to be reprogrammed thereafter. This is called destructive readout. Due to this destructive readout, the endurance of the memory cell, i.e. the total number of achievable write / erase cycles, is related to the number of read cycles. This usually leads to more demanding specifications. For example, a memory cell should withstand up to 1E13 write / erase cycles or more.
[0004] Furthermore, the switching power is determined by the polarization value of the ferroelectric layer, which can be quite high. Since the memory cell is switched in 50% of all read cycles, reading requires a high enough voltage to switch the memory cell to a known memory state and requires additional rewrite cycles, both of which increase power consumption.
[0005] Furthermore, the select transistors typically used for decoding of memory cells in a 1T-1C configuration enlarge the size of the memory cell and make it non-stackable, especially when using silicon transistors.
[0006] However, 3D stacking of memory cells is highly desirable as this can increase memory density without requiring aggressive scaling of lateral dimensions. So far, this approach has proven successful in the case of flash memory such as 3D NAND, but similar architectures for SCM and Computing-in-Memory (CiM) applications have not yet been established. In particular, in the field of SCM, no satisfactory solution has been found, as most concepts rely on resistive switching, which implies high current and power consumption. Summary of the invention
[0007] In view of the above, an object of the present disclosure is to provide an improved ferroelectric memory structure suitable for designing FeRAM, and an improved method for reading out the ferroelectric memory structure in a non-destructive manner. Another object is to provide a 3D (i.e., having stacked memory cells) ferroelectric memory structure. The overall object is to avoid the above-mentioned disadvantages.
[0008] These and other objects are achieved by the solutions provided in the independent claims. Advantageous implementations are described in the dependent claims.
[0009] A first aspect provides a 3D ferroelectric memory structure, comprising: a substrate; a layer stack arranged on the substrate, wherein the layer stack includes a plurality of dielectric layers and a plurality of first metal layers arranged alternately with each other along a first axis; a first ferroelectric layer extending through each layer of the stack; and a second metal layer extending through each layer of the stack adjacent to the first ferroelectric layer; wherein the first ferroelectric layer is combined with the plurality of first metal layers and the second metal layers to form a plurality of first capacitor memory cells; and wherein a first work function of the first metal layer is different from a second work function of the second metal layer.
[0010] A first aspect therefore provides a 3D (ie having stacked memory cells) ferroelectric memory structure which can increase the memory (cell) density of a memory device (eg FeRAM) comprising the 3D ferroelectric memory structure.
[0011] In addition, the 3D ferroelectric memory structure of the first aspect provides the following advantages: the memory cell can be read out in a non-destructive manner. Specifically, the different work functions of the first metal layer and the second metal layer lead to the asymmetry of the hysteresis loop of the ferroelectric layer, and in particular also lead to the asymmetry of the capacitance-voltage hysteresis. Due to this asymmetry of the capacitance-voltage hysteresis, even if no bias is applied to the ferroelectric layer, the capacitance and therefore the dielectric response of the 3D ferroelectric memory structure will be different depending on the current polarization state of the ferroelectric layer. This difference in capacitance (or dielectric response) can also be called a memory window.
[0012] Thus, even when no (or only a small) bias voltage is applied, the current polarization state of the ferroelectric layer can be detected by measuring the dielectric response (e.g., effective dielectric constant or capacitance) of the ferroelectric layer. Thus, the memory state of the memory structure can be read without having to "switch" the polarization of the ferroelectric layer (non-destructive readout (NDRO)), because even a small bias voltage can be lower than the voltage required to switch the ferroelectric layer.
[0013] It is noteworthy that each first metal layer, ferroelectric layer and second metal layer can together form a corresponding ferroelectric capacitor for realizing a first capacitance memory unit. The first metal layer and the second metal layer can thus form a capacitor plate of the ferroelectric capacitor. Considering one memory cell among all first capacitance memory cells, the corresponding first metal layer can completely surround the ferroelectric layer of the memory cell, while the ferroelectric layer surrounds the second metal layer. The ferroelectric layer and the second metal layer can have a cylindrical shape in this case and can be formed in a so-called memory hole passing through the stack. Alternatively, the first metal layer can be arranged on one side of the ferroelectric layer, and the second metal layer can be arranged on the other side of the ferroelectric layer along a second axis perpendicular to the first axis.
[0014] The fact that the first metal layer and the second metal layer have different work functions may mean that they include or are formed of materials (or material combinations) having different work functions. For example, the first metal layer may have a first work function and the second metal layer may have a second work function different from the first work function.
[0015] The substrate may be a silicon substrate, in particular it may be a p-doped silicon substrate. The stack may be deposited directly on the substrate. However, one or more further layers may be arranged between the substrate and the stack.
[0016] In one implementation, the 3D ferroelectric memory structure further includes: a second ferroelectric layer extending through the layers of the stack; and a third metal layer extending through the layers of the stack adjacent to the second ferroelectric layer; wherein the second ferroelectric layer is combined with the plurality of first metal layers and the third metal layer to form a plurality of second capacitor memory cells; and wherein the first work function of the first metal layer is different from the third work function of the third metal layer.
[0017] Therefore, additional memory cells can be processed in the same stack, which can increase memory density.
[0018] In one implementation, the 3D ferroelectric memory structure further includes a dielectric material extending through the layers of the stack and disposed between the second metal layer and the third metal layer.
[0019] According to the above implementation, a plurality of first capacitive memory cells and a plurality of second capacitive memory cells can be processed and arranged adjacently in a stack.The first and second ferroelectric layers, the second and third metal layers and the dielectric material can be adjacently formed in trenches previously formed in the layer stack.
[0020] In an implementation of the 3D ferroelectric memory structure, both the first ferroelectric layer and the second ferroelectric layer extend along a first axis or extend obliquely at opposite angles relative to the first axis.
[0021] Thus, the first ferroelectric layer and the second ferroelectric layer may be parallel to each other, but may also extend at an angle to each other.
[0022] In the implementation of the 3D ferroelectric memory structure, the first ferroelectric layer and the second ferroelectric layer can be electrically excited to two polarization states respectively; and each polarization state represents a respective memory state of the first or second capacitive memory cell.
[0023] The polarization states to which the ferroelectric layer can be electrically excited can be referred to as the "net polarization" of the electric dipoles in the ferroelectric layer. The two polarization states can be represented as "up" or "down" polarizations, with one polarization state representing "0" and the other polarization state representing "1", or vice versa.
[0024] In an implementation of the 3D ferroelectric memory structure, each first metal layer of the plurality of first metal layers is connected to a corresponding word line driver.
[0025] Thus, the first metal layers may function as word lines and / or each first metal layer may form at least a portion of a word line.
[0026] In the implementation of the 3D ferroelectric memory structure, each of the second metal layer and the third metal layer is connected to a corresponding sensing circuit.
[0027] Thus, the second and third metal layers may function as bit lines and / or each of these metal layers may form at least a portion of a bit line.
[0028] In the implementation of the 3D ferroelectric memory structure, each sensing circuit is formed in the substrate.
[0029] Therefore, a compact design of a 3D ferroelectric memory structure can be achieved.
[0030] In implementations of the 3D ferroelectric memory structure, the first work function differs from the second work function and / or the third work function by at least 0.3 eV.
[0031] In an implementation of a 3D ferroelectric memory structure, the first metal layer includes a different material or material combination than the second metal layer and / or the third metal layer.
[0032] In an implementation of a 3D ferroelectric memory structure, at least one of the first metal layer, the second metal layer, and the third metal layer includes any one of the following materials or material compositions: molybdenum (Mo); a composition comprising molybdenum and molybdenum oxide (MoOx); titanium nitride (TiN); a composition comprising ruthenium (Ru) and titanium nitride; or tungsten (W).
[0033] In an implementation of a 3D ferroelectric memory structure, the first ferroelectric layer includes hafnium zirconium oxide (HZO), such as lanthanum-doped HZO.
[0034] The first ferroelectric layer may additionally or alternatively include any other suitable ferroelectric material, such as hafnium oxide (HfO2) or lead zirconate titanate (PZT). The second ferroelectric layer may include HZO, for example lanthanum-doped HZO. The second ferroelectric layer may include the same material as the first ferroelectric layer.
[0035] In an implementation of the 3D ferroelectric memory structure, each of the first metal layer and the second metal layer is configured to apply a DC bias to the ferroelectric layer, wherein the DC bias is lower than a voltage required to change a current polarization state of the ferroelectric layer.
[0036] The DC bias may additionally increase the difference between the dielectric responses of the two polarization states (memory window) of the ferroelectric layer. However, the DC bias may be lower than the voltage required to switch the polarization state of the ferroelectric layer. Therefore, the memory state of the memory structure can still be read out in a non-destructive manner.
[0037] A second aspect provides a memory device comprising a plurality of 3D ferroelectric memory structures according to the first aspect or any implementation thereof, wherein the 3D ferroelectric memory structures are arranged in a vertical and horizontal array.
[0038] Each 3D ferroelectric structure can provide multiple memory cells of a memory device. The memory device can be a random access memory (RAM) device, such as FeRAM. In an example, the memory device can be a selector-free memory device, that is, the memory cells of the memory device do not include additional selection transistors for capacitors (that is, they are in a so-called 0T-1C configuration). This achieves the advantage that the memory cells can be more densely arranged and can be better stacked. In addition, (all) 3D ferroelectric memory structures can be compatible with the back end line (BEOL).
[0039] A third aspect provides a method for reading out a 3D ferroelectric memory structure, wherein the 3D ferroelectric memory structure comprises a layer stack arranged on a substrate, the layer stack comprising a plurality of dielectric layers and a plurality of first metal layers arranged alternately on top of each other along a first axis, a first ferroelectric layer extending through each layer of the stack, and
[0040] A second metal layer extends adjacent to the first ferroelectric layer through the layers of the stack, and the first ferroelectric layer is combined with the multiple first metal layers and the second metal layers to form a plurality of first capacitor memory cells, wherein the method includes: applying a DC bias to the first ferroelectric layer through one of the first metal layer and the second metal layer, wherein the DC bias is lower than a voltage required to change the current polarization state of the first ferroelectric layer; detecting the capacitance of the first ferroelectric layer under the bias; and correlating the detected capacitance to the current polarization state of the first ferroelectric layer.
[0041] The method of the third aspect achieves similar advantages as described above for the 3D ferroelectric memory structure of the first aspect, in particular, it achieves non-destructive readout of the memory cell.
[0042] Specifically, applying the bias voltage causes or increases the difference between the two polarization states of the ferroelectric layer. Under the bias voltage, the capacitance-voltage loop of the ferroelectric layer shows a larger gap (i.e., a larger memory window) between the capacitance values of the polarization states. The memory window can be used to read out the polarization state. However, since the bias voltage is still lower than the voltage required to change the current polarization state of the ferroelectric layer, the readout can be non-destructive for the current memory state. Here, the capacitance of the ferroelectric layer can refer to the capacitance of the capacitor memory cell formed using the ferroelectric layer and the corresponding metal layer.
[0043] In one implementation, the first metal layer and the second metal layer are formed of the same material or material combination.Thus, the effect of the bias voltage can be sufficient to cause a detectable difference in the dielectric response of the ferroelectric layer, the dielectric response being dependent on the polarization state of the ferroelectric layer that can be read out in a non-destructive manner.
[0044] In an implementation, the first metal layer and the second metal layer comprise different materials or material combinations. This achieves the advantage that the difference between the dielectric response of the two polarization states of the ferroelectric layer can be further enhanced to thereby increase the "memory window".
[0045] In one implementation, a first work function of the first metal layer is different from a second work function of the second metal layer.
[0046] This increases the memory window at small DC biases. In fact, a memory window can even exist at zero bias.
[0047] In an implementation of the method, the capacitance of the first ferroelectric layer is detected by applying an AC voltage signal to one side of the first ferroelectric layer and detecting a dielectric response of the first ferroelectric layer by the AC voltage signal on the other side of the first ferroelectric layer.
[0048] The dielectric response may include a displacement current generated after the displacement charge is accumulated due to the AC voltage signal. The AC voltage signal (e.g., a 30mV or 100mV or 500mV pulse) may be applied to one of the first metal layers, particularly the first metal layer connected to the word line, and may cause the accumulation of displacement charge in the first capacitive memory cell. The dielectric response may be detected on the bit line connected to the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The above aspects and implementations are explained in the following description of embodiments with respect to the accompanying drawings:
[0050] Figure 1A portion of a 3D ferroelectric memory structure according to the present disclosure is shown.
[0051] Figure 2 A first example of a 3D ferroelectric memory structure according to the present disclosure is shown.
[0052] Figure 3 A second example of a 3D ferroelectric memory structure according to the present disclosure is shown.
[0053] Figure 4 Shows Figure 3 Optional details of the 3D ferroelectric memory structure.
[0054] Figure 5 A flow chart of a method for reading out a 3D ferroelectric memory structure according to the present disclosure is shown.
[0055] Figure 6 A diagram showing measurements using a 3D ferroelectric memory structure according to the present disclosure is shown.
[0056] Figure 7 A schematic diagram of a memory device according to the present disclosure is shown. DETAILED DESCRIPTION
[0057] Figure 1 A portion of a 3D ferroelectric memory structure 10 according to the present disclosure is shown. The 3D ferroelectric memory structure 10 can be used to construct a memory device, such as FeRAM. The memory device can include one or more such 3D ferroelectric memory structures 10 and can be configured to store information in one or more memory cells provided by the design of the 3D ferroelectric memory 10.
[0058] The 3D ferroelectric memory structure 10 includes a substrate 11 (e.g., a silicon substrate) and a layer stack 14 disposed directly on (as shown in the figure) or above the substrate 11. The layer stack 14 includes a plurality of dielectric layers 13 and a plurality of first metal layers 14 that are alternately disposed on top of each other along a first axis. The first axis defines a stacking direction of the layer stack 14 and is Figure 1 The (vertical) z-axis of a coordinate system having x-, y-, and z-axes in .
[0059] The 3D ferroelectric memory structure 10 also includes a first ferroelectric layer 15, which extends through the layers 12, 13 of the stack 14. The ferroelectric layer 15 can extend through all layers 12, 13 of the stack 14 and can fall on the substrate 11 (as shown in the figure). The first ferroelectric layer 15 can extend along a first axis (as shown in the figure) and can therefore extend perpendicular to the surfaces of the layers 12, 13 of the layer stack 14. The stack 14 can start with a first metal layer 12 or a dielectric layer 13 (as the bottom layer of the stack 14), for example, which is directly arranged or grown on the substrate 11. The layer stack 14 can also end with the first metal layer 12 or the dielectric layer 13 (as the top layer of the stack 14, i.e., the layer farthest from the substrate 11), Figure 1 The stack 14 shown is only an example.
[0060] The 3D ferroelectric memory structure 10 further comprises a second metal layer 16 extending through the layers 12, 13 of the stack 14 adjacent to the first ferroelectric layer 15. Thus, the second metal layer 16 may extend along the first axis and may therefore extend perpendicularly to the surfaces of the layers 12, 13 of the layer stack 14. The second metal layer 16 may be disposed on the first ferroelectric layer 15.
[0061] The first ferroelectric layer 15, in combination with the plurality of first metal layers 12 and second metal layers 16, forms a plurality of first capacitive memory cells. Each of these first capacitive memory cells may be formed by a capacitor including one of the first metal layer 12 and the second metal layer 16 as capacitor plates and the first ferroelectric layer 15 as a dielectric between the capacitor plates.
[0062] The first work function of the first metal layer 12 is different from the second work function of the second metal layer 16. In this case, the non-destructive readout of the first capacitive memory cell of the 3D ferroelectric memory structure 10 can be performed at zero bias, as will be explained below. The first work function of the first metal layer 12 can also be the same as the second work function of the second metal layer 16. In this case, the non-destructive readout of the first capacitive memory cell of the 3D ferroelectric memory structure 10 can be performed by applying a small DC bias, as will be explained below.
[0063] The first metal layer 12 and the second metal layer 16 may respectively include one or more of the following: molybdenum; a composition including molybdenum and molybdenum oxide; titanium nitride; a composition including ruthenium and titanium nitride; and tungsten. Both of them may be selected from these materials or material compositions, wherein the first metal layer 12 and the second metal layer 16 may include different materials or material compositions or the same material or material composition.
[0064] Notice, Figure 1 Only a portion of the 3D ferroelectric memory structure 10 is shown, while another portion is not shown (in FIG. Figure 1In this regard, different implementations are possible, for example, referring to Figure 2 Implementation of presentation.
[0065] Figure 2 A first example of a 3D ferroelectric memory structure 10 according to the present disclosure is shown, which is constructed on Figure 1 The 3D ferroelectric memory structure 10 is shown. Figure 1 and Figure 2 The same elements in the embodiment share the same reference numerals and can be implemented similarly. Specifically, Figure 1 and Figure 2 The left side of the 3D ferroelectric memory structure 10 may be the same.
[0066] Figure 2 The 3D ferroelectric memory structure 10 shown further includes (in Figure 2 14 (shown on the right side of ), a second ferroelectric layer 21 extending through the layers 12, 13 of the stack 14, and a third metal layer 22 extending through the layers 12, 13 of the stack 14 adjacent to the second ferroelectric layer 21. The second ferroelectric layer 21 can extend along a first axis (as shown in the figure), and can therefore extend perpendicular to the surfaces of the layers 12, 13 of the layer stack 14. Therefore, the first ferroelectric layer 15 and the second ferroelectric layer 21 can extend parallel to each other. The third metal layer 22 can also extend along the first axis, and can therefore extend perpendicular to the surfaces of the layers 12, 13 of the layer stack 14. The second metal layer 22 can be arranged on the second ferroelectric layer 21.
[0067] The second ferroelectric layer 21 forms a plurality of second capacitive memory cells in combination with a plurality of first metal layers 12 and a third metal layer 22. Each of these second capacitive memory cells may be formed by a capacitor comprising one of the first metal layer 12 and the third metal layer 22 as a capacitor plate and the second ferroelectric layer 21 as a dielectric between the capacitor plates. The first work function of the first metal layer may be different from the third work function of the third metal layer 22 or may be the same. The second capacitive memory cells may therefore be read out non-destructively at zero bias or at a small DC bias, respectively, as described above for the first capacitive memory cells and described in more detail below. The work functions of the second metal layer 16 and the third metal layer 22 may be different, but preferably the same. The third metal layer 22 may include one or more of the following: molybdenum; a composition comprising molybdenum and molybdenum oxide; titanium nitride; a composition comprising ruthenium and titanium nitride; and tungsten. The third metal layer 22 may include a material or material composition different from the first metal layer 12. Third metal layer 22 may include a different material or material composition than second metal layer 16 , but preferably has the same material or material composition as second metal layer 16 .
[0068] Figure 2 The illustrated 3D ferroelectric memory structure 10 further includes a dielectric material 23 extending through the layers 12, 13 of the stack 14 and disposed between the second metal layer 22 and the third metal layer 16. The dielectric material 23 may be the same dielectric material used for the dielectric layer 13. For example, the dielectric material 13 may be an oxide, such as silicon oxide.
[0069] Figure 3 A second example of a 3D ferroelectric memory structure 10 according to the present disclosure is shown, which is similar to Figure 1 and 2 The structure 10 is shown. Figure 1 , Figure 2 and Figure 3 The same elements in the embodiment share the same reference numerals and can be implemented similarly. Specifically, Figure 3 (a) shows a cross-sectional view along the z-axis, and Figure 3 (b) shows a cross-sectional view along the y-axis, also as Figure 1 and Figure 2 shown.
[0070] and Figure 2 Different from the Figure 3 In the 3D ferroelectric memory structure 10 shown, the first ferroelectric layer 15 and the second ferroelectric layer 21 extend at opposite angles relative to the first axis. That is, the distance between the two ferroelectric layers 15 and 21 varies along their extension, which may result in a tapered arrangement of the two ferroelectric layers (as shown in the figure). In addition, the second metal layer 16 and the third metal layer 22 extend at (the same) opposite angles relative to the first axis.
[0071] like Figure 3 It can be further seen in (a) that the second metal layer 16 and the third metal layer 22 each have a shorter extension along the y-axis (generally speaking, a third axis perpendicular to the first and second axes (ie, the x-axis)) than the first ferroelectric layer 15 and the second ferroelectric layer 21, respectively.
[0072] Figure 4 Shows Figure 3 Additional optional details of the 3D ferroelectric memory structure 10. Specifically, Figure 4It is shown that each of the multiple first metal layers 12 can be connected to a corresponding word line driver 42. Each first metal layer 12 thus acts as a word line (or a portion of a word line) for selecting one or more memory cells implemented by the 3D ferroelectric memory structure 10. For example, a first capacitor memory cell and a second capacitor memory cell can be selected by each word line (i.e., one for each first metal layer 12) in the 3D ferroelectric memory structure 10 shown. In addition, each of the second metal layer 16 and the third metal layer 22 is connected to a corresponding sensing circuit 41 (also referred to as a readout circuit) and thereby acts as a bit line (or a portion of a bit line). The sensing circuit can be a transistor and can be used to read out one or more memory cells selected by the activated word line. Specifically, each sensing circuit can read out a memory cell selected by the activated word line.
[0073] In summary, the 3D ferroelectric memory structure 10 may include several (N) stacked capacitors with horizontal (along the x-axis) word lines and vertical (along the y-axis) bit lines. The metal layers 16, 22 associated with the bit lines may be connected to a readout (sensing) circuit 41 in the substrate 11. Each sensing circuit 41 may be formed in the substrate 11. One sensing circuit 41 is associated with N capacitors connected to the corresponding vertical bit lines.
[0074] The 3D ferroelectric memory structure 10 of the present disclosure can be a NAND type back-end-of-line (BEOL) memory. The present disclosure can provide a true X-point memory architecture. The ferroelectric memory structure 10 can be used for CiM applications or as FeRAM. Asymmetric reading can be accomplished by the work function difference of the magnetic materials 12, 16, 22 and can be enhanced by applying a read bias.
[0075] Figure 5 1 shows a flow chart of a method 50 for reading out a 3D ferroelectric memory structure 10 according to the present disclosure. Figure 1-4 In the 3D ferroelectric memory structure 10 read out by the method 50 , the first metal layer 12 and the second metal layer 16 may or may not have different work functions.
[0076] In order to non-destructively read out the first capacitive memory cell of the 3D ferroelectric memory structure 10, the method 50 includes a step 51 of applying a DC bias to the first ferroelectric layer 15 through one of the first metal layer 12 and the second metal layer 16, wherein the DC bias is lower than the voltage required to change the current polarization state of the first ferroelectric layer 15. In addition, the method 50 includes a step 52 of detecting the capacitance of the first ferroelectric layer 15 under the bias, and a step 53 of correlating the detected capacitance to the current polarization state of the first ferroelectric layer 15. If the first metal layer 12 and the second metal layer 16 have different work functions, the DC bias can even be zero or close to zero.
[0077] Similarly, to non-destructively read out the second capacitive memory cell of the 3D ferroelectric memory structure 10, the method 50 includes the step of applying a DC bias to the second ferroelectric layer 21 through one of the first metal layer 12 and the third metal layer 22, wherein the DC bias is lower than the voltage required to change the current polarization state of the second ferroelectric layer 21. In addition, the method 50 includes the step of detecting the capacitance of the second ferroelectric layer 21 under the bias, and the step of correlating the detected capacitance to the current polarization state of the second ferroelectric layer 21. If the first metal layer 12 and the third metal layer 22 have different work functions, the DC bias can even be zero or close to zero.
[0078] The steps of applying DC bias to the first ferroelectric layer 15 and the second ferroelectric layer, respectively, can be performed in parallel by using the same first metal layer among the first metal layers 12 as a word line.
[0079] The capacitance of the first ferroelectric layer 15 and the second ferroelectric layer 21 can be detected respectively by applying an AC voltage signal to one side of the first ferroelectric layer 15 or the second ferroelectric layer 21 and detecting the dielectric response of the first ferroelectric layer 10 or the second ferroelectric layer 20 through the AC voltage signal on the other side of the first ferroelectric layer 5 or the second ferroelectric layer 21. The AC voltage signal can be detected via the metal layers 16, 22 using a sensing circuit 41.
[0080] Figure 6 A graph of measurements using a 3D ferroelectric memory structure 10 according to the present disclosure is shown.
[0081] Figure 6 (a) shows the CV characteristics of the ferroelectric memory structure 10. Thus, the x-axis shows the bias voltage applied to the first ferroelectric layer 15, and the y-axis shows the effective dielectric constant of the first ferroelectric layer 15 (linearly related to the capacitance). Figure 6 The curve in (a) can therefore also be called the ε deviation curve
[0082] Specifically, Figure 6 The CV characteristics shown in (a) indicate that the asymmetry of the work functions of the first metal layer 12 and the second metal layer 16 on opposite sides of the ferroelectric layer 15 results in the asymmetry of the curve. That is, even at zero bias (0 V), the capacitance of the first ferroelectric layer 15 is different depending on the polarization state (e.g., up or down) of the first ferroelectric layer. The asymmetry in the ε bias curve allows detection of the polarization state of the capacitor (i.e., one of the first capacitive memory cells being read out) even at zero bias without switching the first ferroelectric layer 15 (i.e., non-destructive readout). This allows for very low power (deep low power mode) non-volatile memory elements that exhibit very high read endurance and are suitable for selector-free operation.
[0083] exist Figure 6 In (a), the effective dielectric constant of the first ferroelectric layer 15 in the first polarization state (ε+) and the second polarization state (ε-) under zero bias is particularly highlighted. The difference between ε+ and ε- defines the memory window (MW) of the 3D ferroelectric memory structure 10. Due to this memory window, data can be read without switching / disturbing the polarization state even under zero DC voltage bias. However, a small DC voltage bias can be applied.
[0084] For example, the effective dielectric constant (ε+ or ε-) of the first ferroelectric layer 15 can be read by applying a low AC voltage signal (e.g., 30 mV) to one of the first metal layers 12 and observing the response at the second metal layer 16. For example, as explained above, the first metal layer 12 can be connected to a word line, and the second metal layer 16 can be connected to a bit line. Thus, the memory state can be read using these word lines and bit lines without switching / disturbance of the polarization state.
[0085] Specifically, an AC voltage signal can be applied to the 3D ferroelectric memory structure 10 in the form of a voltage pulse, which can result in the accumulation of displacement charges. When the 3D ferroelectric memory structure 10 is subsequently discharged, a displacement current that can be measured is generated. Based on the displacement current, the capacitance of the first ferroelectric layer 15 of the 3D ferroelectric memory structure 10 and thus the polarization state (memory state) can be detected.
[0086] Figure 6 (b) shows the zero bias voltage (V read The results of approximately 300 consecutive measurements of ε+ and ε- at 100 Ω ~ 0 V. These measurements show that the memory window, i.e. the difference between ε+ and ε-, remains relatively constant over time, decreasing only slightly after the first measurement.
[0087] Specifically, the fact that the 3D ferroelectric memory structure 10 can be read out in a non-destructive manner results in the endurance specification of the memory structure 10 being determined by the write cycle requirement rather than the read cycle. In addition, power consumption can be much lower because only the displacement current from the paraelectric response of the first ferroelectric layer 15 to the AC signal is required, without actually switching the first ferroelectric layer 15.
[0088] Figure 6 (c) shows the retention times measured in memory states ε+ and ε- These measurements show that good retention times of greater than 1.000 seconds can be achieved.
[0089] It is worth noting that the above reference Figure 6 The description of (a)-(c) is similarly applicable to the readout of the second ferroelectric layer 16 and the second capacitive memory cell of the 3D ferroelectric memory structure 10 .
[0090] In this example, the 3D ferroelectric memory structure 10 according to the present disclosure includes a first metal layer 12 and a second metal layer 16 having the same work function, in particular, both of which can be made of TiN. In this example, the ferroelectric memory structure 10 produces a symmetrical CV characteristic (also known as a symmetrical butterfly curve) that has no memory window under zero voltage bias. However, in order to perform non-destructive readout, a DC bias voltage V can be applied to, for example, the first ferroelectric layer 15 through the first and second metal layers 12, 16. read ~-0.5V. At this bias, the effective dielectric constants corresponding to the positive and negative polarization states will not be equal, and the difference results in a non-zero memory window. However, this 3D ferroelectric memory structure 10 cannot be read out at zero bias. In order to achieve non-destructive readout, the bias is selected to be lower than the voltage required to change the current polarization state of the first ferroelectric layer 15.
[0091] It can be observed that for this example of the 3D ferroelectric memory structure 10, after up to 300 consecutive measurements of the polarization states ε+ and ε- at a non-zero DC read voltage of -0.5V, the memory window decreases slightly but remains large enough for non-destructive readout.
[0092] In another example, the 3D ferroelectric memory structure 10 includes a first metal layer 12 and a second metal layer 16 having different work functions, in particular, it can have a first ferroelectric layer 15 made of La:HZO, a first metal layer 12 made of MoOx / M, and a second metal layer 16 made of TiN. Due to the different work functions of these metal layers 12 and 16, the CV curve is asymmetric, which leads to a non-zero storage window under zero voltage bias. Thus, non-destructive readout can be made even under zero bias. However, the memory window can be further increased by applying a non-zero bias to the first ferroelectric layer 15. Thus, the bias is lower than the voltage required to switch the memory state of the first ferroelectric layer 15.
[0093] It can be observed that for this example of the 3D ferroelectric memory structure 10, the initial memory window value only drops very slightly after up to 300 consecutive measurements of the polarization states ε+ and ε- at a non-zero DC read voltage of, for example, -0.3 V. Therefore, by combining the 3D ferroelectric memory structure 10 with a non-zero DC bias (which is less than the voltage required to switch the memory state), a stable memory window that can be read out in a non-destructive manner can be created.
[0094] In the above examples, a DC bias of, for example, -500 mV or -300 mV may be applied to the respective first ferroelectric layer 15. These values are merely examples of possible non-zero readout voltages. Other DC biases (lower than the voltage required to change the polarization state of the ferroelectric material layer) may be chosen.
[0095] In summary, the difference in capacitance values of the two polarization states of the first ferroelectric layer 15 (the so-called memory window) can be generated by exploiting a change in the dielectric response of the first ferroelectric layer, which occurs before the first ferroelectric layer switches its polarization state. In this way, the polarization state can be read out in a non-destructive manner. In order to generate this memory window, the symmetry of the system can be broken by using different work function metals on both sides of the ferroelectric layer 15. Additionally or alternatively, the memory window can be generated or assisted by using asymmetric write / erase voltages and / or by applying a DC bias during readout.
[0096] It is worth noting that the above contents are similarly applicable to the readout of the second ferroelectric layer 16 and the second capacitive memory cell of the 3D ferroelectric memory structure 10 .
[0097] Figure 7 Schematic diagram of a memory device 70 according to the present disclosure is shown. The memory device 70 includes a plurality of 3D ferroelectric memory structures 10, for example, Figure 1-4 As shown in any of the drawings in FIG. 3D ferroelectric memory structures 10 are arranged in a vertical and horizontal array.
[0098] Preferably, the 3D ferroelectric memory structure 10 of the memory device 70 can form a selector-free, capacitor-only array (0T-1C array), i.e., a memory array without a select transistor. This is possible because the memory structure 10 does not have to be switched during readout, which allows the select transistor to be removed. Therefore, the memory structure 10 can be densely arranged and can be implemented in 3D as described above.
[0099] Sensing of the memory state can be accomplished by an AC voltage signal on the word lines WL1, WL2, ..., WLn connected to the first metal layer 12 and detecting the dielectric response on the bit lines BL1, BL2, ..., BLn (e.g., connected to the second metal layer 16 or the third metal layer 22). In this way, a very compact memory array can be generated that can be fully constructed at the back end of the process and can therefore be uniformly stacked. This can reduce the cost of the memory array.
[0100] Specifically, the 3D ferroelectric memory structure 10 provides a plurality of memory cells of a memory device 70. Compared to conventional memory cells using resistive elements (e.g., resistive RAM, phase change cells, MRAM), the capacitive memory structure 10 does not require active current, which greatly reduces their power consumption. The displacement current that can be used to read out the memory structure can be much lower than the active current in conventional memory and only operates for a limited time during readout. Therefore, the memory structure 10 can be superior for CiM applications that require large memory arrays.
[0101] In the claims and the description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to an advantageous embodiment.
Claims
1. A three-dimensional ferroelectric memory structure, comprising: substrate; a layer stack arranged on the substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of first metal layers arranged alternately with each other along a first axis; a first ferroelectric layer extending through the layers of the stack; as well as a second metallic layer extending through the layers of the stack adjacent to the first ferroelectric layer; wherein the first ferroelectric layer, in combination with the plurality of first metal layers and the second metal layer, forms a plurality of first capacitor memory cells; and The first work function of the first metal layer is different from the second work function of the second metal layer.
2. The 3D ferroelectric memory structure of claim 1, further comprising: a second ferroelectric layer extending through the layers of the stack; as well as a third metal layer extending through the layers of the stack adjacent to the second ferroelectric layer; wherein the second ferroelectric layer, in combination with the plurality of first metal layers and the third metal layer, forms a plurality of second capacitor memory cells; and The first work function of the first metal layer is different from the third work function of the third metal layer. 3 . The 3D ferroelectric memory structure of claim 2 , further comprising a dielectric material extending through each layer of the stack and disposed between the second metal layer and the third metal layer. 4 . The 3D ferroelectric memory structure of claim 2 , wherein both the first ferroelectric layer and the second ferroelectric layer extend along the first axis or extend obliquely at opposite angles relative to the first axis.
5. The 3D ferroelectric memory structure of claim 1, wherein: The first ferroelectric layer and the second ferroelectric layer can be electrically excited to two polarization states respectively; and Each polarization state represents a respective memory state of the first capacitive memory cell or the second capacitive memory cell. 6 . The 3D ferroelectric memory structure of claim 1 , wherein each of the plurality of first metal layers is connected to a corresponding word line driver. 7 . The 3D ferroelectric memory structure of claim 1 , wherein each of the second metal layer and the third metal layer is connected to a corresponding sensing circuit.
8. The 3D ferroelectric memory structure of claim 7, wherein each sensing circuit is formed in the substrate.
9. The 3D ferroelectric memory structure of claim 1, wherein the first work function differs from the second work function and / or the third work function by at least 0.3 eV. 10 . The 3D ferroelectric memory structure of claim 1 , wherein the first metal layer comprises a different material or material combination than the second metal layer and / or the third metal layer.
11. The 3D ferroelectric memory structure of claim 1 , wherein at least one of the first metal layer, the second metal layer, and the third metal layer comprises any one of the following materials or material combinations: -molybdenum; - a composition comprising molybdenum and molybdenum oxide; - titanium nitride; - a composition comprising ruthenium and titanium nitride; or -Tungsten.
12. The 3D ferroelectric memory structure of claim 1, wherein the first ferroelectric layer comprises hafnium zirconium oxide (HZO), such as lanthanum-doped HZO.
13. A memory device comprising a plurality of 3D ferroelectric memory structures as claimed in any one of claims 1 to 12, wherein the 3D ferroelectric memory structures are arranged in a vertical and horizontal array.
14. A method for reading out a 3D ferroelectric memory structure, wherein the 3D ferroelectric memory structure comprises a layer stack arranged on a substrate, the layer stack comprising a plurality of dielectric layers and a plurality of first metal layers arranged alternately on top of each other along a first axis, a first ferroelectric layer extending through each layer of the stack, and a second metal layer extending through the layers of the stack adjacent to the first ferroelectric layer, the first ferroelectric layer, in combination with the plurality of first metal layers and the second metal layer, forming a plurality of first capacitive memory cells; The method comprises: applying a DC bias to the first ferroelectric layer through one of the first metal layer and the second metal layer, wherein the DC bias is lower than a voltage required to change a current polarization state of the first ferroelectric layer; detecting the capacitance of the first ferroelectric layer under the bias voltage; and The detected capacitance is related to the current polarization state of the first ferroelectric layer.
15. The method of claim 14, wherein: The capacitance of the first ferroelectric layer is detected by applying an AC voltage signal to one side of the first ferroelectric layer and detecting a dielectric response of the first ferroelectric layer through the AC voltage signal on the other side of the first ferroelectric layer.