Preparation method of SiC MOSFET structure and SiC MOSFET structure

Abstract

The invention discloses a preparation method of a SiC MOSFET structure and the SiC MOSFET structure, and the preparation method comprises the steps: forming a PS shielding layer through a self-alignment technology and ion implantation, depositing an ohmic contact metal layer which comprises ohmic contact metal, and then carrying out the RTP annealing treatment once, the ohmic contact metal reacts with SiC to form a SixN iy compound, and part of C particles are separated out; ohmic contact metal which does not react to form a compound and part of C particles are stripped through wet cleaning, and then secondary RTP annealing treatment is carried out to form stable ohmic contact. According to the preparation method, the grid shielding effect of the SiC MOSFET structure is enhanced, the electric field intensity of the oxide layer is reduced, the current is promoted to be expanded to the drift region, the electric field concentration at the bottom of the grid groove is alleviated, good ohmic contact is formed, the conduction loss of the SiC MOSFET device structure is reduced, and the parasitic inductance is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for preparing a SiC MOSFET structure and a SiC MOSFET structure. Background Art

[0002] Silicon carbide (SiC) is a typical wide bandgap semiconductor material. It has excellent physical properties such as high breakdown field and high electron mobility, making it an ideal material for preparing high-temperature resistant high-power semiconductor devices. The SiC MOSFET structure has many excellent properties and is widely used in electric vehicles, charging piles and other fields. However, the development of the SiC MOSFET structure is affected by its low channel mobility and large channel resistance. In the prior art, the trench MOSFET structure is widely considered to be an effective method to achieve a low on-resistance SiC MOSFET structure. However, for the traditional trench MOSFET structure, due to the lack of a shielding area, the device may face many problems under high drain voltage, such as severe concentration of electric field strength at the corner of the trench, and the electric field strength in the oxide layer is about 2.5 times that of the electric field strength in SiC. In addition, the contact resistance of the source is also a key factor affecting the conduction loss of SiC MOS devices.

[0003] Therefore, it is very necessary to provide a SiC MOSFET structure and a preparation method thereof that can reduce the electric field strength of the oxide layer and promote the current to expand to the drift region, alleviate the electric field concentration at the bottom of the gate trench, and reduce the conduction loss. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems and provide a method for preparing a SiC MOSFET structure and a SiC MOSFET structure. The SiC MOSFET structure has a strong gate shielding effect, which can not only reduce the electric field strength of the oxide layer and promote the expansion of the current to the drift region, alleviate the electric field concentration at the bottom of the gate trench, but also form a good ohmic contact, reduce the conduction loss of the SiC MOSFET device, and reduce the parasitic inductance.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for preparing a SiC MOSFET structure, comprising the steps of:

[0007] S1. Growing an N-drift layer and an N-type SiC current transport layer in sequence on a silicon carbide N+ substrate by epitaxial growth;

[0008] S2, by ion implantation, sequentially implanting a PW well region, an N+ source region and a P+ base region on the N-type CSL;

[0009] S3, forming a trench structure by etching the top N-type SiC current transport layer;

[0010] S4. Forming a PS shielding layer by self-alignment process and ion implantation:

[0011] S5, oxidizing the trench structure, depositing polysilicon and etching back to form a gate, and depositing ILD and etching back to form a dielectric isolation layer;

[0012] S6, depositing an ohmic contact metal layer, wherein the ohmic contact metal layer includes an ohmic contact metal, performing an RTP annealing treatment, wherein the ohmic contact metal reacts with SiC to form a SixNiy compound and precipitates C particles, and removing the ohmic contact metal and part of the C particles that have not reacted to form the SixNiy compound by wet cleaning, and then performing a secondary RTP annealing treatment to form a stable ohmic contact;

[0013] S7. Deposit a front metal on the front side to form a source electrode, and deposit a back metal on the back side after thinning to form a drain electrode.

[0014] Optionally, step S4 specifically includes the following steps:

[0015] Depositing a layer of boron-doped D-poly with a thickness of 0.5-1 μm on the trench structure formed in step S3 by LPCVD process to form an LP-Poly layer as a self-aligned mask layer, and annealing at 500° C.-550° C. for 30-45 minutes in a horizontal furnace;

[0016] The self-aligned mask layer is etched by dry etching, and then a concentration of 1E15cm -3 To 1E17cm -3 The aluminum ions form a PS shielding layer; the remaining self-aligned mask layer is removed by silicon etching solution; and then the surface of the trench structure is processed by hydrogen heat treatment.

[0017] Optionally, in step S4, the silicon etching solution includes, by mass percentage, 35% nitric acid, 15% hydrofluoric acid, 15% acetic acid and the remainder solvent; the etching time is 5 minutes.

[0018] Optionally, in step S6, the deposition process of the ohmic contact metal layer adopts a sputtering process; the ohmic contact metal includes at least one of metal Ni or metal Ti; the temperature of the first RTP annealing treatment is 500-550°C, and the temperature of the second RTP annealing treatment is 1000-1050°C.

[0019] Optionally, in step S6, the stripping liquid used in the wet cleaning is a metal stripping liquid; the metal stripping liquid includes concentrated sulfuric acid and hydrogen peroxide in a mixing ratio of 4-5:1 in parts by mass.

[0020] Optionally, step S1 specifically includes the steps of: growing 5-20 μm and 1E16 cm concentration on a 350±1 μm N+ substrate in a homoepitaxial manner. -3 The concentration of N-drift layer is 1-2μm higher than that of drift region, which is 1E16cm -3 To 1E17cm -3 N-type SiC current transport layer.

[0021] Optionally, in step S2, the ion implantation temperature is 500±10°C and the implantation concentration is 1E12cm -3 To 1E13cm -3 The aluminum ions form the PW well region, with an implantation concentration of 1E14 cm -3 To 1E15cm -3 Phosphorus ions or nitrogen ions form the N+ source region, and the implantation concentration is 1E16cm -3 To 1E17cm -3 Aluminum ions form the P+ base region.

[0022] Optionally, in step S3, the etcher uses a power of 500-800 W, an RF bias power of 80-200 W, an etching pressure of 0.502 Pa, and a main etching gas of SF6 / O2 / HBr, with a corresponding flow ratio of 30 / 20 / 15 sccm.

[0023] Optionally, step S5 specifically includes the steps of: introducing O2 dry oxygen oxidation at an oxidation temperature of not less than 1350°C through a CT oxidation furnace, with an O2 flow rate of 2-3slm and a pressure of 800-900mtorr, with the thickness of the gate oxide after oxidation being 40-50nm, and passivation treatment by NO and low oxygen annealing to improve the contact interface; etching away excess D-Poly Si by dry etching; and depositing an ILD dielectric isolation layer by a PECVD process; wherein the ILD dielectric isolation layer includes 0.2μm USG and 0.8μm BPSG.

[0024] In a second aspect, the present invention provides a SiC MOSFET structure, which is prepared by using the preparation method of the SiC MOSFET structure as described in any one of the above items.

[0025] The beneficial effects produced by the present invention include at least:

[0026] In the preparation method of the SiC MOSFET structure described in the present invention, by sputtering ohmic contact metal, a first RTP annealing treatment is performed, and part of the C particles precipitated by the SixNiy compound can be removed by a metal stripping solution. On the other hand, the metal stripping solution can also strip part of the metal that has not reacted to form a compound on SiO2, and then a second RTP annealing treatment is performed to form a stable ohmic contact; the compound formed by the two RTP annealing treatments has a smaller difference in electron affinity with the work function of SiC and a lower contact resistivity; at the same time, a PS shielding layer is formed in combination with a self-alignment process; the gate shielding effect of the SiC MOSFET structure is enhanced, the electric field strength of the oxide layer is reduced, and the current is promoted to expand to the drift region, the electric field concentration at the bottom of the gate trench is relaxed, and a good ohmic contact is formed, thereby reducing the conduction loss of the SiC MOSFET device structure and reducing the parasitic inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The figure is a process flow chart of the method for preparing the SiC MOSFET structure of the present invention.

[0028] Figure 2 Schematic diagram of the structure produced in step S1.

[0029] Figure 3 Schematic diagram of the structure produced in step S2.

[0030] Figure 4 Schematic diagram of the structure produced in step S3.

[0031] Figure 5 It is a schematic diagram of the structure after the LP-Poly layer is formed in step S4.

[0032] Figure 6 This is a SEM test image of the LP-Poly layer structure formed in step S4.

[0033] Figure 7 This is a schematic diagram of the structure after the PS shielding layer is formed in step S4.

[0034] Figure 8 It is a schematic diagram of the structure obtained after hydrogen heat treatment in step S4.

[0035] Fig. 9 Schematic diagram of the structure obtained after depositing the B-doped D-poly layer.

[0036] Fig.10 This is a curve obtained by CV test at Vgs 20V.

[0037] Fig.11 This is the curve chart of TDDB test.

[0038] Fig.12 This is a test diagram of the sheet resistance after annealing in step S5.

[0039] Fig.13 It is a schematic diagram of the structure obtained after etching in step S5.

[0040] Fig.14 It is a schematic diagram of the structure after depositing the ILD dielectric isolation layer in step S5.

[0041] Fig.15 It is a schematic diagram of the structure obtained after depositing the ohmic contact metal layer 11.

[0042] Fig.16 This is a schematic diagram of the structure obtained in step S6.

[0043] Fig.17 Schematic diagram of the structure of the SiC MOSFET described in the present invention.

[0044] Among them, 1-N+ substrate, 2-N-drift layer, 3-N-type SiC current transfer layer, 4-PW well region, 5-N+ source region, 6-P+ base region, 7-self-aligned mask layer, 8-PS shielding layer, 9-B-doped D-poly, 10-ILD dielectric isolation layer, 11-ohmic contact metal layer, 12-source, 13-drain. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in the present invention. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The raw materials used in the present invention, unless otherwise specified, are derived from suppliers known in the art or are prepared by known methods.

[0047] Example:

[0048] The embodiment of the present invention provides a SiC MOSFET structure and a method for preparing the SiC MOSFET structure. Figure 1 As shown, the preparation method comprises the steps of:

[0049] S1, growing an N-drift layer 2 and an N-type SiC current transport layer 3 in sequence on a silicon carbide N+ substrate 1 by epitaxial growth;

[0050] Step S1 specifically includes the following steps: growing 5-20 μm thick N+ substrate 1 with a concentration of 1E16 cm by homoepitaxial method in sequence on the substrate 1 with a thickness of 350±1 μm. -3 The concentration of N-drift layer 2, 1-2μm is higher than that of drift region, which is 1E16cm -3 To 1E17cm -3 N-type SiC current transport layer; the schematic diagram of the structure obtained in this step is as follows Figure 2 The introduction of the N-type SiC current transport layer further reduces the on-resistance and channel current influence in the device structure.

[0051] S2. By ion implantation, a PW well region 4, an N+ source region 5 and a P+ base region 6 are sequentially implanted on the N-type CSL; the high-temperature, high-energy, step-by-step, multiple-box implantation is adopted in the embodiment of the present invention, and the ion implantation temperature is 500±10°C and the implantation concentration is 1E12cm -3 To 1E13cm -3 The aluminum ions form the PW well region 4, and the implantation concentration is 1E14cm -3 To 1E15cm -3 Phosphorus ions or nitrogen ions are used to form the N+ source region 5, with an implantation concentration of 1E16 cm -3 To 1E17cm -3 The aluminum ions form the P+ base region 6. The structure obtained in this step is as shown Figure 3 shown.

[0052] S3, forming a trench structure by etching the top N-type SiC current transport layer; specifically:

[0053] The CSL in the implanted SiC epitaxial layer is grooved by using SPTS's Omega LPX Rapier etcher. The structure diagram is shown in the figure below. Figure 4 As shown. The power used by the etcher is 500-800W, the RF bias power is 80-200W, the etching pressure is 0.502Pa, and the main etching gas introduced is SF6 / O2 / HBr, with a corresponding flow ratio of 30 / 20 / 15sccm. The introduction of O2 is due to the fact that the generated by-products are poorly volatile and easily deposited on the side walls of the cavity. O2 can react with them to form SiBrxOy polymers, which helps to form an etching morphology with good steepness, a flat bottom without micro-grooves, and a smooth bottom without footing.

[0054] S4, forming a PS shielding layer 8 by self-alignment process and ion implantation; specifically:

[0055] A layer of boron-doped D-poly with a thickness of 0.5-1 μm is deposited on the groove structure formed in step S3 by LPCVD low-pressure chemical vapor deposition process to form an LP-Poly layer low-pressure polysilicon layer as a self-aligned mask layer 7, and annealed at 500°C-550°C for 30-45 minutes in a horizontal furnace to ensure that the doping is uniform, which is conducive to uniform etching and good morphology formation. The schematic diagram of the obtained structure is shown in Figure 5 As shown; wherein, the LP-Poly layer is used as the self-aligned mask layer 7, because its step coverage rate is as high as 96%-98% and its angle conformality is good, see Figure 6 As shown in the figure, the thickness of the LP-Poly layer at a is 0.480 μm, the thickness at b is 0.500 μm, the thickness at c is 0.488 μm, and the thickness at d is 0.484 μm; indicating that the thickness of the LP-Poly layer obtained in this step is relatively uniform at each location, the step coverage is high, and the wrap angle is good;

[0056] The self-aligned mask layer 7 is etched by dry etching, and then a concentration of 1E15cm -3 To 1E17cm -3 The aluminum ions form a PS shielding layer 8, and the obtained structural schematic diagram is as follows Figure 7 As shown; wherein, the dry etching is completed by AMAT's P5000 equipment, and the main gas for D-Poly Si etching is Cl2; the injection of aluminum ions is performed by high-temperature ion injection;

[0057] The remaining self-aligned mask layer 7 is removed by silicon etching solution; then the surface of the trench structure is treated by hydrogen heat treatment; the resulting structure is shown in FIG. Figure 8 As shown; wherein, in terms of mass percentage, the silicon etching solution includes 35% nitric acid, 15% hydrofluoric acid, 15% acetic acid and the remainder solvent; the etching time is 5 minutes, so that the self-aligned mask can be completely removed. On the one hand, hydrogen heat treatment makes the surface of the groove silicon carbide smooth, thereby reducing the roughness scattering of the channel and improving the mobility of the device; on the other hand, hydrogen heat treatment can also make the groove angle rounded, and the rounded groove angle will increase the gate oxide breakdown time and significantly improve the reliability of MOSFET.

[0058] S5, oxidizing the trench structure, depositing polysilicon and etching back to form a gate, and depositing ILD and etching back to form a dielectric isolation layer;

[0059] Step S5 specifically includes the steps of: introducing O2 dry oxygen oxidation at an oxidation temperature of not less than 1350°C through a CT oxidation furnace, the flow rate of O2 is 2-3slm, the pressure is 800-900mtorr, the thickness of the gate oxide after oxidation is 40-50nm, and passivation treatment is performed by NO and low oxygen annealing to improve the contact interface; see Fig.10 As shown, through CV test at Vgs 20V, the two curves of Positive Scan (voltage gradually increases from a lower value to a higher value) and Negative Scan (voltage gradually decreases from a higher value to a lower value) are basically consistent; Nits = 4.43e+09cm -2 , t ox =48.65nm, △V FB = 0.01V, it can be seen that the near-interface traps are significantly reduced. In addition, Fig.11 As shown in the figure, the TDDB test once again verified the excellent gate oxide reliability performance of the device under this gate oxide condition. Then, a layer of B-doped D-poly 9 with a thickness of 0.5±0.1μm is deposited as the gate oxide layer by the LPCVD process, and the resulting structure is shown in the figure below. Fig. 9 As shown, and annealed at 1000℃-1050℃ for 30min, the square resistance was measured after annealing. Fig.12 As shown, the uniformity within the chip is good and the square resistance is about 12.3Ω / □.

[0060] The excess D-Poly Si is etched away by dry etching equipment AMAT P5000, and the resulting structure is shown in the figure below. Fig.13 As shown; due to the presence of thermally oxidized SiO2 at the bottom and the large etching selectivity between thermally oxidized SiO2 and Poly, the micro-groove phenomenon of Poly etching is avoided.

[0061] The ILD dielectric isolation layer 10 is deposited by using a PECVD process using an AMAT P5000 machine of Applied Materials. The obtained structure diagram is shown in FIG. Fig.14 As shown; wherein the ILD dielectric isolation layer 10 includes 0.2μm USG undoped silicate glass, Undoped Silicate Glass) and 0.8μm BPSG boron-phosphorus silicate glass, Boron-Phosphorus Silicate Glass; wherein, on the one hand, adding B and P elements to BPSG can reduce the reflow temperature, and on the other hand, good fluidity and strong hole filling ability can make the ILD flat.

[0062] S6, depositing an ohmic contact metal layer 11, wherein the ohmic contact metal layer 11 includes an ohmic contact metal, performing an RTP annealing treatment, wherein the ohmic contact metal reacts with SiC to form a SixNiy compound and precipitates C particles, and removing the unreacted SixNiy compound ohmic contact metal and part of the C particles by wet cleaning, and then performing a secondary RTP annealing treatment to form a stable ohmic contact; step S6 is performed after partially etching the ILD dielectric isolation layer 10 formed in step S5;

[0063] In step S6, the deposition process of the ohmic contact metal layer 11 adopts a sputtering process. The structural schematic diagram obtained after the ohmic contact metal layer 11 is deposited is as follows: Fig.15 As shown; the ohmic contact metal includes at least one of metal Ni or metal Ti; optionally, in addition to metal Ni or metal Ti, the ohmic contact metal may also be selected from other metals that can react with SiC to form compounds, whose electron affinity is small compared with the work function of SiC and can form ohmic contact. The ohmic contact metal described in the embodiment of the present application is Ni metal, and the thickness of the sputtered Ni metal is 100nm-200nm. The temperature of the first RTP annealing treatment is 500-550℃, and the temperature of the second RTP annealing treatment is 1000-1050℃. Through the TLM test method, a contact condition with a lower contact resistivity is obtained, where N type is about 1E-5Ω·cm 2 , P type is about 1E-3Ω·cm 2 .

[0064] In step S6, the stripping liquid used in the wet cleaning is a metal stripping liquid; the metal stripping liquid includes concentrated sulfuric acid and hydrogen peroxide in a mixing ratio of 4-5:1 by mass. Among them, the mixing ratio of concentrated sulfuric acid and hydrogen peroxide in the embodiment of the present invention is 5:1; during the treatment process, the temperature of the stripping treatment is above 120°C, the time is 10-15 minutes, and the resulting structural schematic diagram is as follows Fig.16 shown.

[0065] The reason why the metal stripping liquid used in the present invention removes the ohmic contact metal that has not reacted to form a compound is that: during the RTP annealing treatment, SiC reacts with Ni metal to form a compound, and SiO2 does not react with Ni metal, so the stripping liquid can be used to quickly remove the ohmic contact metal that has not reacted to form a compound; on the other hand, when SiC and Ni and other ohmic contact metals react to form a compound, carbon particles or carbon clusters will precipitate, and some carbon clusters or carbon precipitation can also be removed by the stripping liquid.

[0066] S7, depositing a front metal on the front to form a source electrode 12, and depositing a back metal on the back after thinning to form a drain electrode 13, the obtained structure is as follows Fig.17 shown.

[0067] In step S7, the deposition method of the source electrode 12 and the drain electrode 13 includes sputtering molding or evaporation; sputtering deposition is selected in the embodiment of the present invention. Wherein, the front metal includes copper-aluminum composite metal, and the deposition thickness is 4-5μm; wherein the copper-aluminum composite metal is 0.5wt%-2wt% Cu doped in Al metal, and the addition of Cu to Al metal can improve electromigration; the back metal includes one or more of Ti, Ni or Ag.

[0068] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a SiC MOSFET structure, characterized in that: Includes steps: S1. Growing an N-drift layer and an N-type SiC current transport layer in sequence on a silicon carbide N+ substrate by epitaxial growth; S2, by ion implantation, sequentially implanting a PW well region, an N+ source region and a P+ base region on the N-type CSL; S3, forming a trench structure by etching the top N-type SiC current transport layer; S4. Forming a PS shielding layer by self-alignment process and ion implantation: S5, oxidizing the trench structure, depositing polysilicon and etching back to form a gate, and depositing ILD and etching back to form a dielectric isolation layer; S6, depositing an ohmic contact metal layer, wherein the ohmic contact metal layer includes an ohmic contact metal, performing an RTP annealing treatment, wherein the ohmic contact metal reacts with SiC to form a SixNiy compound and precipitates C particles, and then wet cleaning is performed to remove the ohmic contact metal that has not reacted to form a SixNiy compound and part of the C particles, and then performing a secondary RTP annealing treatment to form a stable ohmic contact; S7. Deposit a front metal on the front side to form a source electrode, and deposit a back metal on the back side after thinning to form a drain electrode.

2. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: Step S4 specifically includes the following steps: Depositing a layer of boron-doped D-poly with a thickness of 0.5-1 μm on the trench structure formed in step S3 by LPCVD process to form an LP-Poly layer as a self-aligned mask layer, and annealing at 500° C.-550° C. for 30-45 minutes in a horizontal furnace; The self-aligned mask layer is etched by dry etching, and then aluminum ions with a concentration of 1E15 cm-3 to 1E17 cm-3 are injected to form a PS shielding layer; the remaining self-aligned mask layer is removed by silicon etching solution; and then the surface of the groove structure is processed by hydrogen heat treatment.

3. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: In step S4, the silicon etching solution includes, by mass percentage, 35% nitric acid, 15% hydrofluoric acid, 15% acetic acid and the remainder solvent; the etching time is 5 minutes.

4. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: In step S6, the deposition process of the ohmic contact metal layer adopts a sputtering process; the ohmic contact metal includes at least one of metal Ni or metal Ti; the temperature of the first RTP annealing treatment is 500-550°C, and the temperature of the second RTP annealing treatment is 1000-1050°C.

5. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: In step S6, the stripping liquid used in the wet cleaning is a metal stripping liquid; the metal stripping liquid includes concentrated sulfuric acid and hydrogen peroxide in a mixing ratio of 4-5:1 in parts by mass.

6. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: Step S1 specifically includes the following steps: growing 5-20 μm thick N+ substrates with a concentration of 1E16 cm by homoepitaxial method in sequence on a 350±1 μm N+ substrate. -3 The concentration of N-drift layer is 1-2μm higher than that of drift region, which is 1E16cm -3 To 1E17cm -3 N-type SiC current transport layer.

7. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: In step S2, the ion implantation temperature is 500±10°C and the implantation concentration is 1E12 cm -3 The aluminum ions with a concentration of 1E14 cm-3 form the PW well region. -3 to 1E15 cm -3 Phosphorus ions or nitrogen ions are injected into the N+ source region at a concentration of 1E16 cm -3 to 1E17 cm -3 Aluminum ions form the P+ base region.

8. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: In step S3, the power used by the etcher is 500-800W, the RF bias power is 80-200W, the etching pressure is 0.502Pa, the main etching gas introduced is SF6 / O2 / HBr, and the corresponding flow ratio is 30 / 20 / 15sccm.

9. The method for preparing a SiC MOSFET structure according to claim 1, characterized in that: Step S5 specifically includes the following steps: introducing O2 dry oxygen oxidation at an oxidation temperature of not less than 1350°C through a CT oxidation furnace, wherein the flow rate of O2 is 2-3slm, the pressure is 800-900mtorr, the thickness of the gate oxide after oxidation is 40-50nm, and passivation treatment is performed by NO and low oxygen annealing to improve the contact interface; etching away excess D-Poly Si by dry etching; and depositing an ILD dielectric isolation layer by a PECVD process; wherein the ILD dielectric isolation layer includes 0.2μm USG and 0.8μm BPSG.

10. A SiC MOSFET structure, characterized in that: The SiC MOSFET structure is prepared by using the method for preparing a SiC MOSFET structure according to any one of claims 1 to 9.

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