Transistor and preparation method thereof, power device and vehicle

Abstract

The invention relates to a transistor and a preparation method thereof, a power device and a vehicle. The transistor comprises a first semiconductor layer, a groove located in the first semiconductor layer, a second semiconductor layer at least located on the side wall of the groove, and a gate structure located in the groove and making contact with the second semiconductor layer. The crystal system of the second semiconductor layer is the same as the crystal system of the first semiconductor layer, so that the second semiconductor layer is at least formed on the side wall of the groove, crystal defects of the first semiconductor layer on the side wall of the groove can be reduced, the consistency of the groove is improved, the stability of the gate structure is improved, and the performance and the reliability of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a transistor and a method for manufacturing the same, a power device and a vehicle. Background Art

[0002] Early SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) were planar gate structures with simple processes, good unit consistency, and high avalanche energy. However, this structure produces the effect of a junction field effect transistor (JFET), thereby increasing the on-state resistance, and the parasitic capacitance of this structure is also large. To solve this problem, the industry has introduced a trench SiC MOSFET structure, which buries the gate in the substrate to form a vertical channel. Although its process is complex and the unit consistency is worse than the planar structure, it increases the unit density, has no JFET effect, has smaller parasitic capacitance, fast switching speed, very low switching loss, and significantly reduces the on-resistance. Therefore, the new generation of SiC MOSFETs mainly studies and adopts this structure.

[0003] However, the grooves formed in the substrate by the etching process are prone to defects, which have a certain impact on the device performance. Summary of the invention

[0004] The embodiments of the present application provide a transistor and a method for manufacturing the same, a power device and a vehicle, which can reduce the defects caused by trench etching to at least partially solve the above-mentioned technical problems.

[0005] In order to achieve the above object, according to a first aspect of the present application, a transistor is provided, comprising:

[0006] a first semiconductor layer and a trench located in the first semiconductor layer;

[0007] a second semiconductor layer at least located on a sidewall of the trench, wherein the crystal system of the second semiconductor layer is the same as that of the first semiconductor layer;

[0008] A gate structure is located in the trench, and the gate structure is in contact with the second semiconductor layer.

[0009] In some embodiments, carrier mobility of the second semiconductor layer is greater than carrier mobility of the first semiconductor layer.

[0010] In some embodiments, the material of the second semiconductor layer includes diamond.

[0011] In some embodiments, the first semiconductor layer is a cubic crystal system.

[0012] In some embodiments, a concentration of dopant ions in the second semiconductor layer is greater than a concentration of dopant ions in the first semiconductor layer.

[0013] In some embodiments, the concentration of doping ions in the second semiconductor layer is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

[0014] In some embodiments, the second semiconductor layer includes a first sub-semiconductor layer, and the first sub-semiconductor layer is located on a sidewall of the trench.

[0015] In some embodiments, the second semiconductor layer further includes a second sub-semiconductor layer, the conductivity type of the second sub-semiconductor layer is the same as the conductivity type of the first sub-semiconductor layer, and the second sub-semiconductor layer is located on at least a portion of the bottom surface of the trench.

[0016] In some embodiments, the method further includes a well doping region located in the first semiconductor layer, wherein the well doping region is in contact with the first sub-semiconductor layer.

[0017] In some embodiments, the conductivity type of the first sub-semiconductor layer is the same as the conductivity type of the well doping region.

[0018] In some embodiments, it also includes:

[0019] A source doping region is located in the surface of the first semiconductor layer, wherein the source doping region is in contact with the well doping region and is in contact with the first sub-semiconductor layer.

[0020] In some embodiments, the source doping region includes a first-type sub-source doping region and a second-type sub-source doping region, the first-type sub-source doping region is in contact with the well doping region and the second semiconductor layer, and the second-type sub-source doping region is located on a side of the first-type sub-source doping region away from the second semiconductor layer;

[0021] The conductivity type of the first-type sub-source doping region is opposite to the conductivity type of the second semiconductor layer, and the conductivity type of the second-type sub-source doping region is the same as that of the second semiconductor layer.

[0022] In some embodiments, the gate structure includes:

[0023] a gate dielectric layer located on an inner wall of the trench, wherein the gate dielectric layer covers a surface of the second semiconductor layer;

[0024] A gate is located in the trench, and the gate covers the surface of the gate dielectric layer.

[0025] In some embodiments, the method further includes a shielding doping region located in the first semiconductor layer, wherein the shielding doping region is connected to the gate dielectric layer at the bottom of the trench.

[0026] In some embodiments, the conductivity type of the shielding doped region is opposite to the conductivity type of the first semiconductor layer.

[0027] In some embodiments, a concentration of doping ions in the shielding doping region is greater than a concentration of doping ions in the first semiconductor layer.

[0028] In some embodiments, the concentration of doping ions in the shielding doping region is 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

[0029] According to a second aspect of the present application, a method for preparing a transistor is provided, comprising:

[0030] forming a first semiconductor layer and a trench in the first semiconductor layer;

[0031] forming a second semiconductor layer at least located on a sidewall of the trench, wherein the crystal system of the second semiconductor layer is the same as that of the first semiconductor layer;

[0032] A gate structure is formed in the trench, wherein the gate structure is in contact with the second semiconductor layer.

[0033] In some embodiments, the step of forming a second semiconductor layer at least on the sidewall of the trench comprises:

[0034] depositing an initial second semiconductor layer in the trench and on the surface of the first semiconductor layer;

[0035] The initial second semiconductor layer on the surface of the first semiconductor layer is removed.

[0036] In some embodiments, the material of the initial second semiconductor layer includes diamond.

[0037] In some embodiments, the step of depositing an initial second semiconductor layer in the trench and on the surface of the first semiconductor layer comprises:

[0038] The initial second semiconductor layer is formed by microwave plasma chemical vapor deposition, and the initial second semiconductor layer is doped with doping ions.

[0039] In some embodiments, the concentration of doping ions in the initial second semiconductor layer is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

[0040] In some embodiments, the step of forming a second semiconductor layer at least partially located on the sidewall of the trench further comprises:

[0041] The initial second semiconductor layer at the bottom of the trench is removed to form the second semiconductor layer.

[0042] In some embodiments, the method further includes: forming a shielding doping region connected to the bottom of the trench in the first semiconductor layer, wherein the conductivity type of the shielding doping region is opposite to the conductivity type of the first semiconductor layer.

[0043] In some embodiments, the concentration of doping ions in the shielding doping region is 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

[0044] In some embodiments, it also includes:

[0045] forming a well doping region in the first semiconductor layer, wherein the well doping region contacts the second semiconductor layer on the sidewall of the trench;

[0046] A source doping region is formed on a side of the well doping region close to the surface of the first semiconductor layer.

[0047] According to a third aspect of the present application, a power device is provided, comprising the transistor described in any of the above embodiments.

[0048] According to a fourth aspect of the present application, a vehicle is also provided, comprising the power device as described above.

[0049] The transistor of the embodiment of the present application includes a first semiconductor layer, a trench in the first semiconductor layer, a second semiconductor layer at least on the sidewall of the trench, and a gate structure in the trench and in contact with the second semiconductor layer. The crystal system of the second semiconductor layer is the same as that of the first semiconductor layer, so the second semiconductor layer is formed at least on the sidewall of the trench, which can reduce the crystal defects of the first semiconductor layer at the sidewall of the trench, thereby improving the consistency of the trench, improving the stability of the gate structure, and thus improving the performance and reliability of the device.

[0050] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0052] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0053] Figure 1 A schematic diagram of a cross-sectional structure of a transistor provided in some embodiments of the present application;

[0054] Figure 2 is a schematic diagram of a cross-sectional structure of a transistor provided in some embodiments of the present application;

[0055] Figure 3 is a schematic flow chart of a method for preparing a transistor provided in some embodiments of the present application;

[0056] Figures 4 to 15 is a schematic diagram of the structure of a transistor during the preparation process provided by some embodiments of the present application;

[0057] Figure 16 to Figure 19 It is a schematic diagram of the structure of the transistor during the preparation process provided in some embodiments of the present application. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0059] This application provides a transistor, see Figure 1 , Figure 1 A schematic diagram of the cross-sectional structure of a transistor provided in some embodiments of the present application.

[0060] The transistor 100 includes a first semiconductor layer 10, a trench 11 in the first semiconductor layer 10, a second semiconductor layer 20 at least on the sidewall of the trench 11, and a gate structure 30 in the trench 11 and in contact with the second semiconductor layer 20. The crystal system of the second semiconductor layer 20 is the same as that of the first semiconductor layer 10, so the second semiconductor layer 20 is formed at least on the sidewall of the trench 11, which can reduce the crystal defects of the first semiconductor layer 10 at the sidewall of the trench 11, thereby improving the consistency of the trench 11, improving the stability of the gate structure 30, and thus improving the performance and reliability of the device.

[0061] In some embodiments, the groove 11 is exposed to the surface 101 of the first semiconductor layer 10. The surface 101 of the first semiconductor layer 10 may be Figure 1 The upper surface of the first semiconductor layer 10, that is, the groove 11 extends downward from the upper surface of the first semiconductor layer 10 (the other surface opposite to the surface 101). Figure 1 The up-down direction shown is the stacking direction of the film layers, for example, the stacking direction of the gate structure 30 and the second semiconductor layer 20 .

[0062] The material of the first semiconductor layer 10 may include silicon carbide, and the groove 11 may be obtained by etching the first semiconductor layer 10 .

[0063] like Figure 1 As shown, the size of the trench 11 along the stacking direction is smaller than the size of the first semiconductor layer 10 along the stacking direction. The trench 11 includes a bottom and a sidewall connected to the bottom. The present application does not limit the shape of the trench 11.

[0064] In some embodiments, the gate structure 30 includes a gate dielectric layer 31 and a gate 32, wherein the gate dielectric layer 31 is located on the inner wall of the trench 11, and the gate dielectric layer 31 covers the surface of the second semiconductor layer 20; the gate 32 is located in the trench 11, and the gate 32 covers the surface of the gate dielectric layer 31. Therefore, the gate 32 is located in the trench 11 to form a vertical gate, and the gate dielectric layer 31 can isolate the first semiconductor layer 10 and the gate 32.

[0065] In some embodiments, the conductivity type of the second semiconductor layer 20 is opposite to that of the first semiconductor layer 10, thereby forming a PN junction. The concentration of doped ions in the second semiconductor layer 20 may be greater than the concentration of doped ions in the first semiconductor layer 10, so that the second semiconductor layer 20 of opposite conductivity type can be formed on the first semiconductor layer 10, and will not be compensated by the first semiconductor layer 10 to cause the conductivity type of the second semiconductor layer 20 to be the same as that of the first semiconductor layer 10.

[0066] For example, the concentration of doped ions in the first semiconductor layer 10 is 1e 14 atoms / cm 3 ~1e 16 atoms / cm 3 , the concentration of doped ions in the second semiconductor layer is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

[0067] In some embodiments, the second semiconductor layer 20 includes a first sub-semiconductor layer 21, and the first sub-semiconductor layer 21 is located on the sidewall of the trench 11. The first sub-semiconductor layer 21 can reduce crystal defects on the sidewall of the trench 11, reduce roughness, and improve interface scattering, thereby improving carrier mobility and device reliability.

[0068] In some embodiments, the second semiconductor layer 20 further includes a second sub-semiconductor layer 22, the conductivity type of the second sub-semiconductor layer 22 is the same as the conductivity type of the first sub-semiconductor layer 21, and the second sub-semiconductor layer 22 is located on at least a portion of the bottom surface of the trench 11. Therefore, crystal defects on the sidewalls and at least a portion of the bottom surface of the trench 11 can be reduced, thereby improving the performance of the device.

[0069] The transistor 100 may further include a well doped region 40 located in the first semiconductor layer 10, and the well doped region 40 is connected to the first sub-semiconductor layer 21. Therefore, under the control of the gate 32, a channel may be formed in the first sub-semiconductor layer 21, and when the voltage of the gate 32 is large enough, part of the well doped region 40 may form a channel together with the first sub-semiconductor layer 21. The channel is along the extension direction of the sidewall of the trench 11 (i.e., the stacking direction), in other words, the channel is a vertical channel, so that the device density can be improved.

[0070] Specific examples, such as Figure 1 As shown, the well doping region 40 is located on the left and right sides of the groove 11, and the side of the well doping region 40 away from the surface 101 of the first semiconductor layer 10 is lower than (or flush with) the bottom side of the groove 11, and the side of the well doping region 40 close to the surface 101 of the first semiconductor layer 10 is higher than (or flush with) the top side of the groove 11.

[0071] Understandably, Figure 1 The side of the middle well doped region 40 away from the surface 101 of the first semiconductor layer 10 is the bottom side. Figure 1The side of the well doped region 40 close to the surface 101 of the first semiconductor layer 10 is the top side. This means that the well doped region 40 has a side close to the surface 101 of the first semiconductor layer 10 and a side far from the surface 101 of the first semiconductor layer 10, and these two sides are generally opposite, and the close side is the side closer to the surface 101 of the first semiconductor layer 10, and the far side is the side far from the surface 101 of the first semiconductor layer 10. Both "far away" and "close" in this article can be understood similarly.

[0072] In some embodiments, the conductivity type of the first semiconductor sub-layer 21 is the same as the conductivity type of the well doping region 40, for example, both are N-type or both are P-type. In this way, the carriers (for example, electrons) in the channel can flow along the direction of the channel (that is, the extension direction of the sidewall of the trench 11) as much as possible, and will not flow in other directions to affect the performance of the device.

[0073] Specifically, when the conductivity type of the first semiconductor layer 10 is N-type, the conductivity type of the well doping region 40 is P-type, and the conductivity type of the second semiconductor layer 20 is also P-type, an N-metal-oxide-semiconductor (NMOS) can be formed. When the conductivity type of the first semiconductor layer 10 is P-type, the conductivity type of the well doping region 40 is N-type, and the conductivity type of the second semiconductor layer 20 is also N-type, a P-metal-oxide-semiconductor (NMOS) can be formed.

[0074] In some embodiments, the carrier mobility of the second semiconductor layer 20 is greater than the carrier mobility of the first semiconductor layer 10. Since the material of the well doping region 40 is the same as that of the first semiconductor layer 10, the mobility of the first sub-semiconductor layer 21 is greater than the carrier mobility of the well doping region 40, so the channel mobility can be further improved, thereby improving the device performance.

[0075] In some embodiments, the material of the second semiconductor layer 20 includes diamond, and the carrier mobility of diamond is greater than the carrier mobility of silicon carbide (an exemplary material of the first semiconductor layer 10), so the channel mobility can be improved.

[0076] Since diamond is a cubic crystal, when the first semiconductor layer 10 is made of SiC, cubic SiC can also be used. In this way, the two have the same crystal system type, and diamond can better repair defects on the surface of the groove 11 to further improve the performance of the device.

[0077] The transistor 100 may further include a third semiconductor layer 50, the third semiconductor layer 50 is located on a side of the first semiconductor layer 10 away from the second semiconductor layer 20, and the conductivity type of the third semiconductor layer 50 is the same as the conductivity type of the first semiconductor layer 10. For example, when the conductivity type of the first semiconductor layer 10 is N-type, the conductivity type of the third semiconductor layer 50 is also N-type. The third semiconductor layer 50 may be made of the same material as the first semiconductor layer 10, for example, both are SiC.

[0078] The third semiconductor layer 50 can be used as a substrate for the supporting structure. In some embodiments, the concentration of doped ions in the third semiconductor layer 50 is greater than the concentration of doped ions in the first semiconductor layer 10. Since the lower the concentration, the wider the width of the depletion layer, and the greater the reverse withstand voltage capability, the first semiconductor layer 10 mainly plays the role of bearing the reverse withstand voltage, thereby improving the reliability of the device.

[0079] Specifically, the concentration of doped ions in the third semiconductor layer 50 is 1e 19 atoms / cm 3 ~1e 22 atoms / cm 3 , which can play a good role in reverse voltage resistance.

[0080] The transistor 100 may further include a drain layer 60 , wherein the drain layer 60 is located on a side of the third semiconductor layer away from the first semiconductor layer 10 .

[0081] The transistor 100 may further include a source doping region 70 and a source layer 80, wherein the source doping region 70 is located in the surface 101 of the first semiconductor layer 10, and the source doping region 70 is in contact with the well doping region 40 and the first sub-semiconductor layer 21. Therefore, the source doping region 70 serves as a common source contact region of the well doping region 40 and the first sub-semiconductor layer 21. The source layer 80 is located on the surface 101 of the first semiconductor layer 10, and the source layer 80 is connected to the source doping region 70.

[0082] In some embodiments, the source doping region 70 is heavily doped, thereby reducing the contact resistance and improving the conductivity. The well doping region 40 and the first sub-semiconductor layer 21 are lightly doped, thereby meeting the electrical requirements of their channels. In other words, the concentration of doped ions in the well doping region 40 is less than the concentration of doped ions in the source doping region 70, and the concentration of doped ions in the first sub-semiconductor layer 21 is less than the concentration of doped ions in the source doping region 70. The concentration range of doped ions in the first sub-semiconductor layer 21 can be the same as the concentration range of doped ions in the well doping region 40, which is conducive to maintaining the characteristics of the channel.

[0083] In some embodiments, the source doping region 70 is located on a side of the well doping region 40 close to the surface 101 of the first semiconductor layer 10, and includes a first-type sub-source doping region 71 and a second-type sub-source doping region 72, wherein the second-type sub-source doping region 72 is located on a side of the first-type sub-source doping region 71 away from the second semiconductor layer 20 (i.e. Figure 1 on the left side of the image).

[0084] The conductivity type of the first-type sub-source doping region 71 is opposite to that of the second semiconductor layer 20, and the conductivity type of the second-type sub-source doping region 72 is the same as that of the second semiconductor layer 20. The first-type sub-source doping region 71 serves as a common source contact region for the well doping region 40 and the first sub-semiconductor layer 21, while the second-type sub-source doping region 72 can reduce resistance and prevent transistor conduction.

[0085] For example, the conductivity type of the second semiconductor layer 20 and the second type sub-source doping region 72 is P type, and the conductivity type of the first type sub-source doping region 71 is N type. When the gate 32 is applied with a control voltage, electrons flow from the first type sub-source doping region 71 to the first semiconductor layer 10 via the first sub-semiconductor layer 21, and then flow to the drain layer 60.

[0086] It can be understood that the side of the well doping region 40 close to the surface 101 of the first semiconductor layer 10 is the upper side of the well doping region 40, which means that the well doping region 40 has a side close to the surface 101 of the first semiconductor layer 10 and a side far from the surface 101 of the first semiconductor layer 10, and generally the two are opposite, and the close side is the side closer to the surface 101 of the first semiconductor layer 10, and the far side is the side far from the surface 101 of the first semiconductor layer 10. The "close" in this article can be understood similarly.

[0087] like Figure 1 As shown, the second semiconductor layer 20 includes an end portion 201 close to the surface 101 of the first semiconductor layer 10, and the first type sub-source doping region 71 covers the end portion 201. In this way, the first type sub-source doping region 71 utilizes part of the space of the second semiconductor layer 20, increases the area of ​​the source doping region 70, thereby further reducing the resistance of the source doping region 70, and does not affect the contact area between the well doping region 40 and the second semiconductor layer 20. The first type sub-doping region may include a first portion and a second portion, the first portion is located on the well doping region 40, and its material is the same as that of the first semiconductor layer 10, and the second portion covers the end portion 201 of the second semiconductor layer 20, and its material is the same as that of the second semiconductor layer 20.

[0088] The transistor 100 may further include an isolation layer 90 located between the source layer 80 and the gate structure 30 to achieve electrical isolation between the source layer 80 and the gate structure 30. The isolation layer 90 may be an insulating layer such as an oxide.

[0089] See also Figure 2 , Figure 2 2 is a schematic diagram of a cross-sectional structure of a transistor provided in some embodiments of the present application. The main difference between this embodiment and the above embodiments is the position of the second semiconductor layer 20A.

[0090] In the transistor 200, the second semiconductor layer 20A is only located on the sidewall of the trench 11, that is, the second semiconductor layer 20A only includes the first sub-semiconductor layer 21, and the gate dielectric layer 31 is connected to the second semiconductor layer 20A and the bottom of the trench 11. Figure 1 The space of the second semiconductor layer 22 in the Figure 2 The gate 32 in the trench 11 can form a vertical gate with a greater depth, thereby improving the control capability of the gate 32. In addition, there is no second sub-semiconductor layer 22 connecting the two first sub-semiconductor layers 21 on the sidewalls of the trench 11, that is, the two first sub-semiconductor layers 21 are separated from each other, which can prevent electrons from flowing along the second sub-semiconductor layer 22 and affecting the mobility of the channel.

[0091] In some embodiments, the transistor 200 further includes a shielding doping region 110 located in the first semiconductor layer 10, and the shielding doping region 110 is connected to the gate dielectric layer 31 at the bottom of the trench 11. Since the gate dielectric layer 31 is connected to the bottom of the trench 11, the shielding doping region 110 is connected to the gate dielectric layer 31, which can shield the electric field of the oxide layer of the gate 32 and reduce the electric field strength of the gate dielectric layer 31.

[0092] In some embodiments, the conductivity type of the shielding doping region 110 is the same as the conductivity type of the second-type sub-source doping region 72, and the concentration of doping ions in the shielding doping region 110 is the same as the concentration of doping ions in the second-type sub-source doping region 72. Therefore, the shielding doping region 110 can be formed together with the second-type sub-source doping region 72 through an ion implantation process, thereby reducing the process and cost.

[0093] In some embodiments, the conductivity type of the shielding doping region 110 is opposite to the conductivity type of the first semiconductor layer 10. When the conductivity type of the first semiconductor layer 10 is N-type, the conductivity type of the shielding doping region 110 may be P-type, so that a PN junction may be formed between the shielding doping region 110 and the first semiconductor layer 10, thereby transferring the electric field to the PN junction and reducing the electric field strength of the gate dielectric layer 31.

[0094] In some embodiments, the concentration of doped ions in the shielding doping region 110 is greater than the concentration of doped ions in the first semiconductor layer 10. When a large reverse voltage is applied to the drain layer 60, an electric field is formed to form a depletion layer. The large concentration of doped ions in the shielding doping region 110 can make the depletion layer of the shielding doping region 110 narrow and the depletion layer of the first semiconductor layer 10 wide, thereby improving the protection effect of the gate dielectric layer 31.

[0095] In some embodiments, the concentration of doping ions in the shielding doping region 110 is 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

[0096] According to a second aspect of the present application, a method for preparing a transistor is provided. Figure 3 , Figure 3 1 is a schematic flow chart of a method for preparing a transistor provided in some embodiments of the present application, the method comprising:

[0097] Step S1: forming a first semiconductor layer and a trench in the first semiconductor layer;

[0098] Step S2: forming a second semiconductor layer at least located on the sidewall of the trench, wherein the crystal system of the second semiconductor layer is the same as that of the first semiconductor layer;

[0099] Step S3: forming a gate structure in the trench, wherein the gate structure is in contact with the second semiconductor layer.

[0100] In the transistor manufacturing method, since the second semiconductor layer is formed at least on the sidewall of the trench, the crystal defects on the sidewall of the trench can be repaired, thereby improving the consistency of the trench, improving the stability of the gate structure, and thus improving the performance and reliability of the device.

[0101] Please also see Figures 4 to 15 , Figures 4 to 15 is a schematic diagram of the structure of the transistor provided in some embodiments of the present application during the preparation process. This embodiment takes the preparation of the above-mentioned transistor 100 as an example to illustrate the preparation method, so it can be combined with reference to Figure 1 The method for manufacturing the transistor 100 includes the following steps S1-S3.

[0102] Step S1: forming a first semiconductor layer 10 and a groove 11 located in the first semiconductor layer 10. Figure 4 and Figure 5 .

[0103] like Figure 4As shown, a semiconductor material SiC may be provided, and a plasma implantation process may be used to form a third semiconductor layer 50 and a first semiconductor layer 10, wherein the first semiconductor layer 10 is located above the third semiconductor layer 50, and the concentration of the first semiconductor layer 10 is less than that of the third semiconductor layer 50. The first semiconductor layer 10 has a surface 101.

[0104] like Figure 5 As shown, a hard mask is used for shielding to etch the first semiconductor layer 10-shaped groove 11. The etching process may be inductively coupled plasma (ICP) etching or reactive ion etching (RIE).

[0105] Step S2: forming a second semiconductor layer 20 at least on the sidewall of the trench 11, wherein the crystal system of the second semiconductor layer 20 is the same as that of the first semiconductor layer 10. Figure 6-7 .

[0106] like Figure 6 As shown, a microwave plasma chemical vapor deposition method can be used to deposit an initial second semiconductor layer 20' on the surface 101 of the first semiconductor layer 10 and the bottom and sidewalls of the trench 11. The initial second semiconductor layer 20' is doped with doping ions. For example, the initial second semiconductor layer 20' can be p-type diamond; Figure 7 As shown, the initial second semiconductor layer 20' on the surface 101 of the first semiconductor layer 10 is then removed to form the second semiconductor layer 20. The microwave plasma chemical vapor deposition method can dope while depositing so that the initial second semiconductor layer 20' is doped with doping ions. In another embodiment, the initial second semiconductor layer 20' can also be formed by a process of first depositing and then doping.

[0107] In some embodiments, the concentration of doping ions in the initial second semiconductor layer 20' is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

[0108] Since the deposition method is used to perform epitaxy on the etched semiconductor surface (and the inner wall of the groove 11), the surface defects caused by etching are modified, thereby improving the consistency and stability of the trench SiC MOSFET, reducing interface scattering, and improving channel mobility. When the crystal form of the first semiconductor layer 10 on the inner wall of the groove 11 is the same as the crystal form of the second semiconductor layer 20, it is more conducive to repairing the defects on the inner wall of the groove 11, that is, the crystal quality, atomic ordering, roughness, etc. are greatly improved.

[0109] See also Figure 8 to Figure 10 The method for preparing the transistor 100 may further include the following steps.

[0110] 1) If Figure 8 As shown, a well doping region 40 is formed in the first semiconductor layer 10, and the well doping region 40 is connected to the second semiconductor layer 20 on the sidewall of the trench 11. Specifically, a hard mask can be used for shielding, and ion implantation can be performed on the left and right sides of the trench 11 to form the well doping region 40.

[0111] 2) If Figures 9-10 As shown, a source doping region 70 is formed on the side of the well doping region 40 close to the surface 101 of the first semiconductor layer 10. Specifically, a first-type sub-source doping region 71 can be formed by ion implantation above the second well doping region 40, and a second-type sub-source doping region 72 can be formed by ion implantation above the second well doping region 40, and the second-type sub-source doping region 72 is located on the side of the first-type sub-source doping region away from the second semiconductor layer 20.

[0112] 3) A carbon film is formed on the upper surface of the first semiconductor layer 10 and high temperature annealing is performed to activate the implanted ions, and the carbon film is removed after the annealing is completed. The carbon film can protect the first semiconductor layer 10 from damage during the high temperature annealing process.

[0113] Step S3: forming a gate structure 30 in the trench 11. Figure 11 to Figure 13 .

[0114] like Fig.11 As shown, a high-k dielectric layer 31' can be formed on the upper surface of the first semiconductor layer 10 and the bottom and sidewalls of the trench 11; Fig.12 As shown, the high-k dielectric layer 31' on the upper surface of the first-type sub-source doping region 71 and the second-type sub-source doping region 72 is removed, leaving the high-k dielectric layer 31' at the bottom and sidewall of the trench 11 as the gate dielectric layer 31; Fig.13 As shown, the remaining gap of the trench 11 is filled with a gate metal 32 (eg, tungsten, etc.) to form the gate 32 .

[0115] The manufacturing method of the transistor 100 may further include: 1) referring to Fig.14 , depositing an isolation layer 90 on the first semiconductor layer 10 and on the gate 32; 2) see Fig.15 , forming a source metal on the upper surface of the first type sub-source doping region 71 and the second type sub-source doping region 72 to form a source layer 80; 3) referring to Figure 1 , a drain metal is prepared under the first semiconductor layer 10 to form a drain layer 60 .

[0116] See also Figure 16 to Figure 19 , Figure 16 to Figure 19is a schematic diagram of the structure of the transistor provided in some embodiments of the present application during the preparation process. Figure 2 Taking the transistor 200 in FIG. 1 as an example, the preparation process of the second semiconductor layer 20A and the shielding doping region 110 is described in detail. The preparation process of other film layers can refer to Figures 4 to 6 as well as Figure 11 to Figure 15 .

[0117] and Figure 1 Different from the method for preparing the transistor 100, the method for preparing the second semiconductor layer 20A in the transistor 200 may further include: Figure 6 On the basis of, removing the initial second semiconductor layer 20' at the bottom of the trench 11, forming the second semiconductor layer 20A, see Fig.16 .

[0118] See also Fig.17 The process for preparing the well doping region 40 can refer to the process in the above embodiment. Figure 8 Description of

[0119] The difference is that in this embodiment, during the process of forming the source doping region 70 on the side of the well doping region 40 close to the surface 101 of the first semiconductor layer 10, a shield doping region 110 is formed in the first semiconductor layer 10 at the bottom of the trench 11, and the concentration of doping ions in the shield doping region can be 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

[0120] For specific examples, see Fig.18 , a first type sub-source doping region 71 is formed separately, and the process for preparing the well doping region 40 and the first type sub-source doping region 71 can refer to the process in the above embodiment. Fig. 9 Related descriptions. Fig.19 As shown, the shielding doping region 110 is formed in the process of forming the second type sub-source doping region 72, so that the electric field of the gate dielectric layer 31 can be reduced without increasing the process.

[0121] exist Fig.19 After forming the gate structure 30, the isolation layer 90, the source layer 80 and the drain layer 60, the final structure can be referred to Figure 2 .

[0122] The transistor manufacturing method provided in the embodiment of the present application can at least repair the sidewall crystal defects of the trench 11, thereby improving the consistency of the trench 11, improving the stability of the gate structure 30, and improving the channel mobility, thereby improving the performance and reliability of the device.

[0123] According to the third aspect of the present application, a power device is provided, the power device comprising the transistor in any of the above embodiments, the power device having all the beneficial effects of the above transistor, which will not be described in detail in the present application. The power device can be applied to a transformer or other electric drive device of a vehicle.

[0124] According to a fourth aspect of the present application, a vehicle is provided, which includes a power device in any one of the above embodiments. The vehicle has all the beneficial effects of the above power devices, which will not be described in detail in the present application.

[0125] The vehicle may be a fuel vehicle, a plug-in hybrid vehicle or a new energy vehicle, etc., and this application does not make any specific limitation on this.

[0126] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0127] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0129] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A transistor, characterized in that: include: a first semiconductor layer and a trench located in the first semiconductor layer; a second semiconductor layer at least located on a sidewall of the trench, wherein the crystal system of the second semiconductor layer is the same as that of the first semiconductor layer; A gate structure is located in the trench, and the gate structure is in contact with the second semiconductor layer.

2. The transistor according to claim 1, characterized in that The carrier mobility of the second semiconductor layer is greater than the carrier mobility of the first semiconductor layer.

3. The transistor according to claim 2, characterized in that The material of the second semiconductor layer includes diamond.

4. The transistor according to any one of claims 1 to 3, characterized in that: The first semiconductor layer is a cubic crystal system.

5. The transistor according to claim 1, characterized in that The concentration of doped ions in the second semiconductor layer is greater than the concentration of doped ions in the first semiconductor layer.

6. The transistor according to claim 1 or 5, characterized in that: The concentration of doped ions in the second semiconductor layer is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

7. The transistor according to claim 1, characterized in that The second semiconductor layer includes a first sub-semiconductor layer, and the first sub-semiconductor layer is located on a sidewall of the trench.

8. The transistor according to claim 7, characterized in that The second semiconductor layer further includes a second sub-semiconductor layer, the conductivity type of the second sub-semiconductor layer is the same as the conductivity type of the first sub-semiconductor layer, and the second sub-semiconductor layer is located on at least a portion of the bottom surface of the trench.

9. The transistor according to claim 7, characterized in that It also includes a well doping region located in the first semiconductor layer, wherein the well doping region is in contact with the first sub-semiconductor layer.

10. The transistor according to claim 9, characterized in that The conductivity type of the first sub-semiconductor layer is the same as the conductivity type of the well doping region.

11. The transistor according to claim 9, characterized in that Also includes: A source doping region is located in the surface of the first semiconductor layer, wherein the source doping region is in contact with the well doping region and is in contact with the first sub-semiconductor layer.

12. The transistor according to claim 11, characterized in that The source doping region comprises a first-type sub-source doping region and a second-type sub-source doping region, the first-type sub-source doping region is in contact with the well doping region and the second semiconductor layer, and the second-type sub-source doping region is located on a side of the first-type sub-source doping region away from the second semiconductor layer; The conductivity type of the first-type sub-source doping region is opposite to the conductivity type of the second semiconductor layer, and the conductivity type of the second-type sub-source doping region is the same as that of the second semiconductor layer.

13. The transistor according to claim 1, characterized in that The gate structure comprises: a gate dielectric layer located on an inner wall of the trench, wherein the gate dielectric layer covers a surface of the second semiconductor layer; A gate is located in the trench, and the gate covers the surface of the gate dielectric layer.

14. The transistor according to claim 13, characterized in that It also includes a shielding doping region located in the first semiconductor layer, and the shielding doping region is connected to the gate dielectric layer at the bottom of the trench.

15. The transistor according to claim 14, characterized in that The conductivity type of the shielding doping region is opposite to the conductivity type of the first semiconductor layer.

16. The transistor according to claim 14, characterized in that The concentration of doping ions in the shielding doping region is greater than the concentration of doping ions in the first semiconductor layer.

17. The transistor according to claim 1 or 16, characterized in that: The concentration of doping ions in the shielding doping region is 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

18. A method for preparing a transistor, characterized in that: include: forming a first semiconductor layer and a trench in the first semiconductor layer; forming a second semiconductor layer at least located on a sidewall of the trench, wherein the crystal system of the second semiconductor layer is the same as that of the first semiconductor layer; A gate structure is formed in the trench, wherein the gate structure is in contact with the second semiconductor layer.

19. The method for preparing a transistor according to claim 18, characterized in that: The step of forming a second semiconductor layer at least on the sidewall of the trench comprises: depositing an initial second semiconductor layer in the trench and on the surface of the first semiconductor layer; The initial second semiconductor layer on the surface of the first semiconductor layer is removed.

20. The method for preparing a transistor according to claim 19, characterized in that: The material of the initial second semiconductor layer includes diamond.

21. The method for preparing a transistor according to claim 19, characterized in that: The step of depositing an initial second semiconductor layer in the groove and on the surface of the first semiconductor layer comprises: The initial second semiconductor layer is formed by microwave plasma chemical vapor deposition, and the initial second semiconductor layer is doped with doping ions.

22. The method for preparing a transistor according to claim 21, characterized in that: The concentration of doped ions in the initial second semiconductor layer is 1e 17 atoms / cm 3 ~1e 18 atoms / cm 3 .

23. The method for preparing a transistor according to claim 19, characterized in that: The step of forming a second semiconductor layer at least partially located on the sidewall of the trench further comprises: The initial second semiconductor layer at the bottom of the trench is removed to form the second semiconductor layer.

24. The method for preparing a transistor according to claim 18, characterized in that: Also includes: A shielding doping region connected to the bottom of the trench is formed in the first semiconductor layer, and the conductivity type of the shielding doping region is opposite to the conductivity type of the first semiconductor layer.

25. The method for preparing a transistor according to claim 24, characterized in that: The concentration of doping ions in the shielding doping region is 1e 18 atoms / cm 3 ~1e 20 atoms / cm 3 .

26. The method for preparing a transistor according to claim 18, characterized in that: Also includes: forming a well doping region in the first semiconductor layer, wherein the well doping region contacts the second semiconductor layer on the sidewall of the trench; A source doping region is formed on a side of the well doping region close to the surface of the first semiconductor layer.

27. A power device, characterized in that: A transistor comprising any one of claims 1 to 17.

28. A vehicle, characterized in that: Comprising the power device as claimed in claim 27.

Images