High-reliability SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method

Abstract

The invention relates to the technical field of semiconductors, in particular to a high-reliability SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, and the device comprises a silicon carbide wafer, two gate regions, two doped regions and a mixed PIN Schottky diode (MPS) region, the two gate regions are located on the silicon carbide wafer; the two doped regions are located on the silicon carbide wafer and are correspondingly located on the far sides of the two gate regions respectively, and the far sides are the sides, far away from the other gate region, of the gate regions; the MPS region is located on the silicon carbide wafer and located between the two gate regions, and is used for improving the surge resistance of the device while avoiding the bipolar degeneration effect of the device. According to the device, the limit overcurrent capability of the device is enhanced, the reliability under an extreme surge condition is improved, meanwhile, the gate oxide layer of the device is protected, the service life of the gate oxide layer is prolonged, the long-term reliability of the gate oxide layer is improved, and the loss of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-reliability SiC MOSFET device and a manufacturing method thereof. Background Art

[0002] Silicon carbide SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have a series of outstanding advantages such as large bandgap, high critical breakdown electric field, fast electron saturation drift velocity, and high thermal conductivity, making them have great potential in high voltage, high temperature, and high frequency applications. Especially in the fields of new energy vehicles, photovoltaic energy storage, and charging piles that have emerged in recent years, SiC MOSFET devices are becoming increasingly important.

[0003] When replacing high-voltage silicon-based power devices IGBT, SiC MOSFET does not necessarily require anti-parallel FRD freewheeling, but in areas such as automotive grade with high requirements, anti-parallel freewheeling diodes are usually integrated inside SiC MOSFET chips or in modules to avoid the "bipolar degradation effect" caused by the SiC MOSFET body diode being forward-conducted for a long time. This effect is mainly triggered by the basal plane dislocations that existed earlier on the SiC crystal during bipolar operation, and as the bipolar operation time increases, the on-resistance (Ron) and forward conduction voltage drop (VF) of the SiC MOSFET gradually increase. However, existing SiC MOSFET devices with integrated diodes are extremely easy to be damaged when encountering occasional surge currents, resulting in low reliability of existing SiC MOSFET devices. Summary of the invention

[0004] The embodiments of the present application solve the technical problem of low reliability of SiC MOSFET devices in the prior art by providing a high-reliability SiC MOSFET device and a manufacturing method, thereby enhancing the ultimate overcurrent capability of the device and improving the reliability under extreme surge conditions. At the same time, the gate oxide layer of the device is protected, the service life of the gate oxide layer is extended, the long-term reliability of the gate oxide layer is improved, and the device loss is reduced, etc.

[0005] In a first aspect, an embodiment of the present invention provides a high-reliability SiC MOSFET device, comprising: a silicon carbide wafer, two gate regions, two doping regions, and a hybrid PIN Schottky diode region MPS region; The two gate regions are located on the silicon carbide wafer; The two doping regions are located on the silicon carbide wafer and are respectively located on the far side of the two gate regions, where the far side is a side of the gate region away from the other gate region; The MPS region is located on the silicon carbide wafer and between the two gate regions, and is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

[0006] Optionally, the MPS region includes: a first target P+ region, a second target P+ region and a doping adjustment region, wherein the size of the second target P+ region is larger than that of the first target P+ region; The first target P+ region is correspondingly located at an adjacent side of each of the gate regions, and the adjacent side is a side of the gate region adjacent to another gate region; The second target P+ region is located between the first target P+ regions; The doping adjustment region is located between the first target P+ region and the second target P+ region.

[0007] Optionally, the conductivity type of the doping adjustment region is N-type or P-type.

[0008] Optionally, it also includes: a source metal layer; the source metal layer is located on the silicon carbide wafer and covers the gate area, the doping area and the MPS area, wherein the first target P+ area and the second target P+ area form an ohmic contact with the source metal layer, and the doping adjustment area forms a Schottky contact with the source metal layer.

[0009] Optionally, each gate region includes: a gate oxide layer, a gate polysilicon layer and a dielectric layer; The gate oxide layer is located on the silicon carbide wafer; The gate polysilicon is located on the gate oxide layer; The dielectric layer wraps the gate polysilicon and the gate oxide layer.

[0010] Optionally, each of the doped regions includes: a P-well region, a P+ region and an N+ region; The P-well region is located in the silicon carbide wafer; The P+ region and the N+ region are located in the P-well region, the N+ region is correspondingly located on the side away from the gate region, and the P+ region contacts the side of the N+ region away from the gate region, wherein the surfaces of the P-well region, the P+ region and the N+ region are located on the same horizontal plane as the surface of the silicon carbide wafer.

[0011] Optionally, the silicon carbide wafer includes: an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer, and the N-type silicon carbide epitaxial layer is located on the N-type silicon carbide substrate.

[0012] Optionally, it also includes: a current spreading layer, the current spreading layer is located in the N-type silicon carbide epitaxial layer, and the surface of the current spreading layer and the surface of the N-type silicon carbide epitaxial layer are located in the same horizontal plane, and the doping region and the MPS region are located on the current spreading layer.

[0013] Optionally, it also includes: a drain metal layer, wherein the drain metal layer is located under the N-type silicon carbide substrate.

[0014] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a high-reliability SiC MOSFET device, which is used to manufacture the high-reliability SiC MOSFET device described in the first aspect, and the method comprises: forming two gate regions on the silicon carbide wafer; A doping region is formed on each of the two gate regions at a far side, wherein the far side is a side of the gate region away from the other gate region; A hybrid PIN Schottky diode region MPS region is formed on the silicon carbide wafer and between the two gate regions, wherein the MPS region is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: The embodiment of the present invention separates the gate structure, that is, sets a hybrid PIN Schottky diode MPS region between the gate regions, to avoid the "bipolar degradation effect" caused by long-term forward conduction of the device. At the same time, during the reverse withstand voltage process of the device, the MPS region set between the gate regions widens the depletion layer between the doped region and the epitaxial layer of the silicon carbide wafer, shields the Schottky junction of the Schottky contact region of the MPS region, and reduces reverse leakage. In addition, the design of the MPS region of the embodiment of the present invention makes the strong electric field of the gate oxide (i.e., the gate oxide layer) of the gate region near the MPS structure move down to the epitaxial layer with a higher critical breakdown field strength, thereby improving the long-term reliability of the gate oxide of the gate region and reducing device loss. During the forward conduction of the device, under the condition of small current (i.e., the normal working state of the device), only the Schottky contact region in the MPS region passes current; while under the condition of abnormally large current (such as surge current, etc.), the PIN diode in the MPS region and the Schottky contact region pass current together, thereby improving the reliability of the device under extreme surge conditions, improving the device's limit overcurrent capability, and reducing device loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings: Figure 1 A schematic structural diagram of a high-reliability SiC MOSFET device in an embodiment of the present invention is shown; Figure 2a The electric field intensity distribution diagram of the conventional split-gate integrated SBD structure SiC MOSFET device in the embodiment of the present invention is shown; Figure 2b The electric field intensity distribution diagram of the high reliability silicon carbide SiC MOSFET device in the embodiment of the present invention is shown; Figure 3 A schematic diagram showing the flow direction of the current path in different situations in the embodiment of the present invention is shown; Figure 4a shows a current-voltage curve diagram of a SiC MOSFET device with different MPS regions in an embodiment of the present invention; Figure 4b The embodiment of the present invention is shown Figure 4a A magnified view of the current-voltage curve of SiCMOSFET devices with different MPS zones under the BB' region; Figure 5 A schematic diagram of the structure of forming a P-well region and an N+ region on an N-type silicon carbide epitaxial layer in an embodiment of the present invention is shown; Figure 6 A schematic diagram of a structure for forming a doping adjustment region in an embodiment of the present invention is shown; Figure 7 A schematic diagram of the structure of forming a P+ region, a first target P+ region, and a second target P+ region in an embodiment of the present invention is shown; Figure 8 A schematic diagram of the structure of forming a current spreading layer in an embodiment of the present invention is shown; Fig. 9 A schematic diagram of the structure of forming a gate oxide layer and gate polysilicon in an embodiment of the present invention is shown; Fig.10 A schematic diagram of the structure of forming a dielectric layer and an ohmic contact region in an embodiment of the present invention is shown; Fig.11 A schematic diagram of the structure of forming a Schottky contact region in an embodiment of the present invention is shown; Fig.12 A schematic flow chart showing the steps of a method for manufacturing a high-reliability SiC MOSFET device in an embodiment of the present invention is shown; In the drawings, 110, silicon carbide wafer; 120, gate region; 130, doping region; 140, MPS region; 150, source metal layer; 160, drain metal layer; 111. N-type silicon carbide substrate; 112. N-type silicon carbide epitaxial layer; 113. current spreading layer; 121, gate oxide layer; 122, gate polysilicon; 123, dielectric layer; 131, P well region; 132, P+ region; 133, N+ region; 141. First target P+ region; 142. Second target P+ region; 143. Doping adjustment region; 144. Ohmic contact hole; 145. Schottky contact hole. DETAILED DESCRIPTION

[0017] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0018] Embodiment 1 The first embodiment of the present invention provides a high reliability silicon carbide SiC MOSFET device, such as Figure 1 As shown, it includes: a silicon carbide wafer 110, two gate regions 120, two doping regions 130 and a mixed PIN / Schottky diode (Merged Pin / Schottky diode) region MPS region 140. The two gate regions 120 are located on the silicon carbide wafer 110. The two doping regions 130 are located on the silicon carbide wafer 110 and correspond to the far side of the two gate regions 120, respectively, and the far side is the side of the gate region 120 away from the other gate region 120. The MPS region 140 is located on the silicon carbide wafer 110 and between the two gate regions 120, and is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

[0019] This embodiment separates the gate structure, that is, sets the hybrid PIN Schottky diode region MPS region 140 between the gate regions 120, so as to avoid the "bipolar degradation effect" caused by long-term forward conduction of the device. At the same time, during the reverse withstand voltage process of the device, the MPS region 140 set between the gate regions 120 widens the depletion layer between the doped region 130 and the epitaxial layer of the silicon carbide wafer 110, shields the Schottky junction of the Schottky contact region of the MPS region 140, and reduces reverse leakage. In addition, the design of the MPS region 140 of this embodiment makes the strong electric field of the gate oxide (i.e., the gate oxide layer 121) of the gate region 120 near the MPS structure move down to the epitaxial layer with a higher critical breakdown field strength, thereby improving the long-term reliability of the gate oxide of the gate region 120 and reducing device loss. During the forward conduction process of the device, under low current conditions (i.e., the normal working state of the device), only the Schottky contact area in the MPS area 140 passes current; while under abnormally large current conditions (such as surge current, etc.), the PIN diode in the MPS area 140 and the Schottky contact area pass current together, thereby improving the reliability of the device under extreme surge conditions, enhancing the device's ultimate overcurrent capability, and reducing device losses.

[0020] Next, combine Figure 1 The specific structure of the high-reliability silicon carbide SiC MOSFET device provided in this embodiment is introduced in detail: like Figure 1 As shown, the silicon carbide wafer 110 includes: an N-type silicon carbide substrate 111, an N-type silicon carbide epitaxial layer 112 and a current spreading layer 113. The N-type silicon carbide epitaxial layer 112 is located on the N-type silicon carbide substrate 111. The doping concentration of the N-type silicon carbide epitaxial layer 112 is lower than the doping concentration of the N-type silicon carbide substrate 111. The current spreading layer 113 is located in the N-type silicon carbide epitaxial layer 112, and the surface of the current spreading layer 113 is located at the same level as the surface of the N-type silicon carbide epitaxial layer 112. The doping region 130 and the MPS region 140 are located on the current spreading layer 113, which means that the doping region 130 and the MPS region 140 are both in the current spreading layer 113, and the surfaces of the doping region 130 and the MPS region 140 are located at the same level as the surface of the current spreading layer 113. The surface of the current spreading layer 113 (CSL) or the surface of the N-type silicon carbide epitaxial layer 112 is the surface of the silicon carbide wafer 110. The current spreading layer 113 CSL is introduced into the region between the doping regions 130 (i.e., the gate region 120 corresponds to the JFET region in the N-type silicon carbide epitaxial layer 112) by controlling the implantation dose and energy to reduce the on-resistance and forward conduction voltage drop of the device, thereby optimizing the loss of the device.

[0021] like Figure 1As shown, each gate region 120 on the silicon carbide wafer 110 includes: a gate oxide layer 121, a gate polysilicon 122 and a dielectric layer 123. The gate oxide layer 121 is located on the silicon carbide wafer 110. The gate polysilicon 122 is located on the gate oxide layer 121. The dielectric layer 123 wraps the gate polysilicon 122 and the gate oxide layer 121. The gate region 120 of this embodiment is a separated gate structure, that is, the entire gate is separated into two gate regions 120. The dielectric layer 123 is an ILD (Inter Layer Dielectric) dielectric layer. The ILD dielectric layer refers to a dielectric material formed between the device and the metal layer to form electrical isolation. The ILD dielectric layer can effectively reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field effect transistor formed by the metal crossing different regions. The two doping regions 130 are located on the silicon carbide wafer 110 and are respectively located at the far side of the two gate regions 120 . The far side of the gate region 120 is the side of the gate region 120 away from the other gate region 120 .

[0022] Specifically, in Figure 1 In the figure, two left and right gate regions 120 are provided on the silicon carbide wafer 110, which are respectively denoted as the left gate region and the right gate region. The left side of the left gate region is the side of the left gate region away from the right gate region, and the left side of the left gate region is the away side of the left gate region. The right side of the left gate region is the side of the left gate region close to or adjacent to the right gate region, and the right side of the left gate region is the adjacent side of the left gate region. Similarly, the right side of the right gate region is the side of the right gate region away from the left gate region, and the right side of the right gate region is the away side of the right gate region. The left side of the right gate region is the side of the right gate region close to or adjacent to the left gate region, and the left side of the right gate region is the adjacent side of the right gate region.

[0023] The two doping regions 130 are located in the current spreading layer 113 of the silicon carbide wafer 110, and the surfaces of the doping regions 130 and the current spreading layer 113 are located at the same level. The doping regions 130 are located at the far side of the gate region 120, such as Figure 1 As shown, the two doping regions 130 are respectively recorded as the left doping region and the right doping region. The left doping region corresponds to the far side of the left gate region (i.e., the left side of the left gate region), and the right doping region corresponds to the far side of the right gate region (i.e., the right side of the right gate region). In addition, the position area range of the doping region 130 may correspond to no more than half of the gate region 120 itself.

[0024] Each doping region 130 includes: a P-well region 131, a P+ region 132, and an N+ region 133. The P-well region 131 is located in the silicon carbide wafer 110, that is, the P-well region 131 is located in the current spreading layer 113. The P+ region 132 and the N+ region 133 are located in the P-well region 131. The N+ region 133 is correspondingly located on the side away from the gate region 120. The P+ region 132 contacts the side of the N+ region 133 away from the gate region 120, wherein the surfaces of the P-well region 131, the P+ region 132, and the N+ region 133 are located at the same level as the surface of the silicon carbide wafer 110.

[0025] Taking the left doping region as an example, the N+ region of the left doping region is located at the far side of the left gate region (i.e., the left side of the left gate region). The P+ region of the left doping region is located at the left side of the N+ region of the left doping region and contacts the left side of the N+ region of the left doping region. The structure of the right doping region is similar and will not be described here.

[0026] The MPS region 140 is located on the silicon carbide wafer 110 and between the two gate regions 120. The MPS region 140 includes: a first target P+ region 141, a second target P+ region 142 and a doping adjustment region 143. The size of the second target P+ region 142 is larger than the first target P+ region 141. The first target P+ region 141 is located at the adjacent side of each gate region 120, and the adjacent side is the side of the gate region 120 adjacent to another gate region 120. The second target P+ region 142 is located between the first target P+ region 141, and the doping adjustment region 143 is located between the first target P+ region 141 and the second target P+ region 142.

[0027] Specifically, the size of the second target P+ region 142 is larger than the first target P+ region 141, which means that the width of the second target P+ region 142 is larger than the width of the first target P+ region 141. The widths of the first target P+ region 141 and the second target P+ region 142 can be set according to actual needs. In the MPS region 140, the first target P+ region 141 can be called a small P+ region, and the second target P+ region 142 can be called a large P+ region.

[0028] Figure 1The MPS region 140 shown is the simplest MPS region 140, which includes: two first target P+ regions 141, one second target P+ region 142 and two doping adjustment regions 143. The two first target P+ regions 141 are respectively the left first target P+ region and the right first target P+ region. The left first target P+ region is located at the adjacent side of the left gate region (i.e., the right side of the left gate region), and the position area range of the left first target P+ region can be close to the range of the left gate region. Similarly, the right first target P+ region is located at the adjacent side of the right gate region (i.e., the left side of the right gate region), and the position area range of the right first target P+ region can be close to the range of the right gate region. The second target P+ region 142 is located between the two first target P+ regions 141. The two doping adjustment regions 143 are respectively the left doping adjustment region and the right doping adjustment region. The left doping adjustment region is located between the left first target P+ region and the second target P+ region 142, and the right doping adjustment region is located between the right first target P+ region and the second target P+ region 142.

[0029] The MPS region 140 can also be configured into a more complex structure. The MPS region 140 includes: N first target P+ regions 141, N-1 second target P+ regions 142, and N doping adjustment regions 143, where N>2. A first target P+ region 141 is correspondingly provided on the adjacent side of each gate region 120, that is, a first target P+ region 141 is provided at each end of the MPS region 140. The first target P+ region 141 and the second target P+ region 142 are alternately distributed between the first target P+ regions 141 at the two ends. The doping adjustment region 143 is located between the first target P+ region 141 and the second target P+ region 142.

[0030] The conductivity type of the doping adjustment region 143 is N-type or P-type. According to different application scenarios, a small dose and low energy N-type or P-type implantation is performed to form an N-type doping adjustment region or a P-type doping adjustment region. If the conductivity type of the doping adjustment region 143 is N-type, the Schottky barrier height of the device is reduced, thereby reducing the turn-on voltage and conduction voltage drop of the Schottky diode. If the conductivity type of the doping adjustment region 143 is P-type, the influence of the Schottky current on the potential below the first target P+ region 141 and the second target P+ region 142 is reduced by increasing the Schottky barrier height, thereby reducing the bipolar turn-on voltage (Vturn) of the MPS diode.

[0031] In this embodiment, the first target P+ region 141 in the MPS region 140 forms a PIN diode in the device, and the second target P+ region 142 in the MPS region 140 forms a Schottky contact region, i.e., a Schottky diode, in the device. When the device withstands reverse voltage, the design of the large and small P+ regions (i.e., the first target P+ region 141 and the second target P+ region 142) can shield the Schottky junction of the Schottky contact region and reduce reverse leakage. At the same time, the small P+ region (i.e., the first target P+ region 141) can also reduce the electric field strength of the gate oxide near the MPS structure, improve the long-term reliability of the gate oxide, extend the service life of the gate oxide layer, and reduce device loss. In addition, through the structural design of the MPS region 140 of this embodiment, the reliability of the device under extreme surge conditions is improved. The doping adjustment region 143 can adjust the bipolar turn-on voltage (Vturn) and forward conduction voltage drop (VF) of the MPS diode according to different application requirements.

[0032] The device of this embodiment further includes: a source metal layer 150. The source metal layer 150 is located on the silicon carbide wafer 110 and covers the gate region 120, the doping region 130 and the MPS region 140. The first target P+ region 141 and the second target P+ region 142 form an ohmic contact with the source metal layer 150, and the first target P+ region 141 and the second target P+ region 142 form a PIN diode with the N-type silicon carbide epitaxial layer 112. The doping adjustment region 143 forms a Schottky contact with the source metal layer 150 to obtain a Schottky contact region.

[0033] Specifically, the first target P+ region 141 and the second target P+ region 142 form ohmic contacts with the source metal layer 150 by forming ohmic contact holes 144 at the interfaces between the first target P+ region 141 and the second target P+ region 142 and the source metal layer 150, respectively, and filling metal in the ohmic contact holes 144 to obtain ohmic contact regions. The doping adjustment region 143 forms a Schottky contact with the source metal layer 150 by forming a Schottky contact hole 145 at the interface between the doping adjustment region 143 and the source metal layer 150, and filling metal in the Schottky contact hole 145 to form a Schottky contact region.

[0034] The device of this embodiment further includes a drain metal layer 160 . The drain metal layer 160 is located under the N-type silicon carbide substrate 111 .

[0035] The working principle of the SiC MOSFET device in this embodiment is as follows: The first target P+ region 141 (small P+ region) and the second target P+ region 142 (i.e., large P+ region) form an ohmic contact with the upper source metal layer 150, and form a PIN diode with the lower N-type silicon carbide epitaxial layer 112 and the N-type silicon carbide substrate 111. The doping adjustment region 143 forms a Schottky contact with the upper source metal layer 150 to generate a Schottky contact region. During the reverse withstand voltage process, the large and small P+ regions in the MPS region 140 will widen the depletion layer between the P well region 131 and the N-type silicon carbide epitaxial layer 112, shield the Schottky junction in the Schottky contact region, and reduce reverse leakage. At the same time, the design of the small P+ region moves the strong electric field of the gate oxide near the MPS structure downward to the N-type silicon carbide epitaxial layer 112 with a higher critical breakdown field strength, thereby protecting the gate oxide, extending the service life of the gate oxide, and improving the long-term reliability of the gate oxide.

[0036] like Figure 2a and Figure 2b As shown, Figure 2a A diagram showing the electric field intensity distribution of a SiC MOSFET device with a conventional split-gate integrated SBD (Schottky Barrier Diode) structure. Figure 2b The electric field intensity distribution diagram of the SiC MOSFET device with the integrated MPS region 140 structure of this embodiment is shown. The conventional separated gate integrated SBD structure SiC MOSFET device structure is that the SBD structure is integrated in the MOSFET gate region, and the Schottky diode contact region is reserved in the JFET region below the conventional structure gate region. It can be understood that the conventional separated gate integrated SBD structure SiC MOSFET device structure is based on the fact that the current spreading layer 113 is not set, and the MPS region 140 structure of this embodiment is removed, and the N-type silicon carbide epitaxial layer 112 and the source metal layer 150 directly form a Schottky contact between the two gate regions 120. Figure 2a and Figure 2b In the figure, source represents the source, that is, the source metal layer 150 . gate represents the gate, that is, the gate region 120 .

[0037] from Figure 2a The area in the middle frame shows that Figure 2a The gate region in the conventional split-gate integrated SBD structure SiC MOSFET device gate region has a high electric field strength near the gate oxide layer 121. Figure 2b The framed area shows that Figure 2bThe gate region 120 in the device corresponds to the region in the N-type silicon carbide epitaxial layer 112. Based on the MPS region 140 structure, the electric field strength near the gate oxide layer 121 of the gate region 120 of the device in the embodiment is significantly reduced. Therefore, the design of the first target P+ region 141 (i.e., the small P+ region) moves the strong electric field of the gate oxide near the MPS structure downward to the N-type silicon carbide epitaxial layer 112 with a higher critical breakdown field strength, thereby protecting the gate oxide, extending the service life of the gate oxide, and improving the long-term reliability of the gate oxide.

[0038] During the forward conduction process, under low current conditions (i.e., normal device operation), the PIN diodes under the first target P+ region 141 (small P+ region) and the second target P+ region 142 (i.e., large P+ region) have high turn-on voltages, so the first target P+ region 141 (small P+ region), the second target P+ region 142 (i.e., large P+ region), and the PIN diode do not pass current, and only the Schottky contact region passes current. Under abnormally high current conditions (such as surge current, etc.), the PIN diode is turned on, and the PIN diode and the Schottky contact region pass current together. The design of the second target P+ region 142 (i.e., large P+ region) reduces the bipolar turn-on voltage (Vturn) of the MPS region 140 diode and provides a spacious current path, thereby improving the reliability of the device under extreme surge conditions. The current paths under different conditions are shown in the figure. Figure 3 As shown. Figure 3 In the normal working state of the device, the normal current path is that only the Schottky contact area passes the current, and the first target P+ area 141 (small P+ area) and the second target P+ area 142 (i.e., large P+ area), as well as the PIN diode below, do not pass the current. When the device has an abnormally large current state, such as when there is a surge current, the surge current path is that the PIN diode is turned on, and the PIN diode and the Schottky contact area pass the current together. Through the MPS area 140 structure, the device's limit overcurrent capability is optimized, and the reliability of the device under extreme surge conditions is improved.

[0039] This embodiment also proposes that the integrated MPS region 140 structure can be implanted with a small dose and low energy of N-type or P-type to form a doping adjustment region 143 according to different application scenarios. The N-type doping adjustment region formed by the N-type implantation can reduce the Schottky barrier height, thereby reducing the turn-on voltage and conduction voltage drop of the Schottky diode. The P-type doping adjustment region formed by the P-type implantation can reduce the influence of the Schottky current on the potential below the first target P+ region 141 and the second target P+ region 142 by increasing the Schottky barrier height, thereby reducing the bipolar turn-on voltage (Vturn) of the MPS diode. Figure 4a In addition, this embodiment also introduces a current spreading layer 113 (CSL) by controlling the implantation dose and energy of the JFET region to reduce the on-resistance and forward conduction voltage drop of the device, thereby optimizing the loss of the device.

[0040] like Figure 4a and Figure 4b As shown, the horizontal axis represents the forward conduction voltage drop VF of the diode in the MPS region 140, and the vertical axis represents the current IF of the diode in the MPS region 140. Curve A1 represents a SiC MOSFET device having an MPS region 140 structure with a P-type doping adjustment region 143, curve A2 represents a SiC MOSFET device having an MPS structure with an N-type doping adjustment region 143, and curve A3 represents a SiC MOSFET device having an MPS region 140 structure with no doping adjustment region. The BB' region represents an enlarged view of the three curves in the Schottky diode-dominated mode of the SiCMOSFET device, as shown in FIG. Figure 4b The CC' region represents a curve diagram in which the bipolar conduction of the SiC MOSFET device is the dominant mode. The bipolar conduction of the SiC MOSFET device is the conduction mode of the PN junction formed by the first target P+ region 141 and the second target P+ region 142 and the N+ region 133.

[0041] When there is a low forward voltage between the source and the drain, the Schottky diode starts to conduct when it reaches the turn-on voltage. At this time, the MPS region 140 diode is far from reaching the turn-on voltage and is in a cut-off state. Therefore, the IF-VF curve between the source and the drain of the device depends only on the Schottky diode, that is, the BB' region. When there is a high forward voltage between the source and the drain, the IF-VF curve between the source and the drain depends only on the MPS region 140 diode, that is, the CC' region (the current of the Schottky diode is very small relative to the MPS region 140 diode, which can be ignored in qualitative analysis). The inflection points of the curves in the BB' region and the CC' region correspond to the turn-on voltages of the Schottky diode and the MPS region 140 diode, respectively. In the BB' region, the turn-on voltage of the Schottky diode of the SiC MOSFET device with the MPS structure of the N-type implanted doping adjustment region 143 is the smallest, and the turn-on voltage of the Schottky diode of the SiC MOSFET device with the MPS region 140 structure of the P-type implanted doping adjustment region 143 is the largest. In the CC' region, the bipolar conduction voltage / conduction voltage drop of the MPS region 140 diode of the SiC MOSFET device having the MPS region 140 structure with the P-type implanted doping adjustment region 143 is the smallest, and the bipolar conduction voltage / conduction voltage drop of the MPS region 140 diode of the SiC MOSFET device having the MPS region 140 structure with the N-type implanted doping adjustment region 143 is the largest. Therefore, a small dose and low energy N-type or P-type implant is performed according to different application scenarios to form the doping adjustment region 143. The bipolar conduction voltage (Vturn) and forward conduction voltage drop (VF) of the diode of the MPS region 140 are adjusted by the doping adjustment region 143.

[0042] The specific manufacturing process of the high-reliability SiC MOSFET device of this embodiment is described below: First, as Figure 5 As shown, an N-type silicon carbide epitaxial layer 112 is formed on an N-type silicon carbide substrate 111. A photolithography mask and a hard mask are used to define regions on the N-type silicon carbide epitaxial layer 112 and multiple aluminum ion high-temperature implantations are performed to form a P-well region 131. Then, a self-aligned process is used to define regions and multiple nitrogen ion high-temperature implantations are performed to form an N+ region 133 in the P-well region 131. The implantation dose range of the P-well region 131 is 1E13~1E15cm -2 The junction depth range is 0.6um~1.2um. The N+ region 133 implantation dose range is 1E14~2E16cm -2 , the junction depth range is 0.2um~0.5um.

[0043] Second, if Figure 6 As shown, a doping adjustment region 143 is formed in the N-type silicon carbide epitaxial layer 112 by defining an area through a mask and a hard mask and performing high temperature implantation of aluminum ions or nitrogen ions. The junction depth of the doping adjustment region 143 is in the range of 0.2um to 0.5um.

[0044] Third, if Figure 7 As shown, the regions are defined by a mask and a hard mask and multiple aluminum ion high temperature implantations are performed to form a P+ region in the P well region 131, and a first target P+ region 141 and a second target P+ region 142 are formed in the region corresponding to the MPS region 140. The implantation dose range of the P+ region 132, the first target P+ region 141 and the second target P+ region 142 is 1E15~1E17cm -2 The junction depth ranges from 0.3um to 0.8um. ​​The doping concentrations of the P+ region 132, the first target P+ region 141, and the second target P+ region 142 can be consistent, and can also be adjusted according to actual needs.

[0045] Fourth, if Figure 8 As shown, a current spreading layer 113 is formed on the basis of the N-type silicon carbide epitaxial layer 112 by multiple high-temperature nitrogen ion implantation without a mask. Then, a carbon layer is covered on the surface of the N-type silicon carbide epitaxial layer 112 and high-temperature activation annealing is performed to activate the implanted ions while preventing the high-temperature volatilization of silicon atoms. The carbon layer is removed after annealing. The implantation dose of N ions in the current spreading layer 113 ranges from 1E11 to 1E13 cm -2 , the junction depth range is 0.4um~1.2um. The annealing temperature range is 1700℃~2000℃, and the annealing time range is 10min~60min.

[0046] Fifth, if Fig. 9As shown, a gate oxide layer 121 is grown by thermal oxidation on the surface of the N-type silicon carbide epitaxial layer 112 (a small amount of nitrogen monoxide NO is introduced into the oxidizing atmosphere, which can greatly improve the SiO2 / SiC interface quality), and then a gate polysilicon 122 is chemically deposited. Photolithography and etching are performed at designated positions through a mask to form a separated gate structure, that is, a structure of two gate regions 120. The gate oxide layer 121 material includes but is not limited to SiO2, and the thickness ranges from 0.02um to 0.12um. The thickness range of the gate polysilicon 122 is 0.3um to 1um.

[0047] Sixth, if Fig.10 As shown, a dielectric layer 123 is deposited on the surface of the N-type silicon carbide epitaxial layer 112 and the separation gate structure (i.e., the gate polysilicon 122 and the gate oxide layer 121 of the gate region 120). The dielectric layer is an ILD dielectric layer. Photolithography and dielectric layer etching are performed at a specified position through a mask. An ohmic contact hole 144 is formed at the interface between the first target P+ region 141, the second target P+ region 142 and the source metal layer 150, and then metal nickel is sputtered by physical vapor deposition and annealing is performed. An ohmic contact region is formed at the opening position of the ohmic contact hole 144. The width of the ohmic contact hole 144 ranges from 0.3um to 1.2um. The material of the dielectric layer 123 includes but is not limited to silicon dioxide and borophosphosilicate glass, and the thickness ranges from 0.4 to 1.2um.

[0048] Seventh, such as Fig.11 As shown, photolithography and dielectric layer etching are performed at designated positions through a mask, and a Schottky contact hole 145 is formed at the interface between the doping adjustment region 143 and the source metal layer 150, followed by physical vapor deposition and sputtering of metal titanium and annealing. A Schottky contact region is formed at the opening position of the Schottky contact hole 145, and the width of the Schottky contact hole 145 ranges from 0.3um to 1.2um.

[0049] Eighth, such as Figure 1 As shown, a source metal layer 150 is formed on the dielectric layer 123, and the material of the source metal layer 150 includes but is not limited to aluminum copper. The thickness of the source metal layer 150 ranges from 2um to 5um. A drain metal layer 160 is formed under the N-type substrate. Finally, a complete SiC MOSFET device structure of this embodiment is formed.

[0050] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: This embodiment separates the gate structure, that is, sets a hybrid PIN Schottky diode MPS region between the gate regions, to avoid the "bipolar degradation effect" caused by long-term forward conduction of the device. At the same time, during the reverse withstand voltage of the device, the MPS region set between the gate regions widens the depletion layer between the doped region and the epitaxial layer of the silicon carbide wafer, shields the Schottky junction of the Schottky contact region of the MPS region, and reduces reverse leakage. In addition, the design of the MPS region of this embodiment moves the strong electric field of the gate oxide (i.e., the gate oxide layer) of the gate region near the MPS structure down to the epitaxial layer with a higher critical breakdown field strength, thereby improving the long-term reliability of the gate oxide of the gate region and reducing device loss. During the forward conduction of the device, under low current conditions (i.e., the normal working state of the device), only the Schottky contact region in the MPS region passes current; while under abnormally large current conditions (such as surge current, etc.), the PIN diode in the MPS region and the Schottky contact region pass current together, thereby improving the reliability of the device under extreme surge conditions, improving the device's limit overcurrent capability, and reducing device loss.

[0051] Embodiment 2 Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a high-reliability SiC MOSFET device, such as Fig.12 As shown, for manufacturing the high-reliability SiC MOSFET device described in Embodiment 1, the method includes: S201, forming two gate regions on the silicon carbide wafer; S202, forming a doping region on each of the two gate regions' remote sides, wherein the remote side is a side of the gate region remote from the other gate region; S203, forming a hybrid PIN Schottky diode region MPS region on the silicon carbide wafer and between the two gate regions, wherein the MPS region is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

[0052] Since the manufacturing method of the high-reliability SiC MOSFET device introduced in this embodiment is the manufacturing method adopted for implementing the high-reliability SiC MOSFET device in the first embodiment of the present application, based on the high-reliability SiC MOSFET device introduced in the first embodiment of the present application, the technical personnel in the field can understand the specific implementation method and various variations of the manufacturing method of the high-reliability SiC MOSFET device in this embodiment, so how the manufacturing method realizes the high-reliability SiC MOSFET device in the first embodiment of the present application is not introduced in detail here. As long as the technical personnel in the field implement the manufacturing method adopted by the high-reliability SiC MOSFET device in the first embodiment of the present application, it belongs to the scope of protection of this application.

[0053] It should be understood by those skilled in the art that, although the preferred embodiments of the present invention have been described, other changes and modifications may be made to these embodiments once those skilled in the art have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0054] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high reliability SiC MOSFET device, characterized in that: include: Silicon carbide wafer, two gate regions, two doping regions and hybrid PIN Schottky diode region MPS region; The two gate regions are located on the silicon carbide wafer; The two doping regions are located on the silicon carbide wafer and are respectively located on the far side of the two gate regions, where the far side is a side of the gate region away from the other gate region; The MPS region is located on the silicon carbide wafer and between the two gate regions, and is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

2. The SiC MOSFET device according to claim 1, wherein: The MPS region includes: a first target P+ region, a second target P+ region and a doping adjustment region, wherein the size of the second target P+ region is larger than the first target P+ region; The first target P+ region is correspondingly located at an adjacent side of each of the gate regions, and the adjacent side is a side of the gate region adjacent to another gate region; The second target P+ region is located between the first target P+ regions; The doping adjustment region is located between the first target P+ region and the second target P+ region.

3. The SiC MOSFET device according to claim 2, characterized in that: The conductivity type of the doping adjustment region is N-type or P-type.

4. The SiC MOSFET device according to claim 3, characterized in that: Also includes: source metal layer; The source metal layer is located on the silicon carbide wafer and covers the gate region, the doping region and the MPS region, wherein the first target P+ region and the second target P+ region form an ohmic contact with the source metal layer, and the doping adjustment region forms a Schottky contact with the source metal layer.

5. The SiC MOSFET device according to claim 3, characterized in that: Each gate region includes: a gate oxide layer, a gate polysilicon layer and a dielectric layer; The gate oxide layer is located on the silicon carbide wafer; The gate polysilicon is located on the gate oxide layer; The dielectric layer wraps the gate polysilicon and the gate oxide layer.

6. The SiC MOSFET device according to claim 3, characterized in that: Each of the doped regions includes: a P-well region, a P+ region and an N+ region; The P-well region is located in the silicon carbide wafer; The P+ region and the N+ region are located in the P-well region, the N+ region is correspondingly located on the side away from the gate region, and the P+ region contacts the side of the N+ region away from the gate region, wherein the surfaces of the P-well region, the P+ region and the N+ region are located on the same horizontal plane as the surface of the silicon carbide wafer.

7. The SiC MOSFET device according to claim 3, characterized in that: The silicon carbide wafer comprises: an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer, wherein the N-type silicon carbide epitaxial layer is located on the N-type silicon carbide substrate.

8. The SiC MOSFET device according to claim 7, characterized in that: Also includes: A current spreading layer, wherein the current spreading layer is located in the N-type silicon carbide epitaxial layer, and a surface of the current spreading layer and a surface of the N-type silicon carbide epitaxial layer are located at the same horizontal plane, and the doping region and the MPS region are located on the current spreading layer.

9. The SiC MOSFET device according to claim 8, characterized in that: Also includes: A drain metal layer, wherein the drain metal layer is located below the N-type silicon carbide substrate.

10. A method for manufacturing a high-reliability SiC MOSFET device, characterized in that: A method for manufacturing a high-reliability SiC MOSFET device as claimed in any one of claims 1 to 9; the method comprising: forming two gate regions on the silicon carbide wafer; A doping region is formed on each of the two gate regions at a far side, wherein the far side is a side of the gate region away from the other gate region; A hybrid PIN Schottky diode region MPS region is formed on the silicon carbide wafer and between the two gate regions, wherein the MPS region is used to improve the surge resistance of the device while avoiding the bipolar degradation effect of the device.

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