Semi-super-junction high-reliability planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a semi-super-junction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a first drift region; a barrier layer is formed, etching and ion implantation are carried out, and a column region is formed; the barrier layer is removed, epitaxial growth is carried out on the first drift region, a second drift region is formed, and the drift layer comprises the first drift region and the second drift region; forming a barrier layer, etching, performing ion implantation, and forming a first P-type well region, a lug boss, a second P-type well region, an N-type source region and a Schottky region; re-forming a barrier layer, etching and depositing to form a gate dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: re-forming a barrier layer, etching, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that dual protection can be provided during reverse voltage withstanding, and the reliability of the device is improved.

Description

Technical Field

[0001] The invention relates to a semi-superjunction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion, etc. For silicon carbide power VDMOS, different fields have different requirements for device performance. Aiming at the high reliability requirements of aerospace and automotive electronics, we continue to provide a high-reliability VDMOS. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a semi-superjunction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, which can provide double protection during reverse withstand voltage, thereby improving the reliability of the device.

[0004] In a first aspect, the present invention provides a method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a first drift region; Step 2, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and implanting ions to form a pillar region; Step 3, removing the barrier layer, performing epitaxial growth on the first drift region to form a second drift region, wherein the drift layer includes the first drift region and the second drift region; Step 4, forming a barrier layer above the second drift region, etching the barrier layer to form a through hole, and performing ion implantation into the second drift region to form a first P-type well region and a protruding portion; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a second P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift region to form a Schottky region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0005] In a second aspect, the present invention provides a semi-super junction high-reliability planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a semi-super junction high-reliability planar gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are: 1. The present invention realizes a semi-superjunction device structure of the device by constructing a pillar region in the drift layer, thereby improving the voltage resistance of the device and reducing the on-resistance of the device; 2. The present invention constructs a first P-type well region and a second P-type well region wrapped therein in the gate structure of the device, wherein the side of the N-type source region away from the gate metal layer and below is the second P-type well region, and the side close to the gate metal layer is the first P-type well region, and the N-type source region of the device overlaps with the gate metal layer in the lateral direction, wherein the second P-type well region can ensure the reverse withstand voltage capability of the device, and the first P-type well region on the side of the N-type source region close to the gate can ensure low gate charge of the device and fast switching speed, thereby improving the device performance in terms of withstand voltage reliability and switching characteristics of the device; the second P-type well region wraps the N-type source region, which can improve the body diode freewheeling capability of the device; 3. The present invention constructs a Schottky region, which can construct a parasitic Schottky body diode of the device and reduce the body diode freewheeling loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of the semi-superjunction high-reliability planar gate silicon carbide VDMOS of the present invention is shown.

[0009] Figure 2 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 1 .

[0010] Figure 3 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 2 .

[0011] Figure 4 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 3 .

[0012] Figure 5 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 4 .

[0013] Figure 6 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 8 .

[0017] Fig.10 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 9 .

[0018] Fig.11 A cross-sectional view of the process of manufacturing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to the present invention Figure 10 . DETAILED DESCRIPTION

[0019] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0021] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0022] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0023] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the side of the silicon carbide substrate 1 to form a first drift region 23; Step 2, forming a barrier layer 9 above the first drift region 23, etching the barrier layer 9 to form a through hole, and performing ion implantation to form a pillar region 21; Step 3, removing the barrier layer 9, performing epitaxial growth on the first drift region 23 to form a second drift region 24, wherein the drift layer 2 includes the first drift region 23 and the second drift region 24; Step 4, forming a barrier layer 9 above the second drift region 24, etching the barrier layer 9 to form a through hole, and performing ion implantation into the second drift region 24 to form a first P-type well region 3 and a protruding portion 22; Step 5, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the first P-type well region 3 to form a second P-type well region 31; Step 6, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the second P-type well region 31 to form an N-type source region 311; Step 7, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the second drift region 24 to form the Schottky region 4; Step 8, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and depositing to form a gate dielectric layer 5; Step 9, removing the original barrier layer, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing metal, and forming a gate metal layer 6; Step 10: remove the original barrier layer, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.

[0025] In this embodiment, preferably, the thickness of the column region 21 is smaller than the thickness of the drift layer 2 .

[0026] In this embodiment, preferably, the column region 21 is located directly below the first P-type well region 3 and the second P-type well region 31 , and the column region 21 is not located directly below the N-type source region 311 , the protrusion 22 and the Schottky region 4 .

[0027] In this embodiment, preferably, the Schottky region 4 , the drift layer 2 and the silicon carbide substrate 1 are all of N type; and the pillar region 21 is of P type.

[0028] In this embodiment, preferably, the doping concentration of the Schottky region 4 is greater than the doping concentration of the first P-type well region 3 ; and the doping concentration of the Schottky region 4 is less than the doping concentration of the second P-type well region 31 .

[0029] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1; A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a column region 21 is provided in the drift layer 2, wherein the lower side of the column region 21 is connected to the silicon carbide substrate 1, and a protrusion 22 is provided on the drift layer 2; A first P-type well region 3, wherein the lower side of the first P-type well region 3 is connected to the upper side of the drift layer 2, and the inner side of the first P-type well region 3 is connected to the outer side of the protrusion 22; a second P-type well region 31 is provided on the first P-type well region 3, and an N-type source region 311 is provided on the second P-type well region 31, and the inner side of the N-type source region 311 is connected to the first P-type well region 3; A Schottky region 4, wherein the lower side of the Schottky region 4 is connected to the upper side of the drift layer 2, and the inner side of the Schottky region 4 is respectively connected to the first P-type well region 3 and the second P-type well region 31; A gate dielectric layer 5, the lower side of which is connected to the N-type source region 311 and the first P-type well region 3; A gate metal layer 6, wherein the gate metal layer 6 is connected to the gate dielectric layer 5; A source metal layer 7, wherein the source metal layer 7 is respectively connected to the Schottky region 4, the second P-type well region 31 and the N-type source region 311; and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0030] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 , the doping concentration of the P-type column region 21 is 1-5e16cm -3 , the doping concentration of the first P-type well region 3 is 1-6e17cm -3 The doping concentration of the second P-type well region 31 is 1-5e18cm -3 , the doping concentration of the N-type Schottky region 4 is 6-9e17cm -3 The material of the gate dielectric layer 5 can be one of silicon dioxide, silicon nitride or a composite. The doping concentration of the N-type source region 311 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 1 is to ensure that it forms a low-resistance ohmic contact with the drain metal layer 8; the doping concentration of the P-type column region 21 is to form a laterally distributed pn junction when the device drain is subjected to a high voltage, thereby changing the single longitudinal withstand voltage structure of the device to a withstand voltage structure combined with a transverse and longitudinal structure, thereby improving the withstand voltage capability of the device; the doping concentration of the first P-type well region 3 is to form a gradual junction between the reverse withstand voltage of the device N-type drift layer 2 and the P-type column region 21, thereby avoiding device reliability problems caused by sudden changes in electric field strength; the second P-type well region 3 is to form a gradual junction between the reverse withstand voltage of the device N-type drift layer 2 and the P-type column region 21, thereby avoiding device reliability problems caused by sudden changes in electric field strength; Region 31 is to protect the device from drain-source breakdown during reverse withstand voltage. At the same time, the second P-type well region 31 forms an ohmic contact with the source metal layer 7 to reduce the conduction loss of the parasitic pn junction body diode of the device; the N-type Schottky region 4 is to form the parasitic Schottky body diode of the device to reduce the conduction loss of the body diode of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device, and the doping concentration of the N-type source region 311 is to reduce the source contact resistance of the device and reduce the on-resistance of the device.

[0031] The thickness of the N-type silicon carbide substrate 1 of the device is 2 μm, which is to provide support during the preparation process. The thickness of the N-type drift layer 2 is 50-100 μm, which is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the P-type column region 21 is 80-90% of the thickness of the N-type drift layer 2, so as to achieve the device's horizontal and vertical combined withstand voltage, and the space charge region of the first P-type well region 3 can contact the region of the P-type column region 21 during reverse withstand voltage, thereby ensuring the reverse withstand voltage characteristics of the device. The width of the N-type source region 311 of the device is 500nm-2 μm, and the width of the second P-type well region 31 is 3-5 times the width of the N-type source region, in order to ensure The second P-type well region 31 is wrapped at the bottom and away from the gate side to ensure the withstand voltage characteristics of the device; the width of the first P-type well region 3 is 300nm larger than the width of the second P-type well region 31, which is to form the gate control structure of the device, the thickness of the N-type source region 311 is 200nm, the thickness of the second P-type well region 31 is 400nm, the thickness of the first P-type well region 3 is 600nm, the thickness of the N-type Schottky region 4 is 600nm, the width of the N-type Schottky region 4 is equal to the width of the N-type source region 311, the thickness of the gate dielectric layer 5 is 50nm, the thickness of the source metal layer 7 is 200nm, and the thickness of the gate metal layer 6 is 150nm; In the present embodiment, a column region 21 is constructed in the drift layer 2 to realize a semi-superjunction device structure of the device, thereby improving the voltage resistance of the device and reducing the on-resistance of the device; a first P-type well region 3 and a second P-type well region 31 wrapped therein are constructed in the gate structure of the device, wherein the side of the N-type source region 311 away from the gate metal layer 6 and below is the second P-type well region 31, and the side close to the gate metal layer 6 is the first P-type well region 3, and the N-type source region 311 of the device overlaps with the gate metal layer 6 in the horizontal direction, wherein the second P-type well region 31 can ensure the reverse voltage resistance of the device, and the first P-type well region 3 on the side of the N-type source region 311 close to the gate metal layer 6 can ensure low gate charge of the device and fast switching speed, thereby improving the device performance in terms of the voltage resistance reliability and switching characteristics of the device; the second P-type well region 31 wraps the N-type source region 311, which can improve the body diode freewheeling capability of the device; the Schottky region 4 can construct the parasitic Schottky body diode of the device and reduce the body diode freewheeling loss of the device.

[0032] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a first drift region; Step 2, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and implanting ions to form a pillar region; Step 3, removing the barrier layer, performing epitaxial growth on the first drift region to form a second drift region, wherein the drift layer includes the first drift region and the second drift region; Step 4, forming a barrier layer above the second drift region, etching the barrier layer to form a through hole, and performing ion implantation into the second drift region to form a first P-type well region and a protruding portion; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the first P-type well region to form a second P-type well region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the second P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift region to form a Schottky region; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the stud region is smaller than the thickness of the drift layer.

3. The method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The column region is located directly below the first P-type well region and the second P-type well region, and the column region is not located directly below the N-type source region, the protruding portion, and the Schottky region.

4. The method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The Schottky region, the drift layer and the silicon carbide substrate are all N-type; the pillar region is P-type.

5. The method for preparing a semi-superjunction high-reliability planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the Schottky region is greater than the doping concentration of the first P-type well region; the doping concentration of the Schottky region is less than the doping concentration of the second P-type well region.

6. A semi-superjunction high-reliability planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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