Vertically stacked complementary field effect transistor and manufacturing method and application thereof

Abstract

The invention provides a vertical stacking complementary field effect transistor and a manufacturing method and application thereof. According to an embodiment of the present invention, the vertically stacked complementary field effect transistor comprises: a substrate; the N-type transistor is arranged on one side of the substrate and is of a top gate structure, the N-type transistor comprises a first channel layer, a passivation protection layer and a first gate oxide layer, the first channel layer is an IGZO channel, and the passivation protection layer is located between the first channel layer and the first gate oxide layer; the P-type transistor is arranged on one side, far away from the substrate, of the N-type transistor, is of a back gate structure, and shares a gate with the N-type transistor. The passivation protection layer is formed to protect the IGZO channel, when the first gate oxide layer is manufactured and the P-type transistor is manufactured subsequently, diffusion of hydrogen can be effectively blocked, the hydrogen resistance of the N-type transistor is improved, and therefore the electrical performance of the N-type transistor is improved; and the vertical stacking complementary field effect transistor which is compatible with the next process in which the N-type transistor is arranged and is high in performance can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to vertically stacked complementary field effect transistors and methods for making the same and applications thereof, and more specifically, to vertically stacked complementary field effect transistors and methods for making the same and multilayer stacked complementary field effect transistors. Background Art

[0002] Multi-metal oxide semiconductors represented by Indium Gallium Zinc Oxide (IGZO) have higher equivalent mobility (greater than 10cm 2 V -1 s -1 ), in addition, its good optical transparency, low manufacturing temperature and cost, and large-area preparation by sputtering or atomic layer deposition compatible with silicon-based processes make it have great potential in the fields of display, storage, and monolithic three-dimensional heterogeneous integration. At present, various structures of IGZO channel transistors have been proposed, including back-gate, top-gate, double-gate, and even vertical channel all-around gate structures.

[0003] Vertical Stack Complementary Field-Effect Transistor (VSCFET) is a new type of semiconductor component, which is composed of two complementary field-effect transistors (FET) stacked vertically, one of which is an n-type FET and the other is a p-type FET. VSCFET has the characteristics of high efficiency, high speed and low power consumption.

[0004] At present, in some common VSCFET structures, doped single crystal silicon, low temperature polysilicon, carbon nanotubes (CNT), etc. are used as P-type transistor channels, using a top gate structure (the gate and gate oxide layer are located above the channel) and manufactured in the lower layer; oxide semiconductors represented by IGZO are used as N-type transistors, using a back gate structure (the gate and gate oxide layer are located below the channel), manufactured in the upper layer, and sharing the gate with the P-type transistor. In the manufacturing process, the top-gate P-type transistor is manufactured first, and after the subsequent back-gate IGZO transistor is manufactured, it can still maintain good device characteristics. The matching performance between the two enables it to function normally in basic CMOS logic gates. At the same time, as a back-end process compatible device (back-end process compatibility usually means that new processes or devices can be implemented in the back-end interconnect layer after the standard CMOS front-end process is completed without interfering with or damaging the completed devices and structures), the CFET can be manufactured directly on silicon-based circuits through low-temperature processes, and can be used to construct digital logic circuits, SRAM memories and their peripheral circuits in the back-end process, realizing three-dimensional integration on a single chip, and further improving device density and functional integration.

[0005] Among them, the performance of IGZO is easily affected by factors such as high temperature conditions in subsequent processes or the external environment, hydrogen atom diffusion and plasma damage, which is mainly reflected in threshold voltage drift, hysteresis of transfer characteristics, and reduced device reliability. This makes IGZO and other oxide channel semiconductors only manufactured on the top layer to avoid performance degradation caused by subsequent high temperature or hydrogen-rich processes. If the IGZO transistor is made as a top gate at the bottom, it will face great challenges. Summary of the invention

[0006] The present invention aims to solve one of the technical problems in the related art at least to some extent. To this end, one object of the present invention is to provide a vertically stacked complementary field effect transistor, the bottom transistor of which can be a top-gate IGZO channel transistor.

[0007] In one aspect of the present invention, the present invention provides a vertically stacked complementary field effect transistor. According to an embodiment of the present invention, the vertically stacked complementary field effect transistor includes: a substrate; an N-type transistor, the N-type transistor is arranged on one side of the substrate and is a top gate structure, the N-type transistor includes a first channel layer, a passivation protection layer and a first gate oxide layer, the first channel layer is an IGZO channel, and the passivation protection layer is located between the first channel layer and the first gate oxide layer; a P-type transistor, the P-type transistor is arranged on a side of the N-type transistor away from the substrate, is a back gate structure, and shares a gate with the N-type transistor. Therefore, by forming a passivation protection layer to protect the IGZO channel after forming the first channel layer and before forming the first gate oxide layer, when making the first gate oxide layer and the subsequent making of the P-type transistor, it is possible to effectively block the diffusion of small molecule gases such as water, hydrogen, ammonia, and methane into the IGZO channel, that is, it is possible to effectively block the diffusion of hydrogen, improve the hydrogen resistance of the N-type transistor, and thus improve the electrical performance of the N-type transistor; and it is conducive to realizing a vertically stacked complementary field effect transistor that is compatible with the back-end process of the N-type transistor and has high performance.

[0008] According to an embodiment of the present invention, the N-type transistor further includes: a first source and a first drain, the first source and the first drain are spaced apart on a surface of the substrate; wherein the first channel layer is spaced apart on a side of the first source and the first drain away from the substrate, and is electrically connected to the first source and the first drain respectively; the passivation protection layer covers the exposed surface of the first channel layer; the first gate oxide layer is spaced apart on a side of the passivation protection layer away from the substrate; the gate is spaced apart on a side of the first gate oxide layer away from the substrate; the P-type transistor further includes: a second gate oxide layer, the second gate oxide layer is spaced apart on a side of the first gate oxide layer away from the substrate, and covers the gate; a second channel layer, the second channel layer is spaced apart on a side of the second gate oxide layer away from the substrate; a second source and a second drain, the second source and the second drain are spaced apart on a side of the second channel layer away from the substrate, and are both electrically connected to the second channel layer.

[0009] According to an embodiment of the present invention, the material of the passivation protection layer includes at least one of yttrium oxide, aluminum oxide and tantalum oxide.

[0010] According to an embodiment of the present invention, the thickness of the passivation protection layer is 3 nm to 4 nm.

[0011] In another aspect of the present invention, the present invention provides a method for manufacturing the vertically stacked complementary field effect transistor described above. According to an embodiment of the present invention, the method for manufacturing a vertically stacked complementary field effect transistor includes: providing a substrate; manufacturing an N-type transistor with a top gate structure on one side of the substrate, the steps of manufacturing the N-type transistor include the steps of forming a first channel layer, a passivation protection layer and a first gate oxide layer, and the passivation protection layer is formed between the first channel layer and the first gate oxide layer, and the first channel layer is an IGZO channel; manufacturing a P-type transistor with a back gate structure on the side of the N-type transistor away from the substrate, and the P-type transistor shares a gate with the N-type transistor. Therefore, in the above-mentioned manufacturing method, a passivation protection layer is formed after forming the first channel layer and before forming the first gate oxide layer to protect the IGZO channel. In this way, when manufacturing the first gate oxide layer and the subsequent manufacturing of the P-type transistor, it is possible to effectively block the diffusion of small molecule gases such as water, hydrogen, ammonia, and methane into the IGZO channel, that is, it is possible to effectively block the diffusion of hydrogen, improve the hydrogen resistance of the N-type transistor, and thus improve the electrical performance of the N-type transistor; and it is conducive to realizing a vertically stacked complementary field effect transistor that is compatible with the back-end process of the N-type transistor and has high performance.

[0012] According to an embodiment of the present invention, the step of making the N-type transistor also includes: forming a first source and a first drain at intervals on a surface of the substrate; wherein the first channel layer is formed on a side of the first source and the first drain away from the substrate, and is electrically connected to the first source and the first drain respectively; the passivation protection layer covers the exposed surface of the first channel layer; the first gate oxide layer is formed on a side of the passivation protection layer away from the substrate; the gate is formed on a side of the first gate oxide layer away from the substrate; the step of making the P-type transistor also includes: forming a second gate oxide layer on a side of the first gate oxide layer away from the substrate, the second gate oxide layer covering the gate; forming a second channel layer on a side of the second gate oxide layer away from the substrate; forming a second source and a second drain at intervals on a side of the second channel layer away from the substrate, and the second source and the second drain are both electrically connected to the second channel layer.

[0013] According to an embodiment of the present invention, the method for forming the passivation protective layer includes: directly depositing metal oxide to form the passivation protective layer, or, the method for forming the passivation protective layer includes: first depositing a metal layer; and then thermally oxidizing the metal layer in an air environment to obtain the passivation protective layer.

[0014] According to an embodiment of the present invention, the temperature of the thermal oxidation is 200-300°C.

[0015] According to an embodiment of the present invention, before forming the second gate oxide layer, the N-type transistor is annealed in an oxygen-containing environment, the annealing temperature is 150° C. to 250° C., and the time is 5 to 20 minutes.

[0016] In another aspect of the present invention, the present invention provides a multi-layer stacked complementary field effect transistor. According to an embodiment of the present invention, the multi-layer stacked complementary field effect transistor includes at least two layers of transistor units vertically stacked, and an interlayer dielectric layer is arranged between two adjacent transistor units, and the transistor unit includes the vertically stacked complementary field effect transistor described above, or a vertically stacked complementary field effect transistor manufactured by the method described above. As a result, the multi-layer stacked complementary field effect transistor has good back-end process compatibility and high performance. Those skilled in the art can understand that the multi-layer stacked complementary field effect transistor has all the features and advantages of the vertically stacked complementary field effect transistor described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 It is a schematic diagram of the structure of vertically stacked complementary field effect transistors in one embodiment of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure of a multi-layer stacked complementary field effect transistor in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] The scheme of the present invention will be explained below in conjunction with embodiments. It will be appreciated by those skilled in the art that the following embodiments are only used to illustrate the present invention and should not be considered as limiting the scope of the present invention. Where specific techniques or conditions are not indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are followed.

[0021] The present invention is described below with reference to specific embodiments. It should be noted that these embodiments are merely illustrative and do not limit the present invention in any way.

[0022] At present, IGZO, In 2 O 3N-type transistors such as IGZO are all used as back-gate transistors in CFET, that is, they are on the upper layer. This is mainly because the performance of IGZO is easily affected by high temperature conditions in subsequent processes or external environments, hydrogen atom diffusion and plasma damage, which is mainly reflected in threshold voltage drift, transfer characteristics hysteresis, device reliability reduction, etc., which makes IGZO and other oxide semiconductors can only be manufactured on the top layer to avoid performance degradation caused by subsequent high temperature or hydrogen-rich processes. If a top-gate structure with an N-type transistor underneath is used, there will be two major challenges: first, the gate oxide layer of IGZO and the P-type transistor will be manufactured after the IGZO channel is deposited, and the gate oxide layer is usually manufactured by atomic layer deposition (ALD). During the ALD process, a large number of hydrogen atoms produced by the chemical reaction of the precursor will create hydrogen-rich conditions, and the ALD itself also has a high temperature, which will have a great impact on the electrical properties of IGZO, and even make the N-type transistor no longer controlled by the gate and become a "normally on" device; second, the gate oxide layer of the N-type transistor of the top-gate IGZO is limited by the thermal stability of IGZO, and its ALD temperature cannot be as high as the ALD process temperature in the back-gate device. The limitation of the deposition temperature will directly limit the quality of the gate oxide layer and the interface between it and the channel (such as defect density), thereby increasing the off-state current and subthreshold slope of the device.

[0023] Based on this, in one aspect of the present invention, the present invention provides a vertically stacked complementary field effect transistor. According to an embodiment of the present invention, referring to Figure 1The vertically stacked complementary field effect transistor includes: a substrate 100; an N-type transistor 200, which is arranged on one side of the substrate 100 and is a top gate structure, and the N-type transistor 100 includes a first channel layer 210, a passivation protection layer 220 and a first gate oxide layer 230, the first channel layer 210 is an IGZO channel, and the passivation protection layer 220 is located between the first channel layer 210 and the first gate oxide layer 230; a P-type transistor 300, which is arranged on a side of the N-type transistor 200 away from the substrate 100, the P-type transistor 300 is a back gate structure, and the P-type transistor 300 and the N-type transistor 200 share a gate 203. Therefore, by forming a passivation protection layer after forming the first channel layer and before forming the first gate oxide layer to protect the IGZO channel, when making the first gate oxide layer and the subsequent making of the P-type transistor, the diffusion of small molecule gases such as water, hydrogen, ammonia, and methane into the IGZO channel can be well blocked, that is, the diffusion of hydrogen can be effectively blocked, and it has good hydrogen resistance, so that the IGZO can be protected from the damage of small molecules such as water, hydrogen, ammonia, and methane, thereby improving the electrical performance of the N-type transistor; and it is conducive to realizing the vertical stacking complementary field effect transistor with high performance that is compatible with the back-end process of the N-type transistor in the lower layer.

[0024] According to some embodiments of the present invention, the N-type transistor 200 further includes: a first source 240 and a first drain 250, the first source 240 and the first drain 250 are arranged at intervals on a surface of the substrate 100; wherein the first channel layer 210 is arranged on a side of the first source 240 and the first drain 250 away from the substrate 100, and is electrically connected to the first source 240 and the first drain 250 respectively; the passivation protection layer 220 covers the surface of the exposed first channel layer 210; the first gate oxide layer 230 is arranged on a side of the passivation protection layer 220 away from the substrate 100; the gate 2 03 is arranged on the side of the first gate oxide layer 230 away from the substrate; the P-type transistor 300 also includes: a second gate oxide layer 310, the second gate oxide layer 310 is arranged on the side of the first gate oxide layer 230 away from the substrate 100, and covers the gate 203; a second channel layer 320, the second channel layer 320 is arranged on the side of the second gate oxide layer 310 away from the substrate 100; a second source 330 and a second drain 340, the second source 330 and the second drain 340 are arranged at intervals on the side of the second channel layer 320 away from the substrate 100, and are both electrically connected to the second channel layer 320.

[0025] According to some embodiments of the present invention, the material of the passivation protection layer includes yttrium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ) and tantalum oxide (Ta 2 O 5). The above-mentioned material has good adsorption to small molecule gases such as water, hydrogen, ammonia, and methane, and can well block the diffusion of hydrogen, that is, the above-mentioned material has good hydrogen resistance, and can well protect the IGZO channel from the influence of hydrogen. Moreover, the above-mentioned material has good temperature resistance, which can help improve the compatibility of N-type transistors with thick processes. In some specific embodiments, the material of the passivation protection layer includes yttrium oxide, so that the protection effect on the IGZO channel is better.

[0026] According to some embodiments of the present invention, the thickness of the passivation protection layer is 3nm-4nm, such as 3nm, 3.1nm, 3.2nm, 3.3nm, 3.4nm, 3.5nm, 3.6nm, 3.7nm, 3.8nm, 3.9nm, 4nm, etc. Thus, the passivation protection layer of the above thickness can well protect the first channel passivation layer.

[0027] According to some embodiments of the present invention, there is no special requirement for the material of the substrate, and those skilled in the art can flexibly select it according to actual needs. In some specific embodiments, the substrate can be a silicon dioxide substrate.

[0028] According to some embodiments of the present invention, there are no special requirements for the materials of the first source and the first drain, and those skilled in the art can flexibly select them according to actual needs. In some specific embodiments, the materials of the first source and the first drain include but are not limited to at least one of metals such as titanium (Ti), palladium (Pd), nickel (Ni), and molybdenum (Mo). In some specific embodiments, the first source and the first drain can be a stacked structure of Ti / Pd.

[0029] According to some embodiments of the present invention, there are no special requirements for the materials of the second source and the second drain, and those skilled in the art can flexibly select them according to actual needs. In some specific embodiments, the materials of the second source and the second drain include but are not limited to at least one of metals such as titanium (Ti), palladium (Pd), nickel (Ni), and molybdenum (Mo). In some specific embodiments, the second source and the second drain can be a stacked structure of Ti / Pd.

[0030] According to some embodiments of the present invention, there are no special requirements for the materials of the first gate oxide layer and the second gate oxide layer, and those skilled in the art can flexibly select them according to actual needs. In some specific embodiments, the materials of the first gate oxide layer and the second gate oxide layer include, but are not limited to, at least one of hafnium oxide, silicon oxide, silicon nitride, or silicon oxynitride.

[0031] According to some embodiments of the present invention, there is no special requirement for the material of the gate, and those skilled in the art can flexibly select it according to actual needs. In some specific embodiments, the material of the gate includes but is not limited to at least one of metals such as titanium (Ti), palladium (Pd), nickel (Ni), and molybdenum (Mo).

[0032] According to some embodiments of the present invention, there are no special requirements for the material of the second channel layer, and those skilled in the art can flexibly select the channel material of the P-type transistor according to actual needs. In some specific embodiments, the material of the second channel layer includes but is not limited to carbon nanotubes (CNT), two-dimensional materials (such as MoS 2 ), P-type oxide semiconductors (SnO, NiO, TeO 2 ) and other materials.

[0033] In another aspect of the present invention, the present invention provides a method for manufacturing the vertically stacked complementary field effect transistor described above. According to an embodiment of the present invention, the method for manufacturing the vertically stacked complementary field effect transistor comprises:

[0034] S100: providing a substrate 100.

[0035] S200 : manufacturing an N-type transistor 200 with a top-gate structure on one side of the substrate 100 .

[0036] In this step, the steps of making the N-type transistor 200 include the steps of forming a first channel layer 210, a passivation protection layer 220 and a first gate oxide layer 230, and the passivation protection layer 220 is formed between the first channel layer 210 and the first gate oxide layer 230, and the first channel layer 210 is an IGZO channel. Therefore, the formation of the passivation protection layer 220 can well protect the IGZO channel, so that when making the first gate oxide layer and the subsequent making of the P-type transistor, it can well block the diffusion of small molecule gases such as water, hydrogen, ammonia, and methane into the IGZO channel, that is, it can effectively block the diffusion of hydrogen and has good hydrogen resistance, so that the IGZO can be protected from the damage of small molecules such as water, hydrogen, ammonia, and methane, thereby improving the electrical performance of the N-type transistor; and it is conducive to realizing a high-performance vertical stacked complementary field effect transistor that is compatible with the back-end process of the N-type transistor in the lower layer.

[0037] According to some embodiments of the present invention, a method for manufacturing an N-type transistor may include:

[0038] S210 : forming a first source electrode 240 and a first drain electrode 250 on one surface of the substrate 100 .

[0039] In some specific embodiments, the method of forming the first source 240 and the first drain 250 can be to deposit a metal layer by chemical vapor deposition, magnetron sputtering or atomic layer deposition, and then etch and pattern the metal layer to obtain the first source 240 and the first drain 250, that is, the first source 240 and the first drain 250 are obtained by a synchronous process.

[0040] S210 : forming an IGZO channel on the side of the first source 240 and the first drain 250 away from the substrate 100 , that is, forming a first channel layer 210 , and the first channel layer 210 is electrically connected to the first source 240 and the first drain 250 , respectively.

[0041] In some specific embodiments, an IGZO channel material layer is first deposited by chemical vapor deposition, magnetron sputtering or atomic layer deposition, and then the IGZO channel material layer is wet-etched using an acidic solution (such as hydrochloric acid, acetic acid, etc.) to obtain a patterned first channel layer.

[0042] S220 : forming a passivation protection layer 220 on a side of the first channel layer 210 away from the substrate 100 , and the passivation protection layer 220 covers the exposed surface of the first channel layer 210 .

[0043] According to some embodiments of the present invention, the passivation protection layer may be formed by a one-step method or a two-step method, as follows:

[0044] In some specific embodiments, a metal oxide is directly deposited on a side of the first channel layer 210 away from the substrate 100 by electron beam evaporation, magnetron sputtering, or the like to form the passivation protection layer 220 .

[0045] In other specific embodiments, a metal layer (such as a metal yttrium layer, a metal aluminum layer, etc.) is first directly deposited on the side of the first channel layer 210 away from the substrate 100 by electron beam evaporation, magnetron sputtering, etc.; and then the metal layer is thermally oxidized in an air environment to obtain a passivation protective layer 220. In some embodiments, the temperature of thermal oxidation is 200-300° C. (such as 200° C., 220° C., 250° C., 280° C., 300° C., etc.) and the time is 0.5-1 hour (such as 0.5 hour, 0.75 hour, 1 hour, etc.). Under this condition, the metal in the metal layer can be fully oxidized to obtain a passivation material layer of metal oxide.

[0046] S230 : forming a first gate oxide layer 230 on a side of the passivation protection layer 220 away from the substrate 100 .

[0047] In some specific embodiments, the first gate oxide layer 230 may be formed by deposition using methods such as chemical vapor deposition, magnetron sputtering, or atomic layer deposition.

[0048] S240 : forming a gate 203 on a side of the first gate oxide layer 230 away from the substrate 100 .

[0049] In some specific embodiments, the gate 203 may be formed by deposition using methods such as chemical vapor deposition, magnetron sputtering, or atomic layer deposition.

[0050] According to some embodiments of the present invention, after forming the gate, the N-type transistor 200 is annealed in an oxygen-containing environment before forming the second gate oxide layer 310 of the P-type transistor 300. Annealing in an air and oxygen environment can effectively repair oxygen-related vacancies (such as oxygen vacancies) in the first gate oxide layer, reduce defects inside the first gate oxide layer, and thereby improve the quality of the interface between the first gate oxide layer and the first channel layer (such as improving defect density), thereby improving the performance of the vertically stacked complementary field effect transistor.

[0051] In some embodiments, the annealing temperature is 150°C to 250°C (for example, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C, 250°C, etc.), and the annealing time lasts for 5 to 20 minutes before returning to room temperature to complete the annealing process.

[0052] S300: A P-type transistor 300 with a back-gate structure is fabricated on a side of the N-type transistor 200 away from the substrate 100. The P-type transistor 300 and the N-type transistor 200 share a gate 203. The schematic diagram of the structure can be referred to Figure 1 .

[0053] According to some embodiments of the present invention, the step of manufacturing the N-type transistor 300 further includes:

[0054] S310 : forming a second gate oxide layer 310 on a side of the first gate oxide layer 230 away from the substrate 100 , wherein the second gate oxide layer 310 covers the gate 203 .

[0055] In some specific embodiments, the second gate oxide layer 310 may be formed by deposition using methods such as chemical vapor deposition, magnetron sputtering, or atomic layer deposition.

[0056] S320 : forming a second channel layer 320 on a side of the second gate oxide layer 310 away from the substrate 100 .

[0057] According to some embodiments of the present invention, a specific method of forming the second channel layer 320 may be selected according to a specific material of the second channel layer.

[0058] In some embodiments, the material of the second channel layer is carbon nanotubes, and the method for making the second channel layer can be: first, the product obtained in step S310 is allowed to stand in a solution containing carbon nanotubes for a period of time to complete the deposition of the carbon nanotube layer; then, the carbon nanotube layer is dry-etched with plasma to obtain a carbon nanotube channel, i.e., the second channel layer.

[0059] In some other embodiments, the material of the second channel layer is a two-dimensional material (such as MoS 2 ), P-type oxide semiconductors (SnO, NiO, TeO 2 ), the method for making the second channel layer can be: first, deposit a channel material layer by chemical vapor deposition, magnetron sputtering or atomic layer deposition; then use plasma or etching liquid to dry or wet etch the channel material layer to obtain the second channel layer.

[0060] S330 : forming a second source 330 and a second drain 340 at a side of the second channel layer 320 away from the substrate 100 , and the second source 330 and the second drain 340 are both electrically connected to the second channel layer 320 .

[0061] In some specific embodiments, the method for forming the second source 330 and the second drain 340 can be to deposit a metal layer by chemical vapor deposition, magnetron sputtering or atomic layer deposition, and then etch and pattern the metal layer to obtain the second source 330 and the second drain 340, that is, the second source 330 and the second drain 340 are obtained by a synchronous process.

[0062] According to an embodiment of the present invention, in the above-mentioned manufacturing method, a passivation protection layer is formed after forming the first channel layer and before forming the first gate oxide layer to protect the IGZO channel. In this way, when manufacturing the first gate oxide layer and the subsequent manufacturing of the P-type transistor, the diffusion of small molecule gases such as water, hydrogen, ammonia, and methane into the IGZO channel can be well blocked, that is, the diffusion of hydrogen can be effectively blocked, and the hydrogen resistance of the N-type transistor is improved, thereby improving the electrical performance of the N-type transistor; and it is conducive to realizing a vertically stacked complementary field effect transistor that is compatible with the back-end process of the N-type transistor and has high performance.

[0063] Furthermore, after forming the gate, the N-type transistor 200 is annealed in an oxygen-containing environment before forming the second gate oxide layer 310 of the P-type transistor 300. Annealing in an air and oxygen environment can effectively repair oxygen-related vacancies (such as oxygen vacancies) in the first gate oxide layer, reduce defects inside the first gate oxide layer, and thus improve the quality of the interface between the first gate oxide layer and the first channel layer (such as improving defect density), thereby improving the performance of the vertically stacked complementary field effect transistor.

[0064] In another aspect of the present invention, the present invention provides a multi-layer stacked complementary field effect transistor. Figure 2 ( Figure 2 The example of the multilayer stacked complementary field effect transistor is only taken as an example including two layers of transistor units 01, and the number of layers is not limited thereto). The multilayer stacked complementary field effect transistor includes at least two layers of transistor units 01 vertically stacked, and an interlayer dielectric layer 400 is arranged between two adjacent transistor units 01. The transistor unit 01 includes the vertically stacked complementary field effect transistor described above, or a vertically stacked complementary field effect transistor manufactured by the method described above. As a result, the multilayer stacked complementary field effect transistor has good back-end process compatibility and high performance. Those skilled in the art can understand that the multilayer stacked complementary field effect transistor has all the features and advantages of the vertically stacked complementary field effect transistor described above.

[0065] According to some embodiments of the present invention, the material of the interlayer dielectric layer 400 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or organic insulating materials with low dielectric constants or glass. According to some embodiments of the present invention, in the multi-layer stacked complementary field effect transistor, there is no limit on the number of vertically stacked transistor units 01, and those skilled in the art can flexibly select according to actual needs.

[0066] According to some embodiments of the present invention, in a multilayer stacked complementary field effect transistor, all transistor units 01 may be the vertically stacked complementary field effect transistors described above in the present invention, some transistor units 01 may be the vertically stacked complementary field effect transistors described above, and some transistor units 01 may be complementary field effect transistors of other types of structures commonly found in the prior art.

[0067] According to some embodiments of the present invention, in a multi-layer stacked complementary field effect transistor, all transistor units 01 may be the vertically stacked complementary field effect transistors of the present invention. The method for preparing the multi-layer stacked complementary field effect transistor includes:

[0068] T100: manufacturing a first layer of vertically stacked complementary field effect transistors according to the above steps S100, S200 and S300;

[0069] T200: SiO is deposited by chemical vapor deposition (CVD) or magnetron sputtering 2 forming an interlayer dielectric layer 400;

[0070] T300: using chemical mechanical polishing (CMP) to planarize the surface of the interlayer dielectric layer 400;

[0071] T400: repeating steps S200 and S300 to complete the production of the second layer of vertically stacked complementary field effect transistors;

[0072] T500: Repeat steps T200 to T400 to complete the preparation of more layers of stacked complementary field effect transistors.

[0073] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0075] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A vertically stacked complementary field effect transistor, characterized in that: include: substrate; An N-type transistor, the N-type transistor is arranged on one side of the substrate and has a top gate structure, the N-type transistor comprises a first channel layer, a passivation protection layer and a first gate oxide layer, the first channel layer is an IGZO channel, and the passivation protection layer is located between the first channel layer and the first gate oxide layer; A P-type transistor is arranged on a side of the N-type transistor away from the substrate, has a back-gate structure, and shares a gate with the N-type transistor.

2. The vertically stacked complementary field effect transistor according to claim 1, characterized in that: The N-type transistor further comprises: A first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are arranged at intervals on a surface of the substrate; The first channel layer is arranged on a side of the first source and the first drain away from the substrate, and is electrically connected to the first source and the first drain respectively; the passivation protection layer covers the exposed surface of the first channel layer; the first gate oxide layer is arranged on a side of the passivation protection layer away from the substrate; the gate is arranged on a side of the first gate oxide layer away from the substrate; The P-type transistor further comprises: a second gate oxide layer, the second gate oxide layer being arranged on a side of the first gate oxide layer away from the substrate and covering the gate; A second channel layer, wherein the second channel layer is disposed on a side of the second gate oxide layer away from the substrate; A second source electrode and a second drain electrode are arranged at a distance from each other on a side of the second channel layer away from the substrate, and are both electrically connected to the second channel layer.

3. The vertically stacked complementary field effect transistor according to claim 1 or 2, characterized in that: The material of the passivation protection layer includes at least one of yttrium oxide, aluminum oxide and tantalum oxide.

4. The vertically stacked complementary field effect transistor according to claim 1 or 2, characterized in that: The thickness of the passivation protection layer is 3nm-4nm.

5. A method for manufacturing a vertically stacked complementary field effect transistor according to any one of claims 1 to 4, characterized in that: include: providing a substrate; Manufacturing an N-type transistor with a top gate structure on one side of the substrate, wherein the steps of manufacturing the N-type transistor include the steps of forming a first channel layer, a passivation protection layer and a first gate oxide layer, and the passivation protection layer is formed between the first channel layer and the first gate oxide layer, and the first channel layer is an IGZO channel; A P-type transistor with a back-gate structure is fabricated on a side of the N-type transistor away from the substrate, and the P-type transistor and the N-type transistor share a gate.

6. The method according to claim 5, characterized in that The step of manufacturing the N-type transistor further includes: Forming a first source electrode and a first drain electrode on a surface of the substrate in a spaced relationship; The first channel layer is formed on a side of the first source and the first drain away from the substrate, and is electrically connected to the first source and the first drain respectively; the passivation protection layer covers the exposed surface of the first channel layer; the first gate oxide layer is formed on a side of the passivation protection layer away from the substrate; the gate is formed on a side of the first gate oxide layer away from the substrate; The step of manufacturing the P-type transistor also includes: forming a second gate oxide layer on a side of the first gate oxide layer away from the substrate, wherein the second gate oxide layer covers the gate; forming a second channel layer on a side of the second gate oxide layer away from the substrate; A second source and a second drain are formed at a side of the second channel layer away from the substrate, and the second source and the second drain are both electrically connected to the second channel layer.

7. The method according to claim 5 or 6, characterized in that: The method for forming the passivation protection layer comprises: directly depositing metal oxide to form the passivation protection layer, Alternatively, the method of forming the passivation protection layer includes: First, a metal layer is deposited; Then, the metal layer is thermally oxidized in an air environment to obtain the passivation protection layer.

8. The method according to claim 7, characterized in that The temperature of the thermal oxidation is 200-300°C.

9. The method according to claim 6, characterized in that Before forming the second gate oxide layer, the N-type transistor is subjected to an annealing treatment in an oxygen-containing environment, wherein the annealing treatment is performed at a temperature of 150° C. to 250° C. and the duration is 5 to 20 minutes.

10. A multi-layer stacked complementary field effect transistor, characterized in that: It comprises at least two layers of transistor units which are vertically stacked, and an interlayer dielectric layer is arranged between two adjacent transistor units, and the transistor unit comprises the vertically stacked complementary field effect transistor according to any one of claims 1 to 4, or the vertically stacked complementary field effect transistor manufactured by the method according to any one of claims 5 to 9.

Images