Preparation method of low-attenuation heterojunction battery

Abstract

The invention discloses a preparation method of a low-attenuation heterojunction battery. The preparation method comprises the following steps: taking a silicon wafer subjected to gettering, cleaning and texturing treatment as a substrate; plating a passivation layer on the back surface of the substrate; plating a passivation layer and an N-type doping layer on the front surface of the substrate; plating a barrier layer on the passivation layer on the back surface of the substrate; plating a microcrystalline P seed layer on the barrier layer; plating a microcrystalline P main body layer on the microcrystalline P seed layer; respectively plating transparent conductive films on the N-type doped layer on the front surface of the substrate and the microcrystalline P main body layer on the back surface of the substrate; and respectively carrying out silk-screen printing, drying and curing on the transparent conductive films on the front surface and the back surface of the substrate to obtain the cell. The compact barrier layer can prevent boron elements from entering the passivation layer, so that the Voc of the battery is improved, and the attenuation of the battery is reduced. And a proper amount of oxygen source gas is introduced, so that valence band matching of the P-doped layer and the passivation layer is improved, and the FF of the battery is improved. And gradient doping is performed on the microcrystalline P main body layer, so that the contact resistance with TCO is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a method for preparing a crystalline silicon heterojunction cell. Background Art

[0002] Crystalline silicon / amorphous silicon heterojunction solar cells (HJT) have the advantages of high open circuit voltage, high conversion efficiency, low preparation temperature, and simple process flow. These advantages make crystalline silicon / amorphous silicon heterojunction cells gradually become one of the mainstream of mass-produced high-efficiency cells. At present, the conventional preparation method of crystalline silicon / amorphous silicon heterojunction cells is as follows: an N-type single crystal silicon wafer (Nc-Si) that has been treated with doping, cleaning, and texturing is used as a substrate; an intrinsic passivation layer (ia-Si:H) and an N-type microcrystalline doping layer (n-uc-Si:H) are coated on the front of the substrate; an intrinsic passivation layer (ia-Si:H) and a P-type doping layer (p-uc-Si:H) are coated on the back of the substrate; a transparent conductive film (TCO) is then coated on the front and back sides of the substrate; and finally, screen printing, curing, and drying steps are completed. The obtained product is as follows: Figure 1 The crystalline silicon / amorphous silicon heterojunction cell structure shown.

[0003] The crystalline silicon / amorphous silicon heterojunction battery prepared by the prior art, wherein the P-type microcrystalline doped layer and the intrinsic passivation layer are in contact with each other, so that the boron element in the P-type microcrystalline doped layer can easily enter the intrinsic passivation layer, and induce the formation of BH-Si weak bonds, so that the battery decays too much in a dark environment, that is, the dark decay is large. In addition, the boron element in the P-type microcrystalline doped layer will enter the intrinsic amorphous passivation layer through plasma coating or diffusion, destroying the hydrogenated amorphous silicon grid structure and affecting the passivation effect. The valence band matching between the intrinsic passivation layer and the P-type microcrystalline doped layer is unreasonable, and the valence band barrier is too large, which is not conducive to hole transmission, resulting in a low fill factor (FF).

[0004] Therefore, how to overcome the defects of existing crystalline silicon / amorphous silicon heterojunction cells, such as large cell attenuation, P-type microcrystalline doping layer affecting the passivation effect of the intrinsic passivation layer, and low fill factor (FF), is a technical problem that needs to be solved in this field. Summary of the invention

[0005] In order to solve the technical problems of existing crystalline silicon / amorphous silicon heterojunction batteries, such as large battery attenuation, P-type microcrystalline doping layer affecting the passivation effect of the intrinsic passivation layer and low fill factor, the present invention proposes a method for preparing a low-attenuation heterojunction battery.

[0006] The present invention provides a method for preparing a low-attenuation heterojunction battery, comprising the following steps:

[0007] Step 1, using an N-type single crystal silicon wafer (Nc-Si) that has been treated with gettering, cleaning, and texturing as a substrate;

[0008] Step 2, coating an intrinsic passivation layer (ia-Si:H) on the back side of the substrate; coating an intrinsic passivation layer (ia-Si:H) and an N-type microcrystalline doping layer (n-uc-Si:H) on the front side of the substrate;

[0009] Step 3, plating an intrinsic microcrystalline silicon oxygen barrier layer on the intrinsic passivation layer (ia-Si:H) on the back side of the substrate;

[0010] Step 4, plating a microcrystalline P seed layer on the intrinsic microcrystalline silicon oxygen barrier layer;

[0011] Step 5, plating a microcrystalline P main layer on the microcrystalline P seed layer;

[0012] Step 6, coating a transparent conductive film (TCO) on the N-type microcrystalline doped layer on the front side of the substrate and the microcrystalline P main layer on the back side;

[0013] Step 7: screen printing, drying and curing are performed on the transparent conductive films on the front and back sides of the substrate respectively to complete the metallization of the microcrystalline silicon heterojunction cell (HJT) and obtain the low-attenuation heterojunction cell.

[0014] Preferably, in step 3, the intrinsic microcrystalline silicon oxygen barrier layer is plated on the intrinsic passivation layer using a plasma enhanced chemical vapor deposition device; the power supply is 5000W, the pressure is 500Pa, and the ratio of hydrogen flow rate to silane flow rate (H 2 / SiH 4 ) is 300 times, N 2 O flow rate to silane flow rate ratio (N 2 O / SiH 4 ) is 1 times, the thickness of the barrier layer is 2.5-4nm, and the crystallization rate is 50-80%.

[0015] Preferably, in step 4, the microcrystalline P seed layer is plated using a plasma enhanced chemical vapor deposition device; the power supply is 4000W, the pressure is 500Pa, and the ratio of hydrogen flow rate to silane flow rate (H 2 / SiH 4 ) is 350 times, the ratio of B2H6 flow rate to silane flow rate (B 2 H 6 / SiH 4 ) is 0.1%, the thickness of the microcrystalline P seed layer is 3-5nm, and the crystallization rate is 50-60%.

[0016] Preferably, in step 5, the microcrystalline P main layer is plated using a plasma enhanced chemical vapor deposition device; the power supply is 7500W, the pressure is 500Pa, and the ratio of hydrogen flow rate to silane flow rate (H 2 / SiH 4 ) is 280 times; the thickness of the microcrystalline P main layer is 25-30nm, and the crystallization rate is 20-40%; among which, B 2 H 6 Flow rate to silane flow rate ratio (B 2 H 6 / SiH 4 ) gradually increased from 0.2% to 1%.

[0017] Preferably, the thickness of the N-type single crystal silicon wafer (Nc-Si) is 90-120 um, and the velvet pyramid thereof is 2-3 um high and 4-5 um wide.

[0018] Preferably, in step 2, a plasma enhanced chemical vapor deposition device is used to coat three layers of intrinsic passivation layer (ia-Si:H) on the back of the substrate; from inside to outside, the thickness of the first layer is 2-4nm, the thickness of the second layer is 2-5nm, and the thickness of the third layer is 3-10nm.

[0019] Preferably, in step 2, a plasma enhanced chemical vapor deposition device is used to coat three layers of intrinsic passivation layer (ia-Si:H) on the front side of the substrate; from inside to outside, the thickness of the first layer is 1-3nm, the thickness of the second layer is 2-3nm, and the thickness of the third layer is 3-6nm.

[0020] Preferably, in step 2, a plasma enhanced chemical vapor deposition device is used to deposit at least one N-type microcrystalline doping layer on the intrinsic passivation layer (ia-Si:H) on the front side of the substrate, with a thickness of 8-12 nm.

[0021] Preferably, in step 6, a transparent conductive film deposition device PAR (PVD and RPD) is used to plate an ITO film; the film has a square resistance of 30Ω / m, a mobility of 100cm² / Vs, and a transmittance of 98%.

[0022] Preferably, in step 7, the low-temperature silver paste for screen printing has a gate line height of 15 um and a width of 60 um.

[0023] In order to overcome the technical problem of large dark decay of existing crystalline silicon heterojunction cells, the present invention specially prepares an intrinsic microcrystalline silicon oxygen "barrier layer" between the intrinsic passivation layer on the back of the N-type single crystal silicon wafer substrate and the P-type microcrystalline doping layer containing the boron element, that is, a dense barrier layer with a high crystallization rate is set between the intrinsic passivation layer and the P-type microcrystalline doping layer to prevent the boron element of the P-type microcrystalline doping layer from entering the intrinsic passivation layer, thereby reducing the influence of the P-type microcrystalline doping layer on the intrinsic passivation layer. The barrier layer of intrinsic microcrystalline silicon oxygen is prepared by a high pressure, high hydrogen dilution ratio, and high power process. The barrier layer has a high crystallization rate and good density, and can effectively prevent the boron element from entering the intrinsic passivation layer, reducing the generation of BH-Si weak bonds, thereby increasing the battery Voc and reducing the attenuation of the crystalline silicon heterojunction cell in the dark state. During the preparation of the barrier layer, an appropriate amount of oxygen source gas (CO 2 or N 2 O), can significantly improve the valence band matching between the P-type microcrystalline doping layer and the intrinsic passivation layer, and improve the fill factor (FF) of the battery. Gradient doping of the microcrystalline P main layer, that is, low concentration doping is used near the intrinsic passivation layer, and high concentration doping is used near the transparent conductive film (TCO), which can reduce the influence of boron on the intrinsic passivation layer, increase the doping content of the P-type microcrystalline doping layer, and improve the contact resistance with the transparent conductive film. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention is described in detail below with reference to the embodiments and accompanying drawings, wherein:

[0025] Figure 1 It is a schematic diagram of the structure of an existing crystalline silicon heterojunction battery;

[0026] Figure 2 It is a schematic diagram of the structure of the crystalline silicon heterojunction battery of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the present invention and do not constitute a limitation to the present invention.

[0028] At present, in the chemical vapor deposition (CVD) process of preparing double-sided microcrystalline heterojunction cells, plasma enhanced chemical vapor deposition (PECVD) or hot wire chemical vapor deposition (HWCVD) equipment is usually used to first coat the front and back surfaces of the N-type single crystal silicon wafer with intrinsic amorphous silicon stacking, and the intrinsic amorphous silicon stacking has a passivating effect on the dangling bonds on the surface of the silicon wafer. Then, a microcrystalline P seed layer (incubation layer) is coated on the back of the N-type single crystal silicon wafer, and then a microcrystalline P main layer is coated on the surface of the microcrystalline P seed layer, that is, the microcrystalline P seed layer and the microcrystalline P main layer constitute the P-type microcrystalline doping layer, and the P-type microcrystalline doping layer forms a PN junction with the N-type single crystal silicon wafer. In this way, the P-type microcrystalline doped layer is in direct contact with the intrinsic amorphous passivation layer, so that the boron element in the P-type microcrystalline doped layer will enter the intrinsic amorphous passivation layer, destroying the grid structure of hydrogenated amorphous silicon (a-Si:H), and having a negative impact on the passivation performance; at the same time, the boron element will induce the formation of BH-Si weak bonds in the amorphous silicon layer, increasing the attenuation of the battery in a dark environment. Since the boron element has a great influence on the passivation layer, the doping ratio of the P-type microcrystalline doped layer is low, which is not conducive to contact with the transparent conductive film TCO. In addition, it is difficult to match the valence band of the intrinsic amorphous passivation layer with the P-type microcrystalline doped layer, and it is necessary to introduce an oxygen source gas (CO) into the P-type microcrystalline doped layer. 2 or N 2 However, the introduction of oxygen source gas will lead to a decrease in the crystallization rate of the P-type microcrystalline doped layer and an increase in resistance, which is not conducive to the transmission of carriers.

[0029] In order to solve the above problems, the present invention prepares an intrinsic microcrystalline silicon oxygen "barrier layer" between the intrinsic amorphous passivation layer and the P-type microcrystalline doped layer to form a Figure 2 The film structure shown. The barrier layer can be prepared using existing PECVD or HWCVD equipment, using high pressure, high hydrogen dilution ratio, and high power process to form a dense intrinsic microcrystalline layer, the barrier layer, on the surface of the intrinsic amorphous passivation layer. The barrier layer blocks the boron element in the P-type microcrystalline doping layer from entering the intrinsic passivation layer, reducing the impact of the P-type microcrystalline doping layer on the intrinsic passivation layer, increasing the Voc of the battery, and reducing the attenuation of the battery in a dark environment. At the same time, an appropriate amount of oxygen source gas (CO 2 or N 2 O), the prepared barrier layer component is intrinsic microcrystalline silicon oxygen, so as to improve the valence band matching between the intrinsic passivation layer and the P-type microcrystalline doped layer, reduce the valence band barrier, increase the tunneling probability of holes in the valence band barrier, and improve the FF of the battery.

[0030] A gradient doping scheme is adopted for the microcrystalline P main layer, that is, the microcrystalline P main layer close to the intrinsic passivation layer is low-doped, and then the doping concentration is gradually increased, and the side close to the transparent conductive film (TCO) is highly doped to match the TCO film layer. This gradient doping scheme not only reduces the impact of the P-type microcrystalline doping layer on the intrinsic passivation layer, but also increases the doping content of the P-type microcrystalline doping layer, thereby improving the contact resistance with the TCO.

[0031] An embodiment of the method for preparing a low-attenuation heterojunction battery provided by the present invention comprises the following steps: Figure 2 As shown:

[0032] Step 1: Use N-type single crystal silicon wafer (Nc-Si) as substrate, and after impurity gettering, cleaning and texturing, the thickness of the silicon wafer is 90-120um, and the velvet pyramid thereof is 2-3um high and 4-5um wide.

[0033] Step 2: Use plasma enhanced chemical vapor deposition equipment to coat three layers of intrinsic passivation layer (ia-Si:H) on the back of the substrate; from inside to outside, the thickness of the first layer is 2-4nm, the thickness of the second layer is 2-5nm, and the thickness of the third layer is 3-10nm.

[0034] A plasma enhanced chemical vapor deposition device is used to coat three layers of intrinsic passivation layer (ia-Si:H) on the front side of the substrate; from inside to outside, the thickness of the first layer is 1-3nm, the thickness of the second layer is 2-3nm, and the thickness of the third layer is 3-6nm.

[0035] At least one N-type microcrystalline doping layer is deposited on the intrinsic passivation layer (ia-Si:H) on the front side of the substrate using plasma enhanced chemical vapor deposition equipment, with a total thickness of 8-12 nm. In this embodiment, three N-type microcrystalline doping layers are deposited.

[0036] There is no particular order in which the coating is performed on the front side or the back side of the substrate. Depending on the process requirements, the coating can be performed one after the other, or the front side and the back side of the substrate can be coated simultaneously.

[0037] Step 3: Plasma enhanced chemical vapor deposition equipment is used to coat an intrinsic microcrystalline silicon oxygen barrier layer on the intrinsic passivation layer (ia-Si:H) on the back of the substrate. The power supply during coating is 5000W, the pressure is 500Pa, and the ratio of hydrogen flow rate to silane flow rate (H 2 / SiH 4 ) is 300 times, N 2 O flow rate to silane flow rate ratio (N 2 O / SiH 4 ) is 1. The barrier layer has a thickness of 2.5-4 nm and a crystallinity of 50-80%.

[0038] Since the intrinsic microcrystalline silicon oxygen barrier layer is a microcrystalline silicon film layer with a high crystallization rate and a dense texture, it is difficult for the boron element in the P-type microcrystalline doping layer to diffuse in the intrinsic microcrystalline silicon oxygen barrier layer. That is, it is difficult for the boron element to enter the intrinsic passivation layer, and the passivation layer is less affected by the boron element, thereby increasing the Voc of the battery. The continuous diffusion of the boron element into the passivation layer will cause the efficiency of the battery to decay, and at the same time produce a large number of BH-Si weak bonds, which will reduce the effective doping of the B element. Blocking the boron element from entering the intrinsic passivation layer can reduce the attenuation of the battery in the dark state. When an appropriate amount of oxygen source gas (N 2 O), generating an intrinsic microcrystalline silicon oxygen barrier layer, which can significantly improve the valence band matching between the P-type microcrystalline doping layer and the passivation layer, reduce the hole accumulation between the silicon wafer and the back intrinsic passivation layer, improve the hole transmission, reduce the contact resistance, and improve the FF of the battery.

[0039] Step 4: Plasma enhanced chemical vapor deposition equipment is used to coat a microcrystalline P seed layer on the intrinsic microcrystalline silicon oxygen barrier layer. Figure 2 The first P-type microcrystalline doped layer in the coating is 4000W, the pressure is 500Pa, the ratio of hydrogen flow to silane flow (H2 / SiH4) is 350 times, and the ratio of B2H6 flow to silane flow (B2H6 / SiH4) is 0.1%. The microcrystalline P seed layer has a thickness of 3-5nm and a crystallization rate of 50-60%.

[0040] Step 5: Plating a microcrystalline P main layer on the microcrystalline P seed layer using a plasma enhanced chemical vapor deposition device, that is, Figure 2 The power supply during the coating process was 7500W, the pressure was 500Pa, and the ratio of hydrogen flow rate to silane flow rate (H 2 / SiH 4 ) is 280 times. The thickness of the microcrystalline P main layer is 25-30nm, and the crystallization rate is 20-40%.

[0041] During the coating process of the microcrystalline P main layer, control B 2 H 6 The ratio of flow rate to silane flow rate (B 2 H 6 / SiH4) gradually increased from 0.2% to 1%, thereby changing B 2 H 6 / SiH 4 The doping ratio is adjusted to achieve gradient doping of the microcrystalline P main layer.

[0042] Since the boron atoms in the P-type microcrystalline doping layer in contact with the intrinsic passivation layer will diffuse into the intrinsic passivation layer, the less the boron atoms doping in the microcrystalline P main layer, the smaller the impact on the intrinsic passivation layer. When the doping concentration of the microcrystalline P main layer is very high, the barrier region formed by the contact between TCO / microcrystalline P main layer becomes narrower, and the corresponding barrier becomes thinner. The thin barrier can increase the tunneling probability of holes, which is beneficial to the transmission of holes and improves the contact resistance. Therefore, the use of gradient doping can reduce the impact on the passivation layer and improve the contact resistance with TCO.

[0043] Step 6: Use transparent conductive film deposition equipment (PAR PVD and RPD) to coat transparent conductive film ITO on the N-type microcrystalline doped layer on the front side of the substrate and the microcrystalline P main layer on the back side. The ITO film is a type of transparent conductive film TCO. The sheet resistance of the film is 30Ω / m, the mobility is 100cm² / Vs, and the transmittance is 98%.

[0044] Step 7: Screen printing is performed on the transparent conductive film on the front and back of the substrate respectively, and the screen-printed low-temperature silver paste has a gate line height of 15um and a width of 60um. Then drying and curing are performed to complete the metallization of the microcrystalline silicon heterojunction cell (HJT) to obtain the low-attenuation heterojunction cell of the present invention.

[0045] The following tests are conducted on the example samples of the battery prepared by the present invention and the battery samples prepared by the prior art without using a barrier layer.

[0046] The test was carried out according to the test standards of the Institute for Solar Energy Research Hamelin (ISFH) in Germany, using an IV data tester.

[0047] The steps of the test are:

[0048] First, the IV data tester is calibrated using the standard cell test of the Institute for Solar Energy Research Hamelin (ISFH) in Germany, and then the prepared cells are tested.

[0049] By testing the battery prepared by the present invention, compared with the HJT battery without the barrier layer of the present invention, the open circuit voltage (Voc) of the battery prepared by the present invention is increased by 0.5mV; the fill factor (FF) is increased by about 0.3%; the battery conversion efficiency (Efficiency) is increased by about 0.1%; and the 30-day battery dark state decay is reduced from 0.3% to 0.1%. Therefore, it can be fully explained that the main performance of the battery prepared by the present invention is improved, and the problems of the battery prepared by the prior art are effectively solved.

[0050] The above description is only a specific implementation of the present invention. It should be pointed out that any modification, equivalent substitution and change made within the spirit and framework of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a low-attenuation heterojunction battery, comprising the following steps: Step 1, using an N-type single crystal silicon wafer that has been treated with gettering, cleaning, and texturing as a substrate; Step 2, coating the intrinsic passivation layer on the back side of the substrate; coating the intrinsic passivation layer and the N-type microcrystalline doping layer on the front side of the substrate; Step 3, coating an intrinsic microcrystalline silicon oxygen barrier layer on the intrinsic passivation layer on the back side of the substrate; Step 4, coating a microcrystalline P seed layer on the intrinsic microcrystalline silicon oxygen barrier layer; Step 5, coating a microcrystalline P main layer on the microcrystalline P seed layer; Step 6, coating a transparent conductive film on the N-type microcrystalline doped layer on the front side of the substrate and the microcrystalline P main layer on the back side; Step 7: screen printing is performed on the transparent conductive films on the front and back sides of the substrate respectively, followed by drying and curing to obtain the low-attenuation heterojunction battery.

2. The preparation method according to claim 1, characterized in that In the step 3, a plasma enhanced chemical vapor deposition device is used to plate the intrinsic microcrystalline silicon oxygen barrier layer on the intrinsic passivation layer; the power supply is 5000W, the pressure is 500Pa, the ratio of hydrogen flow to silane flow is 300 times, the ratio of N2O flow to silane flow is 1, the thickness of the barrier layer is 2.5-4nm, and the crystallization rate is 50-80%.

3. The preparation method according to claim 1, characterized in that: In step 4, a plasma enhanced chemical vapor deposition device is used to plate the microcrystalline P seed layer; the power is 4000W, the pressure is 500Pa, the ratio of hydrogen flow to silane flow is 350 times, the ratio of B2H6 flow to silane flow is 0.1%, the thickness of the microcrystalline P seed layer is 3-5nm, and the crystallization rate is 50-60%.

4. The preparation method according to claim 1, characterized in that: In the step 5, the microcrystalline P main layer is plated by plasma enhanced chemical vapor deposition equipment; the power of the power supply is 7500W, the pressure is 500Pa, and the ratio of hydrogen flow to silane flow is 280 times; the thickness of the microcrystalline P main layer is 25-30nm, and the crystallization rate is 20-40%; wherein, the ratio of B2H6 flow to silane flow is controlled to gradually increase from 0.2% to 1%.

5. The preparation method according to claim 1, characterized in that: The thickness of the N-type single crystal silicon wafer is 90-120um, and the velvet pyramid thereof is 2-3um high and 4-5um wide.

6. The preparation method according to claim 1, characterized in that: In the step 2, a plasma enhanced chemical vapor deposition device is used to coat three layers of intrinsic passivation layer on the back of the substrate; from the inside to the outside, the thickness of the first layer is 2-4nm, the thickness of the second layer is 2-5nm, and the thickness of the third layer is 3-10nm.

7. The preparation method according to claim 1, characterized in that: In the step 2, a plasma enhanced chemical vapor deposition device is used to coat three layers of intrinsic passivation layer on the front side of the substrate; from the inside to the outside, the thickness of the first layer is 1-3nm, the thickness of the second layer is 2-3nm, and the thickness of the third layer is 3-6nm.

8. The preparation method according to claim 1, characterized in that: In the step 2, a plasma enhanced chemical vapor deposition device is used to coat at least one N-type microcrystalline doping layer on the intrinsic passivation layer on the front side of the substrate, with a thickness of 8-12 nm.

9. The preparation method according to claim 1, characterized in that: In the step 6, a transparent conductive film deposition device is used to deposit an ITO film; the film has a square resistance of 30Ω / m, a mobility of 100cm² / Vs, and a transmittance of 98%.

10. The preparation method according to claim 1, characterized in that: In step 7, the low-temperature silver paste for screen printing has a gate line height of 15 um and a width of 60 um.

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