An IBC battery and its preparation method

Abstract

This invention provides an IBC battery and its preparation method. In this embodiment, after boron doping, laser oxidation of the P-region can form a more dense borosilicate glass mask with stronger barrier properties. This not only gives the prepared p-type doped region the advantages of high surface concentration, high passivation performance, and low contact resistance, but also avoids the pollution problems caused by barrier or etching paste printing. Furthermore, it has higher manufacturing precision and production capacity, making it suitable for mass production.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cell manufacturing technology, and in particular to an IBC cell and its preparation method. Background Technology

[0002] Interdigitated Back Contact (IBC) batteries are a new type of battery in which the P / N junction, substrate and emitter contact electrodes are made in an interdigitated shape on the back of the battery. The core technology is to prepare high-quality p-regions and n-regions that are interdigitated and spaced apart in an interdigitated shape on the back of the battery.

[0003] In the prior art, the preparation of passivated contact IBC cells involves post-boron oxide diffusion + laser etching or blocking paste printing + etching steps. The boron-doped polycrystalline silicon layer (poly-Si(p+) region) is affected by the post-boron oxide diffusion process, and its surface doping concentration is low, which is not conducive to metal contact, has poor passivation performance, and has problems with paste contamination and alignment misalignment. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an IBC battery and its preparation method, so as to solve the problem that the boron doping concentration in the p-type doped region is low due to the influence of the post-oxidation boron expansion process in the existing IBC battery.

[0005] To solve the above problems, the present invention is achieved through the following technical solution:

[0006] This invention proposes a method for preparing an IBC battery, comprising:

[0007] A first silicon oxide layer and a first polycrystalline silicon layer are sequentially formed on the back side of a monocrystalline silicon wafer, and the first polycrystalline silicon layer is boron doped.

[0008] The boron-doped silicon wafer is subjected to chain acid washing.

[0009] Laser oxidation is performed on the first region on the back side of the silicon wafer after chain pickling to form an oxide layer; the first region is used to form a p-type doped region.

[0010] The silicon wafer after laser oxidation is subjected to double-sided alkaline etching.

[0011] A second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the silicon wafer after double-sided alkaline etching, and the second polysilicon layer is phosphorus-doped.

[0012] The phosphorus-silicon glass layer on the back side of the silicon wafer, excluding the second region after phosphorus doping is removed, wherein the second region and the first region are arranged in an interdigitated interval.

[0013] After removing the phosphosilicate glass layer outside the second region, acid washing is used to remove the phosphosilicate glass layer on the front side of the silicon wafer, and the silicon wafer is etched and texturized to expose the interdigitated n-type doped regions and p-type doped regions.

[0014] After etching and texturing, passivation and antireflection films are formed on both sides of the silicon wafer, and positive gate lines connected to the p-type doped region and negative gate lines connected to the n-type doped region are formed on the back side to obtain an IBC cell.

[0015] Furthermore, in the preparation method described above, the single-crystal silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

[0016] Furthermore, in the preparation method, boron doping of the first polycrystalline silicon layer includes:

[0017] First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900℃ for low-temperature deposition. Then, high-temperature propulsion is carried out at a temperature of 900 to 950℃. After the high-temperature propulsion is completed, the vessel is cooled and unloaded without oxygen.

[0018] Furthermore, in the preparation method, the boron doping concentration on the silicon surface after high-temperature propulsion is 1E20~4E20 cm⁻¹. -3 ; and / or

[0019] The phosphorus doping concentration on the silicon surface after phosphorus diffusion is 3E20~7E20cm⁻¹ -3 .

[0020] Furthermore, in the aforementioned preparation method, during the laser oxidation treatment of the first region on the back side of the silicon wafer after chain pickling, the laser power is 15W–55W and the marking speed is 3000–50000 mm / s; and / or

[0021] The phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after removing phosphorus doping includes:

[0022] The phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after phosphorus doping is removed by laser, wherein the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / s.

[0023] Furthermore, in the preparation method described above, the thickness of the oxide layer formed by laser oxidation treatment is 10–100 nm.

[0024] Furthermore, in the preparation method, the silicon wafer undergoes etching and texturing processes, including:

[0025] The silicon wafer is etched using 1% to 5% NaOH and etching additives by mass. Then, the silicon wafer is texturized using 0.5% to 3% NaOH and texturing additives by mass. Finally, the silicon wafer is cleaned using 5% to 30% hydrofluoric acid and O3 by mass to remove the borosilicate glass layer and phosphosilicate glass layer on the back side of the silicon wafer.

[0026] Furthermore, in the aforementioned preparation method, before sequentially forming a first silicon oxide layer and a first polycrystalline silicon layer on the back side of the monocrystalline silicon wafer, the method further includes:

[0027] The silicon wafer is subjected to alkaline polishing.

[0028] Furthermore, in the preparation method, acid washing to remove the phosphosilicate glass layer on the front side of the silicon wafer includes:

[0029] The front side of the silicon wafer is cleaned with hydrofluoric acid at a mass percentage of 5-30%.

[0030] The present invention also proposes an IBC battery, wherein the battery is prepared by the method described above.

[0031] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0032] In this embodiment of the invention, after forming a first polysilicon layer and performing boron doping and chain acid washing, the first region on the back side of the silicon wafer used to form the p-type doped region is subjected to laser oxidation treatment. Then, the silicon wafer after laser oxidation treatment is subjected to double-sided alkaline etching treatment. A second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the silicon wafer and phosphorus doping is performed. Then, the phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after phosphorus doping is removed by laser. The first region and the second region are arranged in an interdigitated interval. Next, acid washing is used to remove the phosphorus-silicon glass layer on the front side of the silicon wafer. The silicon wafer is then etched and texturized to expose the interdigitated n-type doped region and p-type doped region. Finally, a passivation film layer, an anti-reflection film layer, and positive and negative gate lines are formed. In the above process, laser oxidation of the P-region after boron doping can form a more dense borosilicate glass mask with stronger barrier properties. This not only gives the prepared p-type doped region the advantages of high surface concentration, high passivation performance and low contact resistance, but also avoids the pollution problems caused by barrier or etching paste printing. Furthermore, it has higher manufacturing precision and production capacity, making it suitable for mass production.

[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0034] Figure 1 This is a flowchart of the preparation method of the IBC battery provided in the embodiments of the present invention;

[0035] Figure 2 This is a schematic diagram of the IBC structure in this embodiment of the invention when the single-crystal silicon wafer is an N-type silicon wafer;

[0036] Figure 3 This is a schematic diagram of the IBC structure in this embodiment of the invention when the single-crystal silicon wafer is a P-type silicon wafer. Detailed Implementation

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The applicant of this invention has discovered that the current preparation of IBC cells generally requires a boron oxide diffusion followed by laser etching or a blocking paste printing followed by etching steps. The boron-doped polycrystalline silicon layer (poly-Si(p+) region) is affected by the post-boron oxide diffusion process, resulting in a low surface doping concentration, which is not conducive to metal contact, has poor passivation performance, and also has problems with paste contamination and alignment misalignment.

[0039] To address the aforementioned problems, this invention provides a method for preparing an IBC battery, comprising steps 101 to 105:

[0040] Step 101: Sequentially form a first silicon oxide layer and a first polycrystalline silicon layer on the back side of a single-crystal silicon wafer, and then dope the first polycrystalline silicon layer with boron.

[0041] Step 102: Perform chain acid washing on the boron-doped silicon wafer;

[0042] Step 103: Perform laser oxidation treatment on the first region on the back side of the silicon wafer after chain pickling to form an oxide layer; the first region is used to form a p-type doped region;

[0043] Step 104: Perform double-sided alkaline etching on the silicon wafer after laser oxidation treatment;

[0044] Step 105: A second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the double-sided alkaline etched silicon wafer, and the second polysilicon layer is phosphorus doped.

[0045] Step 106: Laser removal of the phosphorus-silicon glass layer on the back side of the silicon wafer, excluding the second region, where the second region and the first region are arranged in an interdigitated pattern.

[0046] Step 107: After removing the phosphosilicate glass layer in the second region, acid washing is performed to remove the phosphosilicate glass layer on the front side of the silicon wafer, and the silicon wafer is etched and texturized to expose the interdigitated n-type doped regions and p-type doped regions.

[0047] Step 108: After etching and texturing, a passivation film and an anti-reflection film are formed on both sides of the silicon wafer, and a positive gate line connected to the p-type doped region and a negative gate line connected to the n-type doped region are formed on the back side to obtain an IBC cell.

[0048] In this embodiment of the invention, laser oxidation of the P-region after boron doping can form a more dense borosilicate glass mask with stronger barrier properties. This not only gives the prepared p-type doped region the advantages of high surface concentration, high passivation performance, and low contact resistance, but also avoids the pollution problems caused by barrier or etching paste printing. Furthermore, it has higher manufacturing precision and production capacity, making it suitable for mass production.

[0049] In step 101 above, an N-type or P-type single-crystal silicon wafer is taken, and low-pressure chemical vapor deposition (LPCVD) is used to first pass oxygen at a flow rate of 10-30 sccm to form an ultrathin silicon oxide layer on the back side of the silicon wafer, which is the first silicon oxide layer mentioned above, as an ultrathin tunneling oxide layer. The thickness of the first silicon oxide layer can be 1-2 nm, for example, 1.5 nm. Then, using a segmented low-pressure deposition method, silane at a flow rate of 100-400 sccm is passed through at a temperature of 550-600°C to prepare a first polycrystalline silicon layer with a thickness sufficient for passivation effect on both sides or on one side. The thickness can be 200-400 nm, for example, one or any two of the values ​​of 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm. In particular, because the preparation of polycrystalline silicon layers on both sides is beneficial for the subsequent removal of the front polycrystalline silicon layer, it is less likely to result in either over-removal or under-removal, thus allowing for better control of the yield.

[0050] In step 101 above, after the first polycrystalline silicon layer is prepared, the silicon wafer is sent into the furnace tube to dope the first polycrystalline silicon layer with boron to form a p-type doped region, thereby forming a passivated contact structure composed of the first silicon oxide layer and the boron-doped polycrystalline silicon layer, effectively reducing surface recombination and metal contact recombination.

[0051] The first polycrystalline silicon layer is boron-doped using boron diffusion. Optionally, the boron doping of the first polycrystalline silicon layer includes:

[0052] First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900℃ for low-temperature deposition. Then, high-temperature propulsion is carried out at a temperature of 900 to 950℃. After the high-temperature propulsion is completed, the vessel is cooled and unloaded without oxygen.

[0053] Specifically, in the boron diffusion process, deposition is first performed at a temperature of 800–900℃, a BCl3 to O2 flow ratio of 1:2–1:5, and a BCl3 flow rate of 100–300 sccm / min for 0–50 min. Then, the silicon wafer is heated to 900–950℃ for high-temperature propulsion, and after the high-temperature propulsion is completed, it is cooled and unloaded in an oxygen-free environment, i.e., no oxygen is introduced during the cooling process. This yields a surface boron doping concentration of 1E20–4E20 cm⁻¹. -3 The p-type doped region.

[0054] In step 102 above, the boron-doped silicon wafer is subjected to chain acid washing to remove the thin borosilicate glass film on the surface of the silicon wafer; optionally, hydrofluoric acid with a mass percentage of 5-30% is used to perform chain acid washing on the boron-doped silicon wafer, which can effectively remove the thin borosilicate glass film on the front and back of the silicon wafer.

[0055] In step 103 above, the first region on the back side of the silicon wafer used to form the p-type doped region is oxidized by laser action to form a dense oxide layer. The laser power is 15W–55W, and the marking speed is 3000–50000 mm / s. This effectively oxidizes the first region on the back side of the silicon wafer to form a dense oxide layer, resulting in a boron doping surface concentration of 1E21–3E21 cm⁻¹. -3 .

[0056] Optionally, in step 103 above, the thickness of the oxide layer formed by the laser oxidation process is controlled to be 10–100 nm, which can effectively mask the p-type doped region and facilitate subsequent etching removal. For example, the thickness of the oxide layer can be one or any two of the following: 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and 100 nm.

[0057] In step 104 above, a tank-type etching chamber is used to perform double-sided alkaline etching on the laser-oxidized silicon wafer using an alkaline solution to remove the laser-damaged layer and the boron-doped layer in the non-laser areas. Optionally, in one embodiment, the alkaline solution in the double-sided alkaline etching includes etching additives and 3% to 10% NaOH or KOH by mass, the processing temperature is 60 to 90°C, and the processing time is 150 to 600 seconds.

[0058] In step 105 above, after completing the double-sided alkaline etching process, a layer of ultrathin silicon oxide, namely the second silicon oxide layer, is formed on the back side of the silicon wafer using low-pressure chemical vapor deposition (LPCVD) with oxygen at a flow rate of 10-30 sccm. This serves as an ultrathin tunneling oxide layer, and the thickness of the second silicon oxide layer can be 1-2 nm, for example, 1.5 nm. Then, using a segmented low-pressure deposition method, silane is introduced at a temperature of 550-600°C with a flow rate of 100-400 sccm to prepare a second polycrystalline silicon layer with a thickness sufficient for passivation, either on one or one side. This thickness can be 100-300 nm, for example, one or any two of the following: 100 nm, 150 nm, 200 nm, 250 nm, and 300 nm. In particular, because the preparation of polycrystalline silicon layers on both sides is beneficial for the subsequent removal of the front polycrystalline silicon layer, it is less likely to result in either over-removal or under-removal, thus allowing for better control of the yield.

[0059] In step 105 above, after the second polysilicon layer is prepared, the silicon wafer is sent into the furnace tube to dope the first polysilicon layer with phosphorus to form an n-type doped region, thereby forming a passivated contact structure composed of the second silicon oxide layer and the phosphorus-doped polysilicon layer, effectively reducing surface recombination and metal contact recombination.

[0060] The second polysilicon layer is phosphorus-doped using phosphorus diffusion. Optionally, phosphorus doping of the second polysilicon layer includes:

[0061] First, deposition was performed at a temperature of 780–880℃, a POCl3 flow rate of 80–150 sccm / min, an oxygen flow rate of 500–800 sccm / min, a nitrogen flow rate of 1000–2000 sccm / min, and a pressure of 150–200 mbar for 15–55 min. Then, the silicon wafer was heated to 850–900℃ and kept at this temperature for 10–60 min. Finally, it was treated at a pressure of 300–900 mbar and an oxygen flow rate of 2000–20000 sccm / min for 40–80 min to obtain a surface doping concentration of 3E20–7E20 / cm³. 3 The n-type doped region.

[0062] In step 106 above, the other areas on the back of the silicon wafer, other than the second region, are treated by laser action or by etching paste and screen printing. The second region is used to form an n-type doped region, and the second region is interdigitated with the first region.

[0063] Optionally, when removing the phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after phosphorus doping by laser action, the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / s, which can effectively remove the phosphorus-silicon glass layer on other regions outside the second region on the back side of the silicon wafer, achieving the effect of opening the P region and the PN isolation region.

[0064] Optionally, when removing the phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after removing the phosphorus doping by means of etching paste and screen printing, an etchable paste such as NH4F is printed in other regions outside the second region on the back side of the silicon wafer to remove the borosilicate glass layer on the surface, thereby achieving the opening of the film in the laser region. Subsequently, the polycrystalline silicon layer and etching paste in the opened film region are cleaned by wet cleaning.

[0065] In step 107 above, the phosphorus-silicon glass layer on the front side of the silicon wafer is removed first to facilitate subsequent etching to remove the phosphorus-doped polysilicon layer on the front side and to perform texturing.

[0066] Optionally, in one embodiment, the front side of the silicon wafer is cleaned with hydrofluoric acid at a mass percentage of 5-30%, thereby removing the phosphosilicate glass layer on the front side of the silicon wafer by acid washing.

[0067] In step 107 above, after removing the front phosphorus glass layer, a tank-type wet process is used to remove the phosphorus-doped polysilicon layer in the laser area on the front and back of the silicon wafer by etching and texturing, and a pyramid textured surface is formed in the gap area (PN isolation area) on the front and back of the silicon wafer.

[0068] Optionally, in one embodiment, the silicon wafer is etched and texturized, including:

[0069] The silicon wafer is etched using 1% to 5% NaOH and etching additives by mass. Then, the silicon wafer is texturized using 0.5% to 3% NaOH and texturing additives by mass. Finally, the silicon wafer is cleaned using 5% to 30% hydrofluoric acid and O3 by mass to remove the borosilicate glass layer and phosphosilicate glass layer on the back side of the silicon wafer.

[0070] In this embodiment, the phosphorus-doped polysilicon layer on the front side and the other areas (i.e., the areas where the phosphorus-silicon glass layer has been removed) are first removed by passing through an alkaline bath. Then, the front and back gap areas are textured by passing through a texturing bath. Finally, the phosphorus-silicon glass layer in the second area on the back side, the dense oxide layer in the first area, and other surface additives are removed by cleaning with hydrofluoric acid and O3, thereby exposing the interdigitated n-type doped regions and p-type doped regions.

[0071] Optionally, in another embodiment, acid etching is performed to remove the phosphosilicate glass layer on the front side of the silicon wafer, and the silicon wafer is then etched, including:

[0072] The silicon wafer is cleaned using a mixed acid, which comprises 25% to 35% HNO3 by mass and 5% to 15% HF by mass.

[0073] In this embodiment, a mixed acid of nitric acid and hydrofluoric acid is used to achieve the effect of removing the phosphorus silicate glass layer on the front side of the silicon wafer and etching it in one step.

[0074] In step 108 above, atomic layer deposition (ALD) is used to deposit a passivation layer on the entire front and back of the product to form field passivation. After forming the aluminum oxide film, plasma enhanced chemical vapor deposition (PECVD) is used to deposit an anti-reflection film on the back of the battery, and then an anti-reflection film is deposited on the front to further improve the passivation effect of the battery cell.

[0075] Optionally, the passivation layer is an aluminum oxide film layer, that is, the passivation layer is formed by depositing an aluminum oxide film layer on the entire front and the entire back side; the thickness of the passivation layer can be 1 to 10 nm.

[0076] Optionally, the aforementioned back antireflection coating can be a silicon nitride layer with a thickness of 50-120 nm, that is, the aforementioned back antireflection coating is obtained by depositing a silicon nitride layer on the entire back surface.

[0077] Optionally, the aforementioned front antireflective coating can be a silicon nitride film, a silicon nitride and silicon oxide stack, or a silicon oxynitride layer, with a thickness of 50–120 nm, which can further enhance the antireflective effect.

[0078] Optionally, in one embodiment, step 108 above, forming a positive gate line connected to the p-type doped region and a negative gate line connected to the n-type doped region on the back side, includes:

[0079] After the anti-reflection film is formed on the silicon wafer, screen printing is performed to form positive electrode grid lines that are connected to the p+ doped region and negative electrode grid lines that are connected to the n+ doped region on the back side. Then, high-temperature sintering is performed to prepare an IBC solar cell.

[0080] Optionally, in another embodiment, step 108 above, forming a positive gate line connected to the p-type doped region and a negative gate line connected to the n-type doped region on the back side, includes:

[0081] A copper-based metal seed layer with a thickness of 150–300 nm is deposited on the back side of a silicon wafer using physical vapor deposition (PVD). A photosensitive ink is then coated onto the seed layer and dried at 100°C for 8–15 minutes. Laser direct writing exposure is then used to expose the photosensitive ink on the back side of the wafer, forming a pattern where the main and sub-gates are perpendicular. After exposure of both sides of the wafer, it is transferred to a chemical solution for development and drying, ultimately resulting in trench patterns on both sides of the wafer ready for electroplating. The patterned silicon wafers on both sides are placed in an electroplating tank for electroplating. The chemical solution in the electroplating tank includes copper sulfate and various additives. Different current parameters are set on the surface of the silicon wafer. After the copper ions in the solution accept electrons, they form copper atoms and attach to the surface of the silicon wafer. Since only some of the grooved areas on the silicon wafer surface have exposed seed layers and are conductive areas, while other areas are covered with photosensitive ink and are not conductive, copper atoms will only gather on the surface of the seed layer in the attached grooves to form copper grid lines. The electroplating time is controlled so that the height of the electroplated copper grid lines does not exceed the height of the patterned grooves.

[0082] After copper plating on the back, the silicon wafer is placed in a KOH solution for film removal. The KOH mass percentage concentration is 5% and the film removal time is 6 minutes, which can remove the residual photosensitive ink on the surface of the silicon wafer.

[0083] Then, the silicon wafer is placed in an acidic solution with a certain oxidizing power to remove the metal seed layer outside the gate lines on the surface of the silicon wafer. This allows the formation of positive gate lines that are connected to the p-type doped region and negative gate lines that are connected to the n-type doped region on the back side.

[0084] Optionally, in one embodiment, the preparation method provided by the present invention further includes step 100 before step 101 described above:

[0085] The silicon wafer is subjected to alkaline polishing.

[0086] In this embodiment, before forming the first silicon oxide layer and the first polycrystalline silicon layer, the silicon wafer is subjected to alkaline polishing to remove organic contaminants and metallic impurities from its surface. Optionally, a tank-type alkaline polishing process is used to polish the silicon wafer on both sides. The alkaline polishing solution includes water, alkaline polishing additives, and 1% to 10% NaOH or KOH by mass, and the treatment time is 50s to 250s.

[0087] Please see Figure 2The diagram shows a schematic of the structure of the IBC in this embodiment of the invention when the single-crystal silicon wafer is an N-type silicon wafer. The first silicon oxide layer 21 and the second silicon oxide layer 22 are arranged in an interdigitated manner on the back side of the N-type silicon wafer 10, and a passivation layer 24 is disposed between the first silicon oxide layer 21 and the second silicon oxide layer 22. A boron-doped polycrystalline silicon layer 23 and a positive gate line 25 are sequentially disposed on the surface of the first silicon oxide layer 21, and a phosphorus-doped polycrystalline silicon layer 26 and a negative gate line 27 are sequentially disposed on the surface of the second silicon oxide layer 22. The passivation layer 24 is a stack of aluminum oxide and silicon nitride.

[0088] Please see Figure 3 The diagram shows a schematic of the IBC structure in an embodiment of the present invention when the single-crystal silicon wafer is a P-type silicon wafer. In this embodiment, a first silicon oxide layer 21 and a second silicon oxide layer 22 are arranged in an interdigitated manner on the back side of an N-type silicon wafer 20, and a passivation layer 24 is disposed between the first silicon oxide layer 21 and the second silicon oxide layer 22. A boron-doped polycrystalline silicon layer 23 and a positive gate line 25 are sequentially disposed on the surface of the first silicon oxide layer 21, and a phosphorus-doped polycrystalline silicon layer 26 and a negative gate line 27 are sequentially disposed on the surface of the second silicon oxide layer 22. The passivation layer 24 is a stack of aluminum oxide and silicon nitride.

[0089] The present invention also proposes an IBC battery, wherein the battery is prepared by the above-described method for preparing an IBC battery.

[0090] The present invention will be described in detail below through embodiments.

[0091] Example 1

[0092] (1) Take an N-type silicon wafer of 182*182 and perform double-sided alkaline polishing. The alkaline polishing solution includes alkaline polishing additives and NaOH with a mass percentage of 5%. The treatment time is 100s.

[0093] (2) A 1.5 nm thick ultrathin silicon oxide layer is formed on the back of the silicon wafer by oxygen with a flow rate of 20 sccm as the first silicon oxide layer; then, a segmented low-pressure deposition method is used to prepare a 200 nm thick first polycrystalline silicon layer on both sides by introducing silane with a flow rate of 250 sccm at a temperature of 580 °C.

[0094] (3) Boron doping of the first polycrystalline silicon layer is performed by boron diffusion. First, deposition is carried out at 850℃ for 25 minutes under conditions of a BCl3 to O2 flow ratio of 1:4 and a BCl3 flow rate of 200 sccm / min. Then, the silicon wafer is heated to 920℃ for high-temperature propulsion. After the high-temperature propulsion is completed, the wafer is cooled and unloaded without oxygen, i.e., no oxygen is introduced during the cooling process. This yields a surface doping concentration of 1E20~4E20cm⁻¹. -3 p-type doped region;

[0095] (4) Use hydrofluoric acid with a mass percentage of 15% to perform chain pickling on the boron-doped silicon wafer to remove the thin borosilicate glass film on the front and back of the silicon wafer.

[0096] (5) A dense oxide layer with a thickness of 50 nm is formed by oxidizing the first region on the back of the silicon wafer to form a p-type doped region by laser action, wherein the laser power is 35W and the marking speed is 20000 mm / second;

[0097] (6) A tank-type tank is used to perform double-sided alkaline etching on the silicon wafer after laser oxidation treatment using an alkaline solution to remove the laser damage layer and the boron doped layer in the non-laser area. The alkaline solution includes etching additives and NaOH with a mass percentage of 8%. The treatment temperature is 80℃ and the treatment time is 300s.

[0098] (7) A 1.5 nm thick ultrathin silicon oxide layer is formed on the back of the silicon wafer by passing oxygen at a flow rate of 20 sccm as the second silicon oxide layer; then, a segmented low-pressure deposition method is used to pass silane at a flow rate of 250 sccm at a temperature of 580°C to prepare a 200 nm thick second polycrystalline silicon layer on both sides.

[0099] (8) Phosphorus doping of the second polycrystalline silicon layer was performed using phosphorus diffusion. In the phosphorus diffusion process, phosphorus was first deposited at 880℃, a POCl3 flow rate of 120 sccm / min, an oxygen flow rate of 700 sccm / min, a nitrogen flow rate of 1800 sccm / min, and a pressure of 160 mbar for 10 min. Then, the silicon wafer was heated to 980℃ and treated at a pressure of 800 mbar and an oxygen flow rate of 12000 sccm / min for 70 min, resulting in a surface doping concentration of 2E20~5E20 / cm². 3 n-type doped regions;

[0100] (9) The phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after phosphorus doping is removed by laser action, wherein the laser power is 35W and the marking speed is 20000mm / second, so as to achieve the effect of opening the P region and the PN isolation region.

[0101] (10) Use 15% hydrofluoric acid by mass to clean the front side of the silicon wafer to remove the phosphosilicate glass layer on the front side of the silicon wafer;

[0102] (11) The silicon wafer is etched with alkaline etching using 2% NaOH and etching additives, and then the silicon wafer is texturized in a groove using 1% NaOH and texturing additives. Then, it is cleaned with 15% hydrofluoric acid and O3 to remove the borosilicate glass layer and phosphosilicate glass layer on the back of the silicon wafer.

[0103] (12) Take the silicon wafer after chain pickling and use atomic layer deposition process to deposit an aluminum oxide film layer with a thickness of 5nm on the entire front and back of the product to form field passivation.

[0104] (13) After forming the aluminum oxide film layer by PECVD, a first silicon nitride layer with a thickness of 80 nm is first deposited on the back of the battery as the back anti-reflection film layer, and then a second silicon nitride layer with a thickness of 80 nm is deposited on the front as the front anti-reflection film layer.

[0105] (14) A positive electrode paste that is connected to the p-type doped region is printed in the third region of the anti-reflection film layer on the back of the silicon wafer, and a negative electrode paste that is connected to the n-type doped region is printed in the fourth region of the anti-reflection film layer on the back.

[0106] (15) The silicon wafers were sintered at high temperature to obtain IBC cells.

[0107] In summary, in this embodiment, laser oxidation of the P-region after boron doping can form a more dense borosilicate glass mask with stronger barrier properties. This not only gives the prepared p-type doped region the advantages of high surface concentration, high passivation performance, and low contact resistance, but also avoids the pollution problems caused by barrier or etching paste printing. Furthermore, it has higher manufacturing precision and production capacity, making it suitable for mass production.

[0108] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0109] The above provides a detailed description of an IBC battery and its preparation method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for preparing an IBC battery, characterized in that, include: A first silicon oxide layer and a first polycrystalline silicon layer are sequentially formed on the back side of a monocrystalline silicon wafer, and the first polycrystalline silicon layer is boron doped. The boron-doped silicon wafer is subjected to chain acid washing. Laser oxidation is performed on the first region on the back side of the silicon wafer after chain pickling to form an oxide layer; the first region is used to form a p-type doped region. The silicon wafer after laser oxidation is subjected to double-sided alkaline etching. A second silicon oxide layer and a second polysilicon layer are sequentially formed on the back side of the silicon wafer after double-sided alkaline etching, and the second polysilicon layer is phosphorus-doped. The phosphorus-silicon glass layer on the back side of the silicon wafer, excluding the second region after phosphorus doping is removed, wherein the second region and the first region are arranged in an interdigitated interval. After removing the phosphosilicate glass layer outside the second region, acid washing is used to remove the phosphosilicate glass layer on the front side of the silicon wafer, and the silicon wafer is etched and texturized to expose the interdigitated n-type doped regions and p-type doped regions. After etching and texturing, passivation and antireflection films are formed on both sides of the silicon wafer, and positive gate lines connected to the p-type doped region and negative gate lines connected to the n-type doped region are formed on the back side to obtain an IBC cell.

2. The preparation method according to claim 1, characterized in that, The monocrystalline silicon wafer is an N-type silicon wafer or a P-type silicon wafer.

3. The preparation method according to claim 1, characterized in that, Boron doping of the first polycrystalline silicon layer includes: First, BCl3 and O2 with a flow ratio of 1:2 to 1:5 are introduced at a temperature of 800 to 900℃ for low-temperature deposition. Then, high-temperature propulsion is carried out at a temperature of 900 to 950℃. After the high-temperature propulsion is completed, the vessel is cooled and unloaded without oxygen.

4. The preparation method according to claim 3, characterized in that, After high-temperature propulsion, the boron doping concentration on the silicon surface is 1E20~4E20cm. -3 ; and / or The phosphorus doping concentration on the silicon surface after phosphorus diffusion is 3E20~7E20cm⁻¹ -3 .

5. The preparation method according to claim 1, characterized in that, In the laser oxidation treatment of the first area on the back side of the silicon wafer after chain pickling, the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / second. and / or The phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after removing phosphorus doping includes: The phosphorus-silicon glass layer outside the second region on the back side of the silicon wafer after phosphorus doping is removed by laser, wherein the laser power is 15W to 55W and the marking speed is 3000 to 50000 mm / s.

6. The preparation method according to claim 5, characterized in that, The thickness of the oxide layer formed by laser oxidation treatment is 10–100 nm.

7. The preparation method according to claim 1, characterized in that, The silicon wafer is etched and texturized, including: The silicon wafer is etched using 1% to 5% NaOH and etching additives by mass. Then, the silicon wafer is texturized using 0.5% to 3% NaOH and texturing additives by mass. Finally, the silicon wafer is cleaned using 5% to 30% hydrofluoric acid and O3 by mass to remove the borosilicate glass layer and phosphosilicate glass layer on the back side of the silicon wafer.

8. The preparation method according to claim 1, characterized in that, Before the first silicon oxide layer and the first polycrystalline silicon layer are sequentially formed on the back side of the monocrystalline silicon wafer, the method further includes: The silicon wafer is subjected to alkaline polishing.

9. The preparation method according to claim 1, characterized in that, Acid etching to remove the phosphosilicate glass layer on the front side of the silicon wafer includes: The front side of the silicon wafer is cleaned with hydrofluoric acid at a mass percentage of 5-30%.

10. An IBC battery, characterized in that, It is prepared by the method described in any one of claims 1 to 9.

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