Tensile strain germanium wafer on glass substrate, imaging chip and forming method thereof

Abstract

According to the tensile strain germanium wafer on the glass substrate, the imaging chip and the forming method of the imaging chip, the acceptor substrate comprises the transparent glass substrate, the light transmittance of the short-wave infrared band is extremely high, light of the short-wave infrared band can reach the tensile strain germanium layer, the transparent glass substrate can also enable visible light to penetrate, and the imaging chip can be applied to the imaging chip. Visible light can also reach the tensile strain germanium layer. Light of more wavebands enters the tensile strain germanium wafer on the glass substrate through the transparent glass substrate, the tensile strain of the tensile strain germanium layer is further increased through direct wafer bonding operation, the response capacity to incident light is improved, and the wavelength response range of the tensile strain germanium wafer on the glass substrate is expanded to be within the range of 400 nm to 1700 nm. The wafer taking the transparent glass as the substrate is large in size and low in batch production cost, can be highly compatible with a CMOS (complementary metal oxide semiconductor) process production line, can overcome the defects of fragility, high cost and the like of a bulk germanium material, and improves the quality of the tensile strain germanium wafer on the glass substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a strained germanium wafer on a glass substrate, an imaging chip, and a method for forming the same. Background Technology

[0002] Currently, Ge semiconductor materials, highly compatible with Complementary Metal Oxide Semiconductor (CMOS) processes, possess significant advantages such as epitaxy on large-size Si substrates, excellent optical response in the short-wave infrared band, and tunable bandgap (through tensile strain engineering, alloy engineering, and doping engineering). These advantages make them important candidate sensing materials for next-generation short-wave infrared imaging technology. Conventional silicon-on-germanium detectors have a wavelength response range of approximately 900-1550 nm, which cannot fully cover the conventional short-wave infrared band (900-1700 nm), resulting in a limited wavelength response range that fails to meet practical requirements. Furthermore, bulk Ge materials also suffer from drawbacks such as fragility and high cost. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a tensile strained germanium wafer on a glass substrate, an imaging chip, and a method for forming the same, which can improve the response capability to incident light, expand the wavelength response range of the tensile strained germanium wafer on the glass substrate, and improve the quality of the tensile strained germanium wafer on the glass substrate. The specific solution is as follows:

[0004] In a first aspect, this application provides a method for forming a tensile-strained germanium wafer on a glass substrate, comprising:

[0005] A donor substrate and an acceptor substrate are formed; the donor substrate includes a silicon substrate and a tensile strained germanium layer on the silicon substrate, the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all have germanium element, the first semiconductor layer and the third semiconductor layer have doping elements of opposite doping types, the doping type being P-type doping or N-type doping; the acceptor substrate includes a transparent glass substrate, and a silicon layer, a silicon dioxide layer and a dielectric layer on the transparent glass substrate;

[0006] The donor substrate and the acceptor substrate are directly wafer-bonded to obtain a bonding structure; in the bonding structure, the silicon layer, the silicon dioxide layer, the dielectric layer and the tensile strained germanium layer are located between the silicon substrate and the transparent glass substrate;

[0007] The silicon substrate in the bonding structure is removed to obtain a strained germanium wafer on a glass substrate.

[0008] Optionally, the donor substrate formation includes:

[0009] The tensile strained germanium layer is formed on the silicon substrate;

[0010] An aluminum oxide layer is formed on the tensile strained germanium layer.

[0011] Optionally, the donor substrate formation includes:

[0012] A low-temperature germanium buffer layer is formed on the silicon substrate;

[0013] The tensile strain germanium layer is formed on the low-temperature germanium buffer layer;

[0014] The process of removing the silicon substrate from the bonding structure to obtain a tensile-strained germanium wafer on a glass substrate includes:

[0015] The silicon substrate and the low-temperature germanium buffer layer in the bonding structure are removed to obtain a tensile-strained germanium wafer on the glass substrate.

[0016] Optionally, the second semiconductor layer is Ge, GeSn, SiGeSn, Ge / GeSi quantum well, Ge / GeSn quantum well, Ge / SiGeSn quantum well, or GeSn / SiGeSn quantum well.

[0017] Optionally, when the second semiconductor layer is the Ge / GeSi quantum well, the silicon content in GeSi is less than or equal to 30%.

[0018] Optionally, the material of the dielectric layer is silicon oxide or ethyl silicate.

[0019] Optionally, the method further includes:

[0020] The strained germanium wafer on the glass substrate is subjected to chemical mechanical polishing to obtain a polished strained germanium wafer on the glass substrate.

[0021] Secondly, embodiments of this application also provide a tensile strained germanium wafer on a glass substrate, prepared using the method for forming a tensile strained germanium wafer on a glass substrate as described above, including:

[0022] Transparent glass substrate;

[0023] The transparent glass substrate contains a silicon layer, a silicon dioxide layer, a dielectric layer, and a tensile strained germanium layer. The tensile strained germanium layer comprises a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all contain germanium. The first semiconductor layer and the third semiconductor layer have doping elements with opposite doping types, namely P-type doping or N-type doping.

[0024] Thirdly, embodiments of this application also provide a method for forming an imaging chip, the method comprising:

[0025] A donor substrate and an acceptor substrate are formed; the donor substrate includes a silicon substrate and a tensile strained germanium layer on the silicon substrate, the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all have germanium element, the first semiconductor layer and the third semiconductor layer have doping elements of opposite doping types, the doping type being P-type doping or N-type doping; the acceptor substrate includes a transparent glass substrate, and a silicon layer, a silicon dioxide layer and a dielectric layer on the transparent glass substrate;

[0026] The donor substrate and the acceptor substrate are directly wafer-bonded to obtain a bonding structure; in the bonding structure, the silicon layer, the silicon dioxide layer, the dielectric layer and the tensile strained germanium layer are located between the silicon substrate and the transparent glass substrate;

[0027] Remove the silicon substrate from the bonding structure to obtain a tensile strained germanium wafer on a glass substrate;

[0028] The tensile strain germanium layer in the tensile strain germanium wafer on the glass substrate is etched to form a plurality of grooves and a plurality of pixels arranged in a horizontal direction. The bottom of the grooves is located within the third semiconductor layer, and the pixels include tensile strain germanium layers located between adjacent grooves.

[0029] A surface passivation layer is formed on the tensile strain germanium layer; the surface passivation layer covers the groove and the surface of the pixel;

[0030] For each of the grooves, a first opening is formed in the surface passivation layer located at the bottom of the groove to expose the third semiconductor layer, and the first opening is filled with a first metal layer;

[0031] For each of the pixels, a second opening is formed in the surface passivation layer on the surface of the pixel to expose the first dielectric layer, and a second metal layer is filled in the second opening;

[0032] A strained germanium wafer on the glass substrate is connected to a readout circuit to form an imaging chip; the readout circuit includes a connection layer, which includes a plurality of third metal layers arranged in a horizontal direction, each of the third metal layers being electrically connected to the first metal layer or the second metal layer.

[0033] Fourthly, embodiments of this application also provide an imaging chip, fabricated using the imaging chip formation method described above, comprising:

[0034] A tensile strained germanium wafer on a glass substrate; the tensile strained germanium wafer on the glass substrate includes a transparent glass substrate, a silicon layer, a silicon dioxide layer, a dielectric layer and a tensile strained germanium layer located on the transparent glass substrate; the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all contain germanium, the first semiconductor layer and the third semiconductor layer have doping elements with opposite doping types, the doping type is P-type doping or N-type doping;

[0035] The tensile strain germanium wafer on the glass substrate includes a plurality of grooves and a plurality of pixels arranged in a horizontal direction, a surface passivation layer, a first metal layer and a second metal layer located on the tensile strain germanium layer; the bottom of the groove is located within the third semiconductor layer, the pixel includes a tensile strain germanium layer located between adjacent grooves, the surface passivation layer covers the surface of the groove and the pixel, the first metal layer is located in a first opening, the first opening is in the surface passivation layer located at the bottom of the groove, the second metal layer is located in a second opening, the second opening is in the surface passivation layer located on the surface of the pixel;

[0036] A readout circuit electrically connected to a strained germanium wafer on the glass substrate; the readout circuit includes a connection layer comprising a plurality of third metal layers arranged in a horizontal direction, each of the third metal layers being electrically connected to a first metal layer or a second metal layer.

[0037] This application provides a tensile strain germanium wafer on a glass substrate, an imaging chip, and a method for forming the same, forming a donor substrate and an acceptor substrate; the donor substrate includes a silicon substrate and a tensile strain germanium layer located on the silicon substrate, the tensile strain germanium layer has tensile strain, the tensile strain germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all have germanium elements, the first semiconductor layer and the third semiconductor layer have doping elements with opposite doping types, the doping type is P-type doping or N-type doping.

[0038] The acceptor substrate includes a transparent glass substrate, and a silicon layer, a silicon dioxide layer, and a dielectric layer located on the transparent glass substrate. Because the transparent glass substrate is transparent, it has extremely high transmittance in the short-wave infrared band, allowing short-wave infrared light to reach the tensile-strained germanium layer. Furthermore, the transparent glass substrate allows visible light to pass through, enabling visible light to reach the tensile-strained germanium layer as well. The donor and acceptor substrates are directly wafer-bonded to obtain a bonding structure. In this bonding structure, the silicon layer, silicon dioxide layer, dielectric layer, and tensile-strained germanium layer are located between the silicon substrate and the transparent glass substrate. During the direct wafer bonding process, the dielectric layer compresses the tensile-strained germanium layer, introducing tensile strain into the tensile-strained germanium layer and increasing its tensile strain. This improves the tensile-strained germanium layer's response range to incident light. Finally, the silicon substrate in the bonding structure is removed, resulting in a tensile-strained germanium wafer on the glass substrate.

[0039] As can be seen, this application allows more wavelengths of light to enter the tensile-strained germanium wafer on the glass substrate through a transparent glass substrate. Furthermore, direct wafer bonding operations can further increase the tensile strain of the tensile-strained germanium layer, improving its response to incident light and thus extending the wavelength response range of the tensile-strained germanium wafer on the glass substrate to the 400nm-1700nm range. Additionally, wafers using transparent glass substrates have larger dimensions, lower mass production costs, and are highly compatible with CMOS process lines. This overcomes the drawbacks of bulk germanium materials, such as fragility and high cost, thereby improving the quality of tensile-strained germanium wafers on glass substrates. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a method for forming a tensile-strained germanium wafer on a glass substrate, as provided in an embodiment of the application, is shown.

[0042] Figure 2-4 This illustration shows a schematic diagram of a donor substrate provided in an embodiment of this application;

[0043] Figure 5 This illustration shows a schematic diagram of a host substrate structure provided in an embodiment of this application;

[0044] Figure 6-11 This application provides a schematic diagram of a bonding structure;

[0045] Figure 12-16A schematic diagram of the structure of an imaging chip provided in an embodiment of this application is shown. Detailed Implementation

[0046] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0049] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides an embodiment of the present application of a strained germanium wafer on a glass substrate, an imaging chip, and a method for forming the same.

[0050] refer to Figure 1 The diagram shown is a schematic representation of a method for forming a tensile-strained germanium wafer on a glass substrate according to an embodiment of this application. The method includes the following steps.

[0051] S101 forms the donor substrate and the acceptor substrate.

[0052] In the embodiments of this application, a donor substrate and an acceptor substrate can be formed. The formation order of the donor and acceptor substrates is not specifically limited; the donor substrate can be formed first, followed by the acceptor substrate, or vice versa, or both can be formed simultaneously. (Reference) Figure 2 and Figure 5 As shown, the donor substrate 100 may include a silicon substrate 101 and a tensile strained germanium layer 102 located on the silicon substrate 101, and the recipient substrate 200 includes a transparent glass substrate 201, and a silicon layer 202, a silicon dioxide layer 203 and a dielectric layer 204 located on the transparent glass substrate 201.

[0053] During the formation of the donor substrate 100, a tensile strain germanium layer 102 can be formed on the silicon substrate 101. The tensile strain germanium layer 102 includes a first semiconductor layer 103, a second semiconductor layer 104, and a third semiconductor layer 105 stacked sequentially, all of which contain germanium. The second semiconductor layer 104 can serve as a light-absorbing layer. When the germanium layer is formed on silicon, there is thermal expansion adaptation between silicon and germanium, thereby introducing tensile strain into the germanium to form the tensile strain germanium layer 102.

[0054] The first semiconductor layer 103 and the third semiconductor layer 105 have doping elements with opposite doping types, namely P-type doping and N-type doping. The thickness of the first semiconductor layer 103 and the third semiconductor layer 105 can be 200-500 nm, and the thickness of the second semiconductor layer 104 can be 1000-3000 nm. When the first semiconductor layer 103 has P-type doping, the third semiconductor layer 105 has N-type doping, and when the first semiconductor layer 103 has N-type doping, the third semiconductor layer 105 has P-type doping. The second semiconductor layer 104 is undoped, that is, the tensile strained germanium layer 102 is a vertical PIN structure or a vertical NIP structure. The first semiconductor layer 103, the second semiconductor layer 104, and the third semiconductor layer 105 can be a P-type doped Ge layer, an intrinsic Ge layer, and an N-type doped Ge layer, respectively.

[0055] Next, we can introduce the formation process of the tensile strained germanium layer 102. A first semiconductor layer 103 can be formed on a silicon substrate 101 by epitaxy. Then, the first semiconductor layer 103 can be doped to form a doped first semiconductor layer 103. Next, a second semiconductor layer 104 and a third semiconductor layer 105 can be epitaxially grown on the doped first semiconductor layer 103. The third semiconductor layer 105 can be doped to form a doped third semiconductor layer 105, thereby forming the tensile strained germanium layer 102.

[0056] In one possible implementation, the donor substrate 100 may further include an aluminum oxide layer located on the tensile strained germanium layer 102, as referenced. Figure 3 As shown, the aluminum oxide layer 106 is located on the tensile strained germanium layer 102. Forming the donor substrate 100 may include forming the tensile strained germanium layer 102 on the silicon substrate 101, and forming the aluminum oxide layer 106 on the tensile strained germanium layer 102. In this way, the aluminum oxide layer 106 can serve as a bonding layer, facilitating the subsequent bonding of the donor substrate 100 and the acceptor substrate 200, and making the bonding between the two more stable.

[0057] In one possible implementation, the donor substrate 100 may further include a low-temperature germanium buffer layer 107, that is, forming the donor substrate 100 may include forming a low-temperature germanium buffer layer 107 on a silicon substrate 101 and forming a tensile strain germanium layer 102 on the low-temperature germanium buffer layer 107.

[0058] The formation of the low-temperature germanium buffer layer 107 can be carried out in a low-temperature environment, with a temperature range of 350-400℃. The thickness of the low-temperature germanium buffer layer 107 can be 100-400nm, thereby improving the morphological quality of the low-temperature germanium buffer layer 107 and facilitating the formation of a tensile strain germanium layer 102 on the low-temperature germanium buffer layer 107, ensuring that the tensile strain germanium layer 102 has a certain tensile strain force.

[0059] The donor substrate 100 may also include a low-temperature germanium buffer layer 107 and an aluminum oxide layer 106, as shown in the reference. Figure 3 The donor substrate 100 includes a silicon substrate 101, a low-temperature germanium buffer layer 107, a tensile strain germanium layer 102, and an aluminum oxide layer 106 stacked sequentially.

[0060] In this embodiment, the second semiconductor layer 104 can be a single-layer structure, and the single-layer structure is a Group 4 material, such as Ge, GeSn or SiGeSn.

[0061] In this embodiment, the second semiconductor layer 104 can also be a stacked layer, specifically it can be composed of two different material layers alternately. That is, the second semiconductor layer 104 can include an alternately stacked fourth semiconductor layer 1041 and a fifth semiconductor layer 1042, both of which are Group 4 materials.

[0062] The second semiconductor layer 104 can be a Ge / GeSi quantum well, a Ge / GeSn quantum well, a Ge / SiGeSn quantum well, or a GeSn / SiGeSn quantum well, etc. (Reference) Figure 4 The diagram shown is a schematic diagram of another strained germanium wafer on a glass substrate provided in this application embodiment. The second semiconductor layer 104 includes multiple alternating layers of a fourth semiconductor layer 1041 and a fifth semiconductor layer 1042.

[0063] When the second semiconductor layer 104 is a Ge / GeSi quantum well, that is, the second semiconductor layer 104 includes alternating stacked Ge layers and GeSi layers, wherein the silicon content in GeSi can be less than or equal to 30%, which can ensure that the second semiconductor layer 104 has good interface quality and can also ensure that the response band of the wafer is in the range of 900-1700nm.

[0064] In this embodiment, when forming the acceptor substrate 200, a silicon layer can be formed on a transparent glass substrate 201. Then, a portion of the silicon layer is thermally oxidized to form a silicon dioxide layer 203, and a dielectric layer 204 is formed on the silicon dioxide layer 203. The dielectric layer 204 can be made of silicon oxide or tetraethyl orthosilicate (TEOS). (Reference) Figure 5 The diagram shown is a schematic representation of a substrate structure provided in an embodiment of this application, comprising a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, and a dielectric layer 204 stacked sequentially.

[0065] In the host substrate 200, the transparent glass substrate 201 is transparent and has extremely high light transmittance in the short-wave infrared band, which allows the short-wave infrared light to reach the tensile strain germanium layer 102 in the bonding structure. Moreover, the transparent glass substrate 201 also allows visible light to pass through, and visible light can also reach the tensile strain germanium layer 102.

[0066] S102, the donor substrate and the acceptor substrate are directly wafer bonded to obtain a bonded structure.

[0067] In this embodiment, the donor substrate 100 and the acceptor substrate 200 can be directly wafer-bonded to obtain a bonded structure, with the transparent glass substrate 201 and the silicon substrate 101 located on the outermost side of the bonded structure. That is, in the bonded structure, the silicon layer 202, the silicon dioxide layer 203, the dielectric layer 204, and the tensile strained germanium layer 102 are all located between the silicon substrate 101 and the transparent glass substrate 201. (Reference) Figure 6 The diagram shown is a schematic of a bonding structure provided in an embodiment of this application. The bonding structure includes a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, a dielectric layer 204, a tensile strained germanium layer 102, and a silicon substrate 101 stacked sequentially.

[0068] In this way, during the direct wafer bonding process, the dielectric layer 204 will compress the tensile strain germanium layer 102 and introduce tensile strain force into the tensile strain germanium layer 102, thereby increasing the tensile strain force in the tensile strain germanium layer 102 and thus improving the response range of the tensile strain germanium layer 102 to incident light.

[0069] In one possible implementation, when the donor substrate 100 includes an aluminum oxide layer 106, the reference... Figure 7 As shown, the bonding structure obtained by bonding the donor substrate 100 and the acceptor substrate 200 specifically includes a silicon dioxide layer 203, a dielectric layer 204 and an aluminum oxide layer 106 stacked sequentially. These three layers can have a certain resonant cavity effect, which can enhance the interaction between light and the tensile strain germanium layer 102, improve the light response of the tensile strain germanium layer 102, and improve the photoresponse.

[0070] S103, remove the silicon substrate from the bonding structure to obtain a strained germanium wafer on a glass substrate.

[0071] Specifically, the silicon substrate 101 located at the top layer of the bonding structure can be removed to expose the first semiconductor layer 103, as shown in the reference. Figure 8 As shown, tensile-strained germanium on glass (tensile-strained GOG) wafers are thus obtained on a glass substrate.

[0072] refer to Figure 9 As shown, the bonding structure includes a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, a dielectric layer 204, an aluminum oxide layer 106, a tensile strained germanium layer 102, a low-temperature germanium buffer layer 107, and a silicon substrate 101 stacked sequentially.

[0073] As can be seen, the transparent glass substrate 201 allows more wavelengths of light to enter the tensile-strained germanium wafer on the glass substrate, including both short-wave infrared and visible light. Furthermore, direct wafer bonding further increases the tensile strain of the tensile-strained germanium layer 102. Increased tensile strain enhances the response of the tensile-strained germanium layer 102 to incident light, thus expanding the wavelength response range of the tensile-strained germanium wafer on the glass substrate. The maximum wavelength response can be extended from 1500nm to 1700nm, while the minimum wavelength response can be extended from 900nm to 400nm, resulting in a total wavelength response range of 400nm-1700nm. Additionally, wafers using transparent glass substrates have larger dimensions, lower mass production costs, and are highly compatible with CMOS process lines. This overcomes the fragility and high cost of bulk germanium materials, thereby improving the quality of tensile-strained germanium wafers on glass substrates. Tensile-strained germanium wafers on glass substrates also possess excellent high-resistivity characteristics, heat dissipation characteristics, low RF loss, and low high-frequency crosstalk.

[0074] In one possible implementation, when the donor substrate 100 includes a low-temperature germanium buffer layer 107, after removing the silicon substrate 101 from the bonding structure, reference... Figure 10 As shown, the silicon substrate 101 has been removed from the bonding structure. Next, the low-temperature germanium buffer layer 107 needs to be removed. This can be done using tetramethylammonium hydroxide (TMAH), which exposes the first semiconductor layer 103. (Refer to...) Figure 8 As shown, a tensile-strained germanium wafer is obtained on a glass substrate. In this way, by removing the silicon substrate 101 and the low-temperature germanium buffer layer 107, a large number of mismatch defects between them can be removed, thereby improving the wafer quality.

[0075] In this embodiment of the application, a tensile-strained germanium wafer on a glass substrate can be subjected to chemical mechanical polishing (CMP) to obtain a polished tensile-strained germanium wafer on a glass substrate, thereby improving the flatness of the wafer surface.

[0076] refer to Figure 11 As shown, when the second semiconductor layer 104 is a stacked structure, the second semiconductor layer 104 includes an alternately stacked fourth semiconductor layer 1041 and a fifth semiconductor layer 1042. Then, the tensile strain germanium wafer on the glass substrate includes a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, a dielectric layer 204, an aluminum oxide layer 106, and a tensile strain germanium layer 102 stacked sequentially.

[0077] Based on the above embodiments, this application also provides a method for forming a tensile strained germanium wafer on a glass substrate, which is prepared using the aforementioned method for forming a tensile strained germanium wafer on a glass substrate.

[0078] refer to Figure 8 The diagram shown is a schematic diagram of a tensile strain germanium wafer on a glass substrate provided in an embodiment of this application, including a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, a dielectric layer 204, a low-temperature germanium buffer layer 106, and a tensile strain germanium layer 102 stacked sequentially.

[0079] In this embodiment, the tensile strain germanium layer 102 includes a first semiconductor layer 103, a second semiconductor layer 104, and a third semiconductor layer 105 stacked sequentially. The first semiconductor layer 103, the second semiconductor layer 104, and the third semiconductor layer 105 all contain germanium. The first semiconductor layer 103 and the third semiconductor layer 105 have doping elements with opposite doping types, namely P-type doping or N-type doping.

[0080] The tensile-strained germanium wafer on the glass substrate is formed on a transparent glass substrate 201. Because the transparent glass substrate 201 is transparent, it has extremely high transmittance in the short-wave infrared band, allowing short-wave infrared light to reach the tensile-strained germanium layer 102. Furthermore, the transparent glass substrate 201 also allows visible light to pass through, enabling visible light to reach the tensile-strained germanium layer 102 as well. The tensile-strained germanium layer 102 has a large tensile strain, which improves its response range to incident light, extending it to the 400nm-1700nm range. Additionally, wafers using transparent glass substrates have larger dimensions, lower mass production costs, and are highly compatible with CMOS process lines. This overcomes the drawbacks of bulk germanium materials, such as fragility and high cost, thereby improving the quality of the tensile-strained germanium wafer on the glass substrate.

[0081] This application embodiment also provides a method for forming an imaging chip, which can be a visible light-shortwave infrared focal plane array imaging chip. The method for forming the imaging chip can include steps S201-S208.

[0082] S201 forms the donor substrate and the acceptor substrate.

[0083] Specifically, the donor substrate 100 includes a silicon substrate 101 and a tensile strained germanium layer 102 located on the silicon substrate 101. The tensile strained germanium layer 102 includes a first semiconductor layer 103, a second semiconductor layer 104, and a third semiconductor layer 105 stacked sequentially. The first semiconductor layer 103, the second semiconductor layer 104, and the third semiconductor layer 105 all contain germanium. The first semiconductor layer 103 and the third semiconductor layer 105 have doping elements with opposite doping types, namely P-type doping or N-type doping. The acceptor substrate 200 includes a transparent glass substrate 201, and a silicon layer, a silicon dioxide layer 203, and a dielectric layer 204 located on the transparent glass substrate 201.

[0084] S202, the donor substrate and the acceptor substrate are directly wafer bonded to obtain a bonded structure.

[0085] In the bonding structure, silicon layer 202, silicon dioxide layer 203, dielectric layer 204 and tensile strained germanium layer 102 are located between silicon substrate 101 and transparent glass substrate 201.

[0086] S203, remove the silicon substrate from the bonding structure to obtain a strained germanium wafer on a glass substrate.

[0087] In other words, after forming a tensile-strained germanium wafer on a glass substrate, the tensile-strained germanium wafer on the glass substrate can be processed by steps S203-S208 to obtain an imaging chip, and the tensile-strained germanium layer 102 can be used as the sensing material of the imaging chip.

[0088] In one possible implementation, the silicon substrate 101 and the low-temperature germanium buffer layer 107 are removed during the formation of the strained germanium wafer on the glass substrate. This can remove a large number of mismatch defects between the two, improve the wafer quality, and play a crucial role in improving key performance indicators of the imaging chip such as dark current, photoresponsivity, quantum efficiency, and spectral response range.

[0089] S204, etching the tensile strain germanium layer in the tensile strain germanium wafer on the glass substrate to form multiple grooves and multiple pixels arranged in the horizontal direction, the bottom of the grooves being located within the third semiconductor layer, and the pixels including tensile strain germanium layers located between adjacent grooves.

[0090] In this embodiment of the application, the tensile strain germanium layer 102 in the tensile strain germanium wafer on the glass substrate can be etched to obtain a plurality of grooves arranged in the horizontal direction. Specifically, a mask can be used for masking to etch a plurality of grooves.

[0091] refer to Figure 12 The diagram shown is a schematic representation of an imaging chip provided in an embodiment of this application. A tensile-strained germanium wafer on a glass substrate has multiple pixels and grooves. The bottom of the grooves is located inside the third semiconductor layer 105; that is, the grooves completely penetrate the first semiconductor layer 103 and the second semiconductor layer 104, and partially penetrate the third semiconductor layer 105.

[0092] Specifically, the tensile strain germanium layer 102 between adjacent grooves can be used as a pixel, that is, the protrusion can be used as a pixel. In this way, multiple pixels arranged at intervals can be obtained by etching.

[0093] S205 forms a surface passivation layer on the tensile strained germanium layer.

[0094] Specifically, a surface passivation layer 301 can be formed on the tensile strain germanium layer 102. The surface passivation layer 301 can cover the surface of the groove and the surface of the pixel. The material of the surface passivation layer can be alumina, silicon nitride, etc., which can reduce the dark current in the imaging chip. (Reference) Figure 13 As shown, the surface passivation layer 301 is located on the surface of the tensile strain germanium layer 102.

[0095] S206, for each groove, a first opening is formed in the surface passivation layer located at the bottom of the groove to expose the third semiconductor layer, and the first opening is filled with a first metal layer.

[0096] In this embodiment, the surface passivation layer 301 has a portion located within the groove and a portion located on the pixel surface. For each groove, a first opening can be formed in the surface passivation layer 301 located at the bottom of the groove. The first opening exposes the third semiconductor layer 105. Then, a first metal layer 302 is filled into the first opening. The first metal layer 302 can serve as an electrode, allowing it to contact the third semiconductor layer 105 and thus enabling the extraction of the third semiconductor layer 105. Alternatively, after filling the first opening with the first metal layer 302, a portion of the first metal layer 302 can also be present on top of the surface passivation layer 301 to increase its area, thereby facilitating subsequent connection with the readout circuit 304. (Reference) Figure 14 As shown, each groove has a first metal layer 302 inside the first opening and above the surface passivation layer 301.

[0097] S207, for each pixel, a second opening is formed in the surface passivation layer located on the surface of the pixel to expose the first dielectric layer, and a second metal layer is filled in the second opening.

[0098] In this embodiment, for each pixel, a second opening can be formed in the surface passivation layer 301 located on the pixel surface. The second opening is used to expose the first semiconductor layer 103. A second metal layer 303 is filled in each second opening. The second metal layer 303 can serve as an electrode to achieve contact between the second metal layer 303 and the first semiconductor layer 103, thereby leading out the first semiconductor layer 103. The first metal layer 302 and the second metal layer 303 can be the same metal or different metals.

[0099] After the second opening is filled with the second metal layer 303, a portion of the second metal layer 303 can also be present on the surface passivation layer 301, thereby increasing the area of ​​the second metal layer 303 and facilitating subsequent connection with the read-out integrated circuit (ROIC). (Reference) Figure 15 As shown, a second metal layer 303 is present inside the second opening of each pixel and above the surface passivation layer 301.

[0100] S208 connects a strained germanium wafer on a glass substrate to a readout circuit to form an imaging chip.

[0101] In this embodiment, after forming the first metal layer 302 and the second metal layer 303, the tensile-strained germanium wafer and the readout circuit 304 on the glass substrate can be bump-bonded to obtain an imaging chip. (Reference) Figure 16 As shown, the readout circuit 304 includes a circuit layer 306 and a connection layer. The circuit layer 306 is used to read the current in the tensile strain germanium layer 102, and the connection layer is used to extract the current in the tensile strain germanium layer 102.

[0102] The connection layer may include a plurality of third metal layers 305 arranged in a horizontal direction, which are used for electrical connection with the first metal layer 302 or the second metal layer 303. All the first metal layers 302 can be connected in series as a common electrode, and the plurality of second metal layers 303 can each serve as a plurality of electrodes. Alternatively, all the second metal layers 303 can also be connected in series as a common electrode, and the plurality of first metal layers 302 can each serve as a plurality of electrodes.

[0103] It is understandable that, since the first metal layer 302 is located in the groove and the second metal layer 303 is located on the pixel surface, the third metal layer 305 in the readout circuit 304 is designed to be able to connect to both the first metal layer 302 and the second metal layer 303 simultaneously. The thickness of the third metal layer 305 connected to the first metal layer 302 is greater than the thickness of the third metal layer 305 connected to the second metal layer 303, thereby ensuring that the third metal layer 305 can be connected to both the first metal layer 302 and the second metal layer 303.

[0104] refer to Figure 16 As shown, the readout circuit 304 is connected to the strained germanium wafer on the glass substrate, a portion of the third metal layer 305 is connected to the first metal layer 302, and a portion of the third metal layer 305 is connected to the second metal layer 303. The arrows indicate the incident direction of the light.

[0105] Therefore, the transparent glass substrate 201, being transparent, has extremely high transmittance in the short-wave infrared band, allowing short-wave infrared light to reach the tensile strained germanium layer 102. Furthermore, the transparent glass substrate 201 also allows visible light to pass through, enabling visible light to reach the tensile strained germanium layer 102 as well. During direct wafer bonding, the dielectric layer 204 compresses the tensile strained germanium layer 102, introducing tensile strain into it and increasing its response range to incident light, extending it to the 400nm-1700nm range. Additionally, wafers using transparent glass substrates have larger dimensions, lower mass production costs, and are highly compatible with CMOS process lines. This overcomes the fragility and high cost of bulk germanium materials, thereby improving the quality of tensile strained germanium wafers on glass substrates.

[0106] In the embodiments of this application, when the donor substrate 100 includes an aluminum oxide layer 106, the stacking of the silicon dioxide layer 203, the dielectric layer 204, and the aluminum oxide layer 106 will have a certain resonant cavity effect, which can enhance the interaction between light and the tensile strain germanium layer 102, improve the light response of the tensile strain germanium layer 102, improve the photoresponsivity, and is beneficial to the improvement of the photoresponsivity of the imaging chip in the 1310nm and 1550nm bands.

[0107] In the embodiments of this application, since the imaging chip does not have contacting silicon and germanium, a large number of mismatch defects between Ge and Si can be removed, which is beneficial to reducing the dark current of the visible light-shortwave infrared focal plane array imaging chip and improving the chip quality.

[0108] In this embodiment, the second semiconductor layer 104 can be a stacked layer, specifically, it can be composed of two different material layers alternately. That is, the second semiconductor layer 104 can include an alternately stacked fourth semiconductor layer 1041 and a fifth semiconductor layer 1042, both of which are Group 4 materials.

[0109] The second semiconductor layer 104 can be a Ge / GeSi quantum well, a Ge / GeSn quantum well, a Ge / SiGeSn quantum well, or a GeSn / SiGeSn quantum well, which can improve the photoresponsivity and quantum efficiency of the imaging chip. When the second semiconductor layer 104 is a Ge / GeSi quantum well structure, the photoresponsivity and quantum efficiency of the imaging chip at 1550nm can be significantly improved.

[0110] This application also provides an imaging chip, which is prepared using the imaging chip formation method described above. (Refer to...) Figure 16 The image shown is a schematic diagram of an imaging chip provided in an embodiment of this application. The imaging chip includes:

[0111] A tensile strained germanium wafer on a glass substrate; the tensile strained germanium wafer on a glass substrate includes a transparent glass substrate 201, a silicon layer 202, a silicon dioxide layer 203, a dielectric layer 204 and a tensile strained germanium layer 102 located on the transparent glass substrate 201; the tensile strained germanium layer 102 includes a first semiconductor layer 103, a second semiconductor layer 104 and a third semiconductor layer 105 stacked sequentially, the first semiconductor layer 103, the second semiconductor layer 104 and the third semiconductor layer 105 all have germanium elements, the first semiconductor layer 103 and the third semiconductor layer 105 have doping elements with opposite doping types, the doping type is P-type doping or N-type doping;

[0112] The tensile strain germanium wafer on the glass substrate includes a plurality of grooves and a plurality of pixels arranged in a horizontal direction, a surface passivation layer 301, a first metal layer 302 and a second metal layer 303 located on the tensile strain germanium layer; the bottom of the groove is located within a third semiconductor layer, the pixel includes a tensile strain germanium layer located between adjacent grooves, the surface passivation layer covers the surface of the groove and the pixel, the first metal layer 302 is located in a first opening, the first opening is in the surface passivation layer located at the bottom of the groove, the second metal layer 303 is located in a second opening, the second opening is in the surface passivation layer located on the surface of the pixel;

[0113] A readout circuit electrically connected to a strained germanium wafer on a glass substrate; the readout circuit includes a circuit layer 305 and a connection layer, the connection layer including a plurality of third metal layers 304 arranged in a horizontal direction, each third metal layer 304 being electrically connected to a first metal layer 302 or a second metal layer 303.

[0114] In this application, a transparent glass substrate allows light of more wavelengths to enter the tensile-strained germanium wafer on the glass substrate. The tensile-strained germanium layer in the imaging chip fabricated using this glass substrate has a large tensile strain, which improves the response to incident light and thus expands the wavelength response range of the imaging chip to 400nm-1700nm. Furthermore, wafers using transparent glass substrates have larger dimensions, lower mass production costs, and are highly compatible with CMOS process lines. This overcomes the drawbacks of bulk germanium materials, such as fragility and high cost, thereby improving the quality of the imaging chip.

[0115] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0116] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a tensile-strained germanium wafer on a glass substrate, characterized in that, include: A donor substrate and an acceptor substrate are formed; the donor substrate includes a silicon substrate and a tensile strained germanium layer on the silicon substrate, the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all have germanium element, the first semiconductor layer and the third semiconductor layer have doping elements of opposite doping types, the doping type being P-type doping or N-type doping; the acceptor substrate includes a transparent glass substrate, and a silicon layer, a silicon dioxide layer and a dielectric layer on the transparent glass substrate; The donor substrate and the acceptor substrate are directly wafer-bonded to obtain a bonding structure; in the bonding structure, the silicon layer, the silicon dioxide layer, the dielectric layer and the tensile strained germanium layer are located between the silicon substrate and the transparent glass substrate; The silicon substrate in the bonding structure is removed to obtain a strained germanium wafer on a glass substrate.

2. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 1, characterized in that, The formation of the donor substrate includes: The tensile strained germanium layer is formed on the silicon substrate; An aluminum oxide layer is formed on the tensile strained germanium layer.

3. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 1, characterized in that, The formation of the donor substrate includes: A low-temperature germanium buffer layer is formed on the silicon substrate; The tensile strain germanium layer is formed on the low-temperature germanium buffer layer; The process of removing the silicon substrate from the bonding structure to obtain a tensile-strained germanium wafer on a glass substrate includes: The silicon substrate and the low-temperature germanium buffer layer in the bonding structure are removed to obtain a tensile-strained germanium wafer on the glass substrate.

4. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 1, characterized in that, The second semiconductor layer is Ge, GeSn, SiGeSn, Ge / GeSi quantum well, Ge / GeSn quantum well, Ge / SiGeSn quantum well, or GeSn / SiGeSn quantum well.

5. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 4, characterized in that, When the second semiconductor layer is the Ge / GeSi quantum well, the silicon content in GeSi is less than or equal to 30%.

6. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 1, characterized in that, The dielectric layer is made of silicon oxide or ethyl silicate.

7. The method for forming a tensile-strained germanium wafer on a glass substrate according to claim 1, characterized in that, The method further includes: The strained germanium wafer on the glass substrate is subjected to chemical mechanical polishing to obtain a polished strained germanium wafer on the glass substrate.

8. A tensile-strained germanium wafer on a glass substrate, characterized in that, The method for forming a tensile strained germanium wafer on a glass substrate as described in any one of claims 1-7 includes: Transparent glass substrate; The transparent glass substrate contains a silicon layer, a silicon dioxide layer, a dielectric layer, and a tensile strained germanium layer. The tensile strained germanium layer comprises a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked sequentially. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all contain germanium. The first semiconductor layer and the third semiconductor layer have doping elements with opposite doping types, namely P-type doping or N-type doping.

9. A method for forming an imaging chip, characterized in that, The method includes: A donor substrate and an acceptor substrate are formed; the donor substrate includes a silicon substrate and a tensile strained germanium layer on the silicon substrate, the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all have germanium element, the first semiconductor layer and the third semiconductor layer have doping elements of opposite doping types, the doping type being P-type doping or N-type doping; the acceptor substrate includes a transparent glass substrate, and a silicon layer, a silicon dioxide layer and a dielectric layer on the transparent glass substrate; The donor substrate and the acceptor substrate are directly wafer-bonded to obtain a bonding structure; in the bonding structure, the silicon layer, the silicon dioxide layer, the dielectric layer and the tensile strained germanium layer are located between the silicon substrate and the transparent glass substrate; Remove the silicon substrate from the bonding structure to obtain a tensile strained germanium wafer on a glass substrate; The tensile strain germanium layer in the tensile strain germanium wafer on the glass substrate is etched to form a plurality of grooves and a plurality of pixels arranged in a horizontal direction. The bottom of the grooves is located within the third semiconductor layer, and the pixels include tensile strain germanium layers located between adjacent grooves. A surface passivation layer is formed on the tensile strain germanium layer; the surface passivation layer covers the groove and the surface of the pixel; For each of the grooves, a first opening is formed in the surface passivation layer located at the bottom of the groove to expose the third semiconductor layer, and the first opening is filled with a first metal layer; For each of the pixels, a second opening is formed in the surface passivation layer on the surface of the pixel to expose the first dielectric layer, and a second metal layer is filled in the second opening; A strained germanium wafer on the glass substrate is connected to a readout circuit to form an imaging chip; the readout circuit includes a connection layer, which includes a plurality of third metal layers arranged in a horizontal direction, each of the third metal layers being electrically connected to the first metal layer or the second metal layer.

10. An imaging chip, characterized in that, The imaging chip is fabricated using the method for forming an imaging chip as described in claim 9, comprising: A tensile strained germanium wafer on a glass substrate; the tensile strained germanium wafer on the glass substrate includes a transparent glass substrate, a silicon layer, a silicon dioxide layer, a dielectric layer and a tensile strained germanium layer located on the transparent glass substrate; the tensile strained germanium layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked sequentially, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all contain germanium, the first semiconductor layer and the third semiconductor layer have doping elements with opposite doping types, the doping type is P-type doping or N-type doping; The tensile strain germanium wafer on the glass substrate includes a plurality of grooves and a plurality of pixels arranged in a horizontal direction, a surface passivation layer, a first metal layer and a second metal layer located on the tensile strain germanium layer; the bottom of the groove is located within the third semiconductor layer, the pixel includes a tensile strain germanium layer located between adjacent grooves, the surface passivation layer covers the surface of the groove and the pixel, the first metal layer is located in a first opening, the first opening is in the surface passivation layer located at the bottom of the groove, the second metal layer is located in a second opening, the second opening is in the surface passivation layer located on the surface of the pixel; A readout circuit electrically connected to a strained germanium wafer on the glass substrate; the readout circuit includes a connection layer comprising a plurality of third metal layers arranged in a horizontal direction, each of the third metal layers being electrically connected to a first metal layer or a second metal layer.

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