Metal-insulator-metal device structures and methods of forming same

Abstract

Embodiments of the present disclosure provide a metal-insulator-metal device (MIM) structure and a method of forming the same. The MIM capacitor device structure includes a first conductive layer and a dielectric stack disposed on first and second portions of the first conductive layer. The dielectric stack includes a first dielectric layer disposed on the first conductive layer, a high-K dielectric layer disposed on the first dielectric layer, and a second dielectric layer disposed on the high-K dielectric layer. The structure also includes a second conductive layer disposed on the dielectric stack, a first conductive feature extending through the first conductive layer and a first portion of the dielectric stack, and a second conductive feature extending through a second portion of the dielectric stack and the second conductive layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically to a metal-insulator-metal device structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid evolution. Technological advances in IC materials and design have resulted in successive generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing, and similar advances have been required in the processing and manufacturing of ICs to achieve these advances. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component that can be created using a manufacturing process) has decreased.

[0003] Many ICs involve capacitor structures for storing charge in various semiconductor devices. These capacitor structures include, for example, metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors can be used for mixed signal devices and logic devices, such as embedded memories and radio frequency devices. MIM capacitors exhibit better frequency and temperature characteristics. In addition, MIM capacitors are formed in or on metal interconnect layers, thereby reducing the interaction or complexity of CMOS transistor process integration. Summary of the invention

[0004] According to one aspect of the present application, a structure is provided, comprising: a first conductive layer, comprising a first portion and a second portion; a dielectric stack, arranged on the first portion and the second portion of the first conductive layer, wherein the dielectric stack comprises: a first dielectric layer, arranged on the first portion and the second portion of the first conductive layer; a high-K dielectric layer, arranged on the first dielectric layer; and a second dielectric layer, arranged on the high-K dielectric layer; a second conductive layer, arranged on the dielectric stack, wherein the second conductive layer comprises a first portion and a second portion; a first conductive feature, extending through the first portion of the first conductive layer, the first portion of the dielectric stack, and the first portion of the second conductive layer; and a second conductive feature, extending through the second portion of the first conductive layer, the second portion of the dielectric stack, and the second portion of the second conductive layer.

[0005] In some implementations, the first dielectric layer and the second dielectric layer each include TiON.

[0006] In some implementations, the first dielectric layer and the second dielectric layer have different thicknesses.

[0007] In some implementations, the first conductive layer and the second conductive layer each include TiN.

[0008] In some implementations, the high-K dielectric layer has a top oxygen concentration and a bottom oxygen concentration, wherein the top oxygen concentration is significantly greater than the bottom oxygen concentration.

[0009] In some implementations, the ratio of the bottom oxygen concentration to the top oxygen concentration is in a range of 0.91 to 0.99.

[0010] In some implementations, the high-K dielectric layer has a top nitrogen concentration and a bottom nitrogen concentration, wherein the bottom nitrogen concentration is significantly greater than the top nitrogen concentration.

[0011] In some implementations, the ratio of the bottom nitrogen concentration to the top nitrogen concentration is in the range of 2-5.

[0012] According to one aspect of the present application, a method is provided, comprising: depositing a first conductive layer on a substrate; patterning the first conductive layer to form a first portion and a second portion of the first conductive layer; forming a dielectric stack on the first portion and the second portion of the first conductive layer, comprising: depositing a first dielectric layer; performing a treatment process; depositing a high-K dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-K dielectric layer; depositing a second conductive layer on the dielectric stack; and patterning the second conductive layer to form a first portion and a second portion of the second conductive layer.

[0013] In some implementations, the treatment process is performed prior to depositing the first dielectric layer.

[0014] In some implementations, the treatment process is performed after depositing the first dielectric layer.

[0015] In some implementations, the treatment process is a plasma nitridation process.

[0016] In some implementations, the treatment process is a N2 plasma treatment process, a NH3 plasma treatment process, or a combination thereof.

[0017] In some implementations, the high-K dielectric layer is deposited by atomic layer deposition.

[0018] In some implementations, oxygen vacancies are formed at the bottom of the high-K dielectric layer.

[0019] In some implementations, the method further includes filling the oxygen vacancies with F, H, and N.

[0020] According to one aspect of the present application, a method is provided, comprising: depositing a first conductive layer on a substrate; forming a dielectric stack on the first conductive layer, comprising: depositing the first dielectric layer; performing a nitridation process on the first dielectric layer to form a nitride layer; depositing a high-K dielectric layer on the nitride layer, wherein a first oxygen concentration at a top of the high-K dielectric layer is significantly greater than a second oxygen concentration at a bottom of the high-K dielectric layer; and depositing a second dielectric layer on the high-K dielectric layer; and depositing a second conductive layer on the dielectric stack.

[0021] In some implementations, the method further includes forming a first conductive feature through the first portion of the dielectric stack and the first conductive layer, and forming a second conductive feature through the second portion of the dielectric stack and the second conductive layer.

[0022] In some implementations, the first dielectric layer includes TiO, the nitride layer includes TiON, and the second dielectric layer includes TiON.

[0023] In some implementations, the high-K dielectric layer is deposited by atomic layer deposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0025] Figure 1A-1I is a cross-sectional side view of a metal-insulator-metal (MIM) capacitor device structure at various stages of fabrication, according to some embodiments.

[0026] Figure 1E-1 According to some embodiments Figure 1E An enlarged cross-sectional side view of the dielectric stack of a MIM capacitor device structure.

[0027] Figure 2 The concentrations of various materials in the dielectric stack of a MIM capacitor device structure are illustrated in accordance with some embodiments.

[0028] Figure 3A-3C Graphs illustrate the concentrations of TiO, F, and H in a dielectric stack of a MIM capacitor device structure according to some embodiments.

[0029] Figure 4 The atomic percentages of various materials in the bottom of the high-K dielectric layer of a MIM capacitor device structure are illustrated in accordance with some embodiments.

[0030] Figure 5A A forward biased MIM capacitor is illustrated in accordance with some embodiments.

[0031] Figure 5B A reverse biased MIM capacitor is illustrated in accordance with some embodiments.

[0032] Fig. 6A A multi-plate MIM capacitor is illustrated in accordance with some embodiments.

[0033] Figure 6B According to some embodiments Fig. 6A Electrical equivalent circuit of a multi-plate MIM capacitor. DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0035] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0036] Some embodiments of the present disclosure have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or removed. Additional features may be added to the semiconductor device structure. For different embodiments, some of the features described below may be replaced or removed. Although operations are performed in a specific order when discussing some embodiments, these operations may be performed in another logical order.

[0037] Embodiments of the present disclosure relate to MIM capacitor device structures and methods of manufacturing MIM capacitor device structures. Some embodiments provide a MIM capacitor device structure, including a dielectric stack formed between two conductive layers. The dielectric stack includes a high-K dielectric layer disposed between two TiON layers. The dielectric stack and its formation method can result in improvements in forward bias time-dependent dielectric breakdown (TDDB) lifetime and reverse bias TDDB lifetime.

[0038] Figure 1A-1I 2 is a cross-sectional side view of a metal-insulator-metal (MIM) capacitor device structure 200 at different stages of fabrication according to some embodiments. Figure 1A-1I Additional operations may be provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or removed for other embodiments of the method. The order of the operations / processes is not limiting and may be interchangeable.

[0039] like Figure 1A As shown, MIM capacitor device structure 200 includes substrate 202, device layer 204 formed within substrate 202 and / or formed on a front side of substrate 202, and interconnect structure 206 formed over device layer 204. MIM capacitors may be formed on and within interconnect structure 206.

[0040] In some embodiments, substrate 202 may be a semiconductor substrate (e.g., a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc.), which may be doped, for example, with a P-type or N-type dopant, or may be undoped. Substrate 202 may be a wafer, such as a silicon wafer. In general, an SOI substrate includes a semiconductor material layer formed on an insulator layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 202 may include: silicon; germanium; a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and / or GaInAsP); or a combination thereof. Substrate 202 may also include isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may surround and isolate various device elements in the device layer 204 .

[0041] The device layer 204 includes device elements formed in and / or on the substrate 202. The device elements may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), diodes, and / or other applicable elements. In some embodiments, the device elements are formed in the substrate 202 using a front-end-of-line (FEOL) process.

[0042] The interconnect structure 206 includes various conductive features, such as a first plurality of conductive features 210 and a second plurality of conductive features 212, and an intermetallic dielectric (IMD) layer 208 for separating and isolating the various conductive features 210, 212. In some embodiments, the first plurality of conductive features 210 are conductive lines, and the second plurality of conductive features 212 are conductive vias. The interconnect structure 206 includes multiple levels of conductive features 210, and the conductive features 210 are arranged in each level to provide electrical paths for various device elements arranged in the device layer 204 below. The conductive features 212 provide vertical electrical routing from the device layer 204 to the conductive features 210 and between the conductive features 210. For example, the bottommost conductive feature 212 of the interconnect structure 206 can be electrically connected to conductive contacts above the source / drain regions and gate electrodes of transistors disposed in the device layer 204.

[0043] The IMD layer 208 includes one or more dielectric materials to provide isolation functions for various conductive features 210, 212. The IMD layer 208 may include multiple levels that embed multiple levels of conductive features 210, 212. One level of the interconnect structure 206 may be a layer of the IMD layer 208. These layers are sometimes referred to as M1, M2, .... M10, M11, etc., where M1 is closest to the device layer 204. In some embodiments, the conductive features 210 on the topmost IMD layer are referred to as top metal and are represented as conductive features 210TL, 210TR.

[0044] The IMD layer 208 may be made of a dielectric material, such as SiO x 、SiO x C y H z , SiOCN, SiON or SiO x C y, where x, y, and z are integers or non-integers. In some embodiments, the IMD layer 208 includes a low-k dielectric material having a k value less than the k value of silicon dioxide. In some embodiments, the IMD layer 208 may include an etch stop layer between the layers of low-k dielectric material to facilitate patterning and formation of the conductive features 210, 212. The etch stop layer may be made of silicon carbide (SiC), silicon nitride (Si x N y ), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or other suitable materials.

[0045] Conductive features 210 and conductive features 212 may be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive features 210 and conductive features 212 are made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, titanium silicon nitride, platinum, chromium, molybdenum, hafnium, iridium, other suitable conductive materials, or combinations thereof. In some embodiments, a barrier layer (not shown) may be formed between IMD layer 208 and conductive features 210, 212 to prevent conductive features 210, 212 from diffusing into the dielectric material of IMD layer 208. The barrier layer may be made of titanium (Ti), a titanium alloy, tantalum (Ta), or a tantalum alloy. For example, the barrier layer may be made of tantalum nitride (TaN).

[0046] In some embodiments, before forming the MIM capacitor, a planarization process, a chemical mechanical polishing (CMP) process, and / or a cleaning process may be performed to expose the topmost conductive feature 210T. Two topmost conductive features 210TL and 210TR are shown and will be connected to the electrodes of the capacitor to be formed. Figure 1A As shown, the topmost conductive features 210TL and 210TR are exposed on the top surface 206 t of the interconnect structure 206 .

[0047] like Figure 1B As shown, an insulating layer 214 is formed over the interconnect structure 206. In some embodiments, the insulating layer 214 may include an etch stop layer 216 and a dielectric layer 218 sequentially deposited over the interconnect structure 206. The etch stop layer 216 may include silicon carbide (SiC), silicon nitride (Si x N y ), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or other suitable materials. In some embodiments, the etch stop layer 216 can be formed by performing a plasma enhanced chemical vapor deposition (CVD) process, a low pressure CVD process, an atomic layer deposition (ALD) process or other suitable processes.

[0048] The dielectric layer 218 may include undoped silicate glass (USG), fluorinated silicate glass (FSG), carbon-doped silicate glass, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the dielectric layer 218 may be formed by a chemical vapor deposition (CVD) process, a spin-on plating process, a sputtering process, or a combination thereof. In some embodiments, the thickness of the dielectric layer 218 is in a range of about 300 nanometers to about 500 nanometers. Figure 1B As shown, dielectric layer 218 may have a substantially planar top surface 218t.

[0049] like Figure 1C As shown, a conductive layer 220 is deposited on the top surface 218t of the dielectric layer 218. The conductive layer 220 can be formed of a suitable conductive material. In some embodiments, the conductive layer 220 is formed of titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN) or a combination thereof. In some embodiments, the conductive layer 220 can be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The thickness of the conductive layer 220 can be in the range of about 10 nm to about 100 nm.

[0050] like Figure 1D As shown, the conductive layer 220 can be patterned to form two or more parts (electrodes). Processes such as the following items can be performed: photolithography, maskless photolithography, etching, or various processes suitable for transferring patterns to the conductive layer. Each part of the conductive layer 220 can form various shapes (viewed from the top) in the xy plane, such as circular, curved, rectangular, straight, polygonal (including rounded polygonal) and / or other suitable shapes. In some embodiments, two parts of the conductive layer 220 overlap with the topmost conductive features 210TL, 210TR. One of the two parts of the conductive layer 220 can be used as the bottom electrode of the MIM capacitor. After forming the parts of the conductive layer 220, a cleaning process can be performed to remove the etchant remaining in the process chamber.

[0051] like Figure 1E As shown, dielectric stack 222 is formed over portions of conductive layer 220 and dielectric layer 218 . Figure 1E-1 is an enlarged cross-sectional side view of the dielectric stack 222. Figure 1E-1As shown, the dielectric stack 222 includes a first dielectric layer 224, a high-K dielectric layer 226 formed on the first dielectric layer 224, and a second dielectric layer 228 formed on the high-K dielectric layer 226. The first dielectric layer and the second dielectric layer 224, 228 may include any suitable dielectric material. In some embodiments, the first dielectric layer 224 and the second dielectric layer 228 each include TiON. It is believed that with the second dielectric layer 228, the MIM capacitor can operate at high temperatures (e.g., in a temperature range of about 100 degrees Celsius to about 125 degrees Celsius) without being decomposed.

[0052] The high-K dielectric layer 226 can be used as an insulator of the MIM capacitor. In some embodiments, the high-K dielectric layer 226 includes a dielectric material having a dielectric constant (k) value in the range of about 10 to about 35. The high-K dielectric layer 226 can be an oxide of the following materials: Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, or other suitable materials. Exemplary high-dielectric materials for the high-K dielectric layer 226 can include: Al2O3, ZrO2, Ta2O5, HfO2, La2O3, TiO2, SiO2, or a combination thereof. In some embodiments, the high-K dielectric layer 226 includes HfO2, ZrO2 or Hf x Zr 1-x O2 (0 < x < 1). In some embodiments, the high-K dielectric layer 226 is formed by a plasma-enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, an atomic layer deposition (ALD) process, a molecular beam deposition (MBD) process, or other suitable processes. In some embodiments, the thickness of the high-K dielectric layer 226 is less than about 6 nanometers. In some embodiments, the high-K dielectric layer 226 is a crystalline high-K dielectric material and is deposited by ALD.

[0053] The dielectric stack 222 may be formed by different methods and may result in different characteristics of the MIM capacitor. In some embodiments, the first method includes performing a treatment process on portions of the conductive layer 220 before forming the first dielectric layer 224. The treatment process may be one or more plasma treatments. In some embodiments, the treatment process utilizes nitrogen-containing plasma. In some embodiments, the treatment process is an N2 plasma treatment process, an NH3 plasma treatment process, or a combination thereof. The exposed portion of the dielectric layer 218 may also be treated by the treatment process. After the treatment process, a dielectric layer is deposited on the treated surface of each portion of the conductive layer 220 and the treated surface of the dielectric layer 218. The dielectric layer reacts with the treated surface of the conductive layer 220 and the treated surface of the dielectric layer 218 to form the first dielectric layer 224. In some embodiments, the dielectric layer is TiO, and the first dielectric layer 224 is TiON. In some embodiments, the first thickness of the dielectric layer is in the range of about 4 angstroms to about 6 angstroms. The second dielectric layer 228 may be formed by any suitable process. In some embodiments, the second dielectric layer 228 is formed by depositing a dielectric layer (eg, a TiO layer) on the high-K dielectric layer 226 and then forming a conductive layer 230 (eg, a TiO layer) on the dielectric layer. Figure 1F ). In some embodiments, the conductive layer 230 includes TiN and is formed by a PVD process. The PVD process may result in a nitridation / re-sputtering effect on the dielectric layer, thereby forming the second dielectric layer 228. In some embodiments, the second dielectric layer 228 includes TiON. The second thickness of the dielectric layer (TiO) used to form the second dielectric layer 228 may be greater than the first thickness of the dielectric layer (TiO) used to form the first dielectric layer 224. In some embodiments, the second thickness is in the range of about 9 angstroms to about 11 angstroms. In some embodiments, the thickness of the first dielectric layer 224 is significantly greater than the thickness of the second dielectric layer 228. For example, the thickness of the first dielectric layer 224 is in the range of about 10 angstroms to about 25 angstroms, while the thickness of the second dielectric layer 228 is several angstroms. The MIM capacitor having the dielectric stack 222 formed by the first method described above has a forward bias TDDB lifetime ranging from about 0.02 years to about 0.22 years and a reverse bias TDDB lifetime ranging from about 0.0027 years to about 0.0047 years.

[0054] In some embodiments, the second method includes reducing the second thickness of the dielectric layer used to form the second dielectric layer 228 to be the same as the first thickness of the dielectric layer used to form the first dielectric layer 224, and the first dielectric layer 224 is formed by the same process as described above. As a result, the MIM capacitor formed by the second method has a forward bias TDDB lifetime ranging from about 4.23 years to about 4.43 years, and has a reverse bias TDDB lifetime ranging from about 0.0014 years to about 0.0034 years.

[0055] In some embodiments, the third method includes reducing the second thickness of the dielectric layer used to form the second dielectric layer 228 to be the same as the first thickness of the dielectric layer used to form the first dielectric layer 224, and the process of forming the first dielectric layer 224 is changed. For example, a dielectric layer (TiO) is first deposited on portions of the dielectric layer 218 and the conductive layer 220, and a treatment process is performed on the dielectric layer to form the first dielectric layer 224. Using a thinner dielectric layer to form the second dielectric layer 228 and performing a treatment process after depositing the dielectric layer to form the first dielectric layer 224, the MIM capacitor has a forward bias TDDB lifetime in the range of about 5.0 years to about 5.2 years, and has a reverse bias TDDB lifetime in the range of about 5.18 years to about 5.38 years. A comparison of the characteristics of the dielectric stack 222 formed by the first method, the second method, and the third method is described as follows.

[0056] like Figure 1F As shown, conductive layer 230 is deposited on dielectric stack 222. Conductive layer 230 may include the same material as conductive layer 220 and may be deposited by the same process as conductive layer 220. The thickness of conductive layer 230 may be in a range from about 10 nm to about 100 nm. In some embodiments, first conductive layer 220 and second conductive layer 230 each include TiN. Figure 1G As shown, a patterning process is performed on the conductive layer 230 to form two or more portions of the conductive layer 230. The patterning process may be the same patterning process as that used to form the portions of the conductive layer 220. A portion of the portions of the conductive layer 230 may be used as a top electrode of the MIM capacitor. In some embodiments, the MIM capacitor includes the conductive layer 220 as a bottom electrode, the dielectric stack 222 as an insulator, and the conductive layer 230 as a top electrode, and the MIM capacitor is a symmetrical structure relative to the center line of the high-K dielectric layer 226.

[0057] like Figure 1HAs shown, dielectric layer 232 is deposited on portions of conductive layer 230 and dielectric stack 222. In some embodiments, dielectric layer 232 may include the same material as dielectric layer 218 and may be formed by the same process as dielectric layer 218. In some embodiments, dielectric layer 232 may include undoped silicate glass (USG), fluorinated silicate glass (FSG), carbon-doped silicate glass, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, dielectric layer 232 may be formed by a chemical vapor deposition (CVD) process, a spin plating process, a sputtering process, or a combination thereof. In some embodiments, the thickness of dielectric layer 232 is in the range of about 300 nm to about 500 nm.

[0058] like Fig. 1I As shown, conductive features 234L and 234R are formed through portions of conductive layer 230, dielectric stack 222, portions of conductive layer 220, and insulating layer 214. In some embodiments, conductive feature 234L is electrically connected to conductive feature 210TL, and conductive feature 234R is electrically connected to conductive feature 210TR. Fig. 1I As shown. Conductive features 234L, 234R may each include copper, aluminum, AlCu and / or other suitable materials. In some embodiments, before forming conductive features 234L, 234R, a barrier layer (not shown) may be deposited at the opening, and conductive features 234L, 234R may be formed on the barrier layer. In some embodiments, the portion of conductive layer 220 electrically connected to conductive feature 234L is the bottom electrode of the MIM capacitor, high-K dielectric layer 226 is the insulator of the MIM capacitor, and the portion of conductive layer 230 electrically connected to conductive feature 234R is the top electrode of the MIM capacitor. Conductive features 234L, 234R provide electrical connections to the MIM capacitor.

[0059] Figure 2 2 illustrates the concentration of various materials in the dielectric stack 222 of the MIM capacitor device structure 200 according to some embodiments. Figure 2 As shown, dielectric stack 222 includes two TiO concentration peaks, indicating the presence of first dielectric layer 224 and second dielectric layer 228 .

[0060] Figure 3A-3C Graphs illustrate the concentrations of TiO, F, and H in the dielectric stack 222 of the MIM capacitor device structure 200 according to some embodiments. Figure 3AAs shown, in some embodiments, TiO concentration profile 302 is the result of forming dielectric stack 222 by a first method (i.e., performing a treatment process before depositing dielectric layer (TiO)), and the second thickness of second dielectric layer 228 is significantly greater than the first thickness of first dielectric layer 224. In some embodiments, TiO concentration profile 304 is the result of forming dielectric stack 222 by a second method (i.e., performing a treatment process before depositing dielectric layer (TiO)), and the second thickness of second dielectric layer 228 is substantially the same as the first thickness of first dielectric layer 224. In some embodiments, TiO concentration profile 306 is the result of forming dielectric stack 222 by a third method (i.e., performing a treatment process after depositing dielectric layer (TiO)), and the second thickness of second dielectric layer 228 is substantially the same as the first thickness of first dielectric layer 224.

[0061] like Figure 3B As shown, in some embodiments, F concentration curve 308 is the result of forming dielectric stack 222 by a first method, F concentration curve 310 is the result of forming dielectric stack 222 by a second method, and F concentration curve 312 is the result of forming dielectric stack 222 by a third method. Figure 3C As shown, in some embodiments, H concentration curve 314 is the result of forming dielectric stack 222 by a first method, H concentration curve 316 is the result of forming dielectric stack 222 by a second method, and H concentration curve 318 is the result of forming dielectric stack 222 by a third method.

[0062] As described above, the MIM capacitor formed by the first method has a forward bias TDDB lifetime in the range of about 0.02 years to about 0.22 years, and has a reverse bias TDDB lifetime in the range of about 0.0027 years to about 0.0047 years, the MIM capacitor formed by the second method has a forward bias TDDB lifetime in the range of about 4.23 years to about 4.43 years, and has a reverse bias TDDB lifetime in the range of about 0.0014 years to about 0.0034 years, and the MIM capacitor formed by the third method has a forward bias TDDB lifetime in the range of about 5.0 years to about 5.2 years, and has a reverse bias TDDB lifetime in the range of about 5.18 years to about 5.38 years. Therefore, in some embodiments, even if the dielectric stack 222 is a three-layer structure (first dielectric layer 224, high-K dielectric layer 226, and second dielectric layer 228), the characteristics of the MIM capacitor may be different due to different methods of forming the dielectric stack 222. Without being bound by a particular theory, it is believed that a higher concentration of F and H at the interface between the high-K dielectric layer 226 and the first dielectric layer 224 results in a longer forward bias TDDB lifetime and a longer reverse bias TDDB lifetime. The source of F and H may be a deposition chamber for depositing the dielectric layer (TiO) and / or a processing chamber for performing a treatment process. F and H may be used to clean the deposition chamber and / or the treatment chamber. Therefore, residual F and H from the inner cavity surface may be incorporated into the MIM capacitor device structure 200. In some embodiments, the third method is performed, and since the treatment process is performed after the deposition process, more F and H are incorporated into the MIM capacitor device structure 200.

[0063] Figure 4 Graphs illustrate the atomic percentages of various materials in the bottom portion of the high-K (HK) dielectric layer 226 of the MIM capacitor device structure 200 according to some embodiments. Figure 4As shown, the numbers under scenario 1 are the results of the first method, the numbers under scenario 2 are the results of the second method, and the numbers under scenario 3 are the results of the third method. The oxygen concentration at the bottom of the high-K dielectric layer 226 formed by the third method is significantly lower than the oxygen concentration at the bottom of the high-K dielectric layer 226 formed by the first method or the second method. The difference is in the range of about 1.5 atomic percent to about 2 atomic percent. In some embodiments, due to the use of the third method, the oxygen concentration at the top of the high-K dielectric layer 226 is greater than the oxygen concentration at the bottom of the high-K dielectric layer 226. For example, the ratio of the bottom oxygen concentration to the top oxygen concentration is less than 1, such as about 0.91 to about 0.99. Without being bound by a particular theory, it is believed that the lower oxygen concentration produced by the third method is the result of a treatment process after the dielectric layer (TiO) is deposited. The treatment process forms a nitrogen-rich surface of the first dielectric layer 224. In some embodiments, the high-K dielectric layer 226 is formed by an ALD process. The first precursor can be a metal-containing precursor, such as a Zr-containing or Hf-containing precursor. The metal-containing precursor has a greater affinity for nitrogen-rich surfaces. Therefore, more molecules of the metal-containing precursor are adsorbed on the surface of the first dielectric layer 224 compared to the processes of the first method and the second method. The second precursor of the ALD process for forming the high-K dielectric layer 226 can be an oxygen-containing precursor. Due to limited space, non-stoichiometric oxidation states of the metal-containing precursor may occur. In other words, the lack of oxygen leads to oxygen vacancies in the high-K dielectric layer 226, for example, at the bottom of the high-K dielectric layer 226. As FIG. 3A to FIG. 3C As described above, a high concentration of F and H is accumulated at the interface between the high-K dielectric layer 226 and the first dielectric layer 224, which is the result of F and H filling the oxygen vacancies. In some embodiments, nitrogen in the first dielectric layer 224 (as a result of the treatment process) may diffuse into the high-K dielectric layer 226 to fill the oxygen vacancies. Figure 4 As shown, the nitrogen concentration in scenario 3 is significantly higher than that in scenarios 1 and 2. In some embodiments, in scenario 3, the nitrogen concentration at the bottom of the high-K dielectric layer 226 is greater than the nitrogen concentration at the top of the high-K dielectric layer 226. For example, the ratio of the bottom nitrogen concentration to the top nitrogen concentration is greater than 1, such as about 2 to about 5. However, when comparing the three scenarios, the difference in nitrogen concentration cannot make up for the difference in oxygen concentration. It is believed that in scenario 3, F and H fill the oxygen vacancies that are not filled by nitrogen. The third method improves both the forward bias TDDB lifetime and the reverse bias TDDB lifetime. One of the reasons may be that the N, F and H passivated oxygen-vacancies in the high-K dielectric layer 226 improve the electrical performance of the high-K dielectric layer 226. In addition, the MIM capacitor device structure 200 formed by the third method includes a capacitor having a capacitance of approximately 50.82 fF / μm 2 to about 52.82fF / μm2 The forward capacitance and about 50.19fF / μm 2 to about 52.19fF / μm 2 The reverse capacitance of the MIM capacitor.

[0064] Figure 5A illustrates a forward biased MIM capacitor according to some embodiments, and Figure 5B FIG. 2 shows a reverse biased MIM capacitor according to some embodiments. Figure 5A As shown, the MIM capacitor 500 includes a bottom electrode, an insulator disposed above the bottom electrode, and a top electrode disposed above the insulator. In some embodiments, the bottom electrode is a conductive layer 220 ( Fig. 1I ), the insulator is a dielectric stack 222 ( Fig. 1I ), and the top electrode is a conductive layer 230 ( Fig. 1I ). In a forward biased circuit, the bottom electrode is connected to ground (GND) and the top electrode is connected to a positive voltage (Vdd). In some embodiments, the conductive feature 234L ( Fig. 1I ) is connected to GND, and conductive feature 234R is connected to Vdd.

[0065] like Figure 5B As shown, the bottom electrode is connected to Vdd, and the top electrode is connected to GND. Therefore, Figure 5B The MIM capacitor 500 shown in FIG. 5 is reverse biased.

[0066] Fig. 6A A multi-plate MIM capacitor 600 is illustrated in accordance with some embodiments. Fig. 6A As shown, the multi-plate MIM capacitor 600 includes a first electrode 602, a first dielectric stack 604 disposed over the first electrode 602, a second electrode 606 disposed over the first dielectric stack 604, a second dielectric stack 608 disposed over the second electrode 606, a third electrode 610 disposed over the second dielectric stack 608, a third dielectric stack 612 disposed over the third electrode 610, and a fourth electrode 614 disposed over the third dielectric stack 612. In some embodiments, the first, second, third, and fourth electrodes 602, 606, 610, 614 include the same material as the conductive layer 220, and the first, second, and third dielectric stacks 604, 608, 612 include the same material as the dielectric stack 222. In some embodiments, the dielectric stacks 604, 608, 612 are formed by the third method described above. Figure 6B According to some embodiments Fig. 6A Electrical equivalent circuit of a multi-plate MIM capacitor.

[0067] Various embodiments or examples described herein have multiple advantages over the state of the art. In some embodiments, a dielectric stack 222 is disposed between two electrodes of a MIM capacitor. The dielectric stack 222 includes a high-K dielectric layer 226 disposed between a first dielectric layer 224 and a second dielectric layer 228. The three-layer dielectric stack 222 enables the MIM capacitor to operate at a higher temperature. In addition, by performing a treatment process after depositing the dielectric layer (TiO), the forward bias TDDB lifetime and the reverse bias TDDB lifetime are improved.

[0068] One embodiment is a MIM capacitor device structure. The structure includes: a first conductive layer, including a first portion and a second portion; a dielectric stack, disposed on the first portion and the second portion of the first conductive layer. The dielectric stack includes: a first dielectric layer, disposed on the first portion and the second portion of the first conductive layer; a high-K dielectric layer, disposed on the first dielectric layer; and a second dielectric layer, disposed on the high-K dielectric layer. The structure also includes: a second conductive layer, disposed on the dielectric stack, and the second conductive layer includes a first portion and a second portion. The structure also includes: a first conductive feature, extending through a first portion of the first conductive layer, a first portion of the dielectric stack, and a first portion of the second conductive layer; and a second conductive feature, extending through a second portion of the first conductive layer, a second portion of the dielectric stack, and a second portion of the second conductive layer.

[0069] Another embodiment is a method. The method includes: depositing a first conductive layer on a substrate; patterning the first conductive layer to form a first portion and a second portion of the first conductive layer, and forming a dielectric stack on the first portion and the second portion of the first conductive layer. Forming the dielectric stack includes: depositing the first dielectric layer; performing a treatment process; depositing a high-K dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-K dielectric layer. The method also includes: depositing a second conductive layer on the dielectric stack; and patterning the second conductive layer to form a first portion and a second portion of the second conductive layer.

[0070] A further embodiment is a method. The method includes: depositing a first conductive layer on a substrate; forming a dielectric stack on the first conductive layer. Forming the dielectric stack includes: depositing the first dielectric layer; performing a nitridation process on the first dielectric layer to form a nitride layer, and depositing a high-K dielectric layer on the nitride layer. A first oxygen concentration at a top of the high-K dielectric layer is significantly greater than a second oxygen concentration at a bottom of the high-K dielectric layer. Forming the dielectric stack also includes: depositing a second dielectric layer on the high-K dielectric layer. The method also includes: depositing a second conductive layer on the dielectric stack.

[0071] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A structure comprising: A first conductive layer including a first portion and a second portion; a dielectric stack disposed on the first portion and the second portion of the first conductive layer, wherein the dielectric stack comprises: a first dielectric layer disposed on the first portion and the second portion of the first conductive layer; a high-K dielectric layer disposed on the first dielectric layer; and a second dielectric layer, disposed on the high-K dielectric layer; a second conductive layer disposed on the dielectric stack, wherein the second conductive layer comprises a first portion and a second portion; a first conductive feature extending through the first portion of the first conductive layer, a first portion of the dielectric stack, and the first portion of the second conductive layer; and A second conductive feature extends through the second portion of the first conductive layer, a second portion of the dielectric stack, and the second portion of the second conductive layer.

2. The structure according to claim 1, wherein: The first dielectric layer and the second dielectric layer each include TiON.

3. The structure according to claim 2, wherein: The first dielectric layer and the second dielectric layer have different thicknesses.

4. The structure according to claim 2, wherein: The first conductive layer and the second conductive layer each include TiN.

5. The structure according to claim 1, wherein: The high-K dielectric layer has a top oxygen concentration and a bottom oxygen concentration, wherein the top oxygen concentration is significantly greater than the bottom oxygen concentration.

6. The structure according to claim 5, wherein: The ratio of the bottom oxygen concentration to the top oxygen concentration is in a range of 0.91 to 0.

99.

7. The structure according to claim 1, wherein: The high-K dielectric layer has a top nitrogen concentration and a bottom nitrogen concentration, wherein the bottom nitrogen concentration is significantly greater than the top nitrogen concentration.

8. The structure according to claim 7, wherein: A ratio of the bottom nitrogen concentration to the top nitrogen concentration is in a range of 2 to 5.

9. A method comprising: depositing a first conductive layer on the substrate; patterning the first conductive layer to form a first portion and a second portion of the first conductive layer; forming a dielectric stack on the first portion and the second portion of the first conductive layer, comprising: depositing a first dielectric layer; Execute treatment process; depositing a high-K dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-K dielectric layer; depositing a second conductive layer over the dielectric stack; and The second conductive layer is patterned to form a first portion and a second portion of the second conductive layer.

10. A method comprising: depositing a first conductive layer on the substrate; forming a dielectric stack on the first conductive layer, comprising: depositing a first dielectric layer; performing a nitridation process on the first dielectric layer to form a nitride layer; depositing a high-K dielectric layer on the nitride layer, wherein a first oxygen concentration at a top of the high-K dielectric layer is significantly greater than a second oxygen concentration at a bottom of the high-K dielectric layer; and depositing a second dielectric layer on the high-K dielectric layer; and A second conductive layer is deposited over the dielectric stack.

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