Compiling tasks for streaming operations at neural processor

Abstract

Embodiments relate to compiling neural network operations into tasks that can be executed in a streaming manner by a neural processor. In the streaming operation, tensors are spatially segmented, and tasks associated with two or more layers of the neural network are performed simultaneously in an overlapping manner. To achieve efficient memory usage during streaming operations, a subset of tasks whose completion times are temporally close are assigned to the same portion of memory in a neural processor during a compilation process. After the task assigned to the same portion of the memory is completed, the portion of the memory may be refreshed to make space for a subsequent task. Multiple tasks may also be coalesced into a single task to reduce the number of tasks and perform operations more efficiently at the neural processor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 946,409, filed on September 16, 2023, which is incorporated herein by reference in its entirety. Background Art Technical Field

[0003] The present disclosure relates to scheduling operations associated with a neural network, and more particularly to compiling operations of multiple tensor layers in a neural network into tasks that can be executed in a streaming manner by a neural processor.

[0004] Related technical description

[0005] An artificial neural network (ANN) is a computing system or model that uses a collection of connected nodes to process input data. ANNs are typically organized into layers, where different layers perform different types of transformations on their inputs. Extensions or variants of ANNs such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), and deep belief networks (DBNs) have received a lot of attention. These computing systems or models typically involve a wide range of computational operations, including multiplication and accumulation. For example, CNN is a class of machine learning techniques that primarily uses convolutions between input data and kernel data, which can be decomposed into multiplication and accumulation operations.

[0006] Depending on the type of input data and the operations to be performed, these machine learning systems or models can be configured differently. Such varying configurations will include, for example, preprocessing operations, the number of channels in the input data, the kernel data to be used, the nonlinear functions to be applied to the convolution results, and the application of various post-processing operations. It is relatively easy to instantiate and execute machine learning systems or models of various configurations using a central processing unit (CPU) and its main memory, because such systems or models can be instantiated simply by updating the code. However, relying solely on the CPU for various operations of these machine learning systems or models will consume a lot of CPU bandwidth and increase overall power consumption. Summary of the invention

[0007] Embodiments are directed to compiling neural network operations into tasks to be executed by a neural processor in a streaming manner. During the compilation process, the compiler determines a spatial partitioning of a first tensor and a second tensor associated with the neural network. Determines the spatial partitioning of the first tensor and the second tensor into a plurality of partitions. Derives the second tensor by performing a convolution on the first tensor by the neural processor. Determines dependencies of the tasks, each task corresponding to one or more of the plurality of partitions. Generates a first task schedule of the tasks that satisfies the dependencies of the tasks. Allocates a first subset of the tasks having a completion time at the neural processor that satisfies a first timing constraint to a same first portion of a memory in the neural processor for storage.

[0008] In some embodiments, a first subset of tasks with completion times within a first time frame is allocated to a first portion of a buffer memory for storage, and a second subset of tasks with completion times within a second time frame is allocated to a second portion of a buffer memory for storage. When the first subset of tasks is completed, the data processor circuit releases the first portion of the buffer memory after the end of the first time frame, and when the second subset of tasks is completed, the second portion of the buffer memory is released after the end of the second time frame.

[0009] In some embodiments, the number of partitions in each task is adjusted according to the hardware configuration of the neural processor. The hardware configuration may be associated with the size of the memory in the neural processor.

[0010] In some embodiments, adjusting the number of partitions in each task includes merging two or more tasks to generate an updated task, determining dependencies of the updated task, and generating a second task schedule for the updated task that satisfies the dependencies of the updated task. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a high-level diagram of an electronic device according to one embodiment.

[0012] Figure 2 is a block diagram illustrating components in an electronic device according to one embodiment.

[0013] Figure 3 is a block diagram illustrating a neural processor circuit according to one embodiment.

[0014] Figure 4A is a block diagram of a neural engine in a neural processor circuit according to one embodiment.

[0015] Figure 4B An example is given according to one embodiment. Figure 4A Example convolution operations performed in a streaming fashion at the Neural Engine of .

[0016] Figure 5 An example of performing convolution operations on multiple convolutional layers in a streaming manner according to one embodiment is illustrated.

[0017] Fig. 6A is a block diagram of a neural task manager of a neural processor circuit according to one embodiment.

[0018] Figure 6B An example is given according to an embodiment Fig. 6A An example of a task memory in the Neural Task Manager.

[0019] Figure 7 is a block diagram of a compiler that may be implemented at a data processor circuit of a neural processor circuit, according to one embodiment.

[0020] Figure 8 An example of spatial partitioning of a tensor according to one embodiment is illustrated.

[0021] Fig. 9A and Fig. 9B An example of dependency relationships between partitions in different layers according to one embodiment is illustrated.

[0022] Fig.10 An example dependency graph representing dependency relationships between partitions or tasks in multiple tensor layers according to one embodiment is illustrated.

[0023] Fig.11 An example of buffer allocation between tasks in different tensor layers according to one embodiment is illustrated.

[0024] FIG. 12A to FIG. 12C Illustrate an example of allocating a portion of a buffer memory for storing and Fig.11 Examples of tasks corresponding to the tasks shown.

[0025] Fig.13 is a flow chart illustrating a method of compiling operations into multiple tasks to be executed in a streaming manner by a neural processor circuit according to one embodiment.

[0026] Fig.14 is a flow chart illustrating another method of compiling operations into multiple tasks to be executed in a streaming manner by neural engine circuitry according to one embodiment.

[0027] For purposes of illustration only, the Brief Description of the Drawings and the Detailed Description describe various non-limiting embodiments. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. Many specific details are shown in the following detailed description to provide a full understanding of the various described embodiments. However, the embodiments may be implemented without these specific details. In other cases, well-known methods, processes, components, circuits and networks are not described in detail, thereby not unnecessarily obscuring various aspects of the embodiments.

[0029] Embodiments relate to compiling neural network operations into tasks that can be executed by a neural processor in a streaming manner. In a streaming operation, tensors are spatially partitioned and tasks associated with two or more layers of a neural network are executed simultaneously in an overlapping manner. To achieve efficient memory usage during a streaming operation, during the compilation process, a subset of tasks that are close in time to completion are assigned to the same portion of memory in a neural processor. After the tasks assigned to the same portion of memory are completed, the portion of memory can be refreshed to make room for subsequent tasks. Multiple tasks can also be aggregated into a single task to reduce the number of tasks and perform operations more efficiently at the neural processor.

[0030] Exemplary Electronic Devices

[0031] Embodiments of electronic devices, user interfaces for such devices, and associated processes for using such devices are described. In some embodiments, the device is a portable communication device, such as a mobile phone, that also includes other functions, such as a personal digital assistant (PDA) and / or a music player function. Exemplary embodiments of portable multifunction devices include, but are not limited to, the Apple Watch from Apple Inc. (Cupertino, California). Devices, iPod Devices, Apple Equipment and Device. Other portable electronic devices, such as wearable devices, laptops, or tablet computers may alternatively be used. In some embodiments, the device is not a portable communication device, but rather a desktop computer or other computing device not designed for portable use. In some embodiments, the disclosed electronic device may include a touch-sensitive surface (e.g., a touch screen display and / or a touchpad). Figure 1 The described example electronic device (eg, device 100) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user interface devices, such as a physical keyboard, mouse, and / or joystick.

[0032] Figure 1is a high-level diagram of an electronic device 100 according to one embodiment. The device 100 may include one or more physical buttons, such as a "home" button or a menu button 104. The menu button 104 is used, for example, to navigate to any application in a set of applications executing on the device 100. In some embodiments, the menu button 104 includes a fingerprint sensor that identifies a fingerprint on the menu button 104. The fingerprint sensor can be used to determine whether the finger on the menu button 104 has a fingerprint that matches a fingerprint stored for unlocking the device 100. Alternatively, in some embodiments, the menu button 104 is implemented as a soft key in a graphical user interface (GUI) displayed on a touch screen.

[0033] In some embodiments, the device 100 includes a touch screen 150, a menu button 104, a push button 106 for turning the device on / off and for locking the device, a volume adjustment button 108, a subscriber identity module (SIM) card slot 110, a headset jack 112, and a docking / charging external port 124. The push button 106 can be used to turn the device on and off by pressing the button and keeping the button pressed for a predefined time interval; lock the device by pressing the button and releasing the button before the predefined time interval has passed; and / or unlock the device or initiate an unlocking process. In an alternative embodiment, the device 100 also accepts verbal input for activating or deactivating certain functions through a microphone 113. The device 100 includes various components, including but not limited to a memory (which may include one or more computer-readable storage media), a memory controller, one or more central processing units (CPUs), a peripheral device interface, an RF circuit, an audio circuit, a speaker 111, a microphone 113, an input / output (I / O) subsystem, and other input or control devices. Device 100 may include one or more image sensors 164, one or more proximity sensors 166, and one or more accelerometers 168. Device 100 may include more than one type of image sensor 164. Each type may include more than one image sensor 164. For example, one type of image sensor 164 may be a camera, and another type of image sensor 164 may be an infrared sensor used for facial recognition performed by one or more machine learning models stored in device 100. Device 100 may include Figure 1 Components not shown in the figure, such as an ambient light sensor, a dot projector, and a flood illuminator for supporting facial recognition.

[0034] Device 100 is only one example of an electronic device, and device 100 may have more or fewer components than listed above, some of which may be combined into one component or have a different configuration or arrangement. The various components of device 100 listed above are embodied in hardware, software, firmware, or a combination thereof, including one or more signal processing and / or application specific integrated circuits (ASICs).

[0035] Figure 2 1 is a block diagram illustrating components in device 100 according to one embodiment. Device 100 may perform various operations, including implementing one or more machine learning models. For this and other purposes, device 100 may include image sensor 202, system on chip (SOC) component 204, system memory 230, permanent storage (e.g., flash memory) 228, motion sensor 234, and display 216, among other components. Figure 2 The illustrated components are merely illustrative. For example, the device 100 may include Figure 2 Other components not illustrated in the embodiment (such as a speaker or microphone). In addition, some components (such as motion sensor 234) may be omitted from device 100.

[0036] The image sensor 202 is a component for capturing image data and may be implemented as, for example, a complementary metal oxide semiconductor (CMOS) active pixel sensor, a camera, a camcorder, or other device. The image sensor 202 generates raw image data, which is sent to the SOC component 204 for further processing. In some embodiments, the image data processed by the SOC component 204 is displayed on the display 216, stored in the system memory 230, the permanent storage device 228, or sent to a remote computing device via a network connection. The raw image data generated by the image sensor 202 may be a Bayer color kernel array (CFA) pattern.

[0037] The motion sensor 234 is a component or a group of components for sensing the motion of the device 100. The motion sensor 234 may generate a sensor signal indicating the orientation and / or acceleration of the device 100. The sensor signal is sent to the SOC component 204 for various operations, such as turning on the device 100 or rotating the image displayed on the display 216.

[0038] The display 216 is a component for displaying images generated by the SOC component 204. The display 216 may include, for example, a liquid crystal display (LCD) device or an organic light emitting diode (OLED) device. Based on data received from the SOC component 204, the display 216 may display various images, such as menus, selected operating parameters, images captured by the image sensor 202 and processed by the SOC component 204, and / or other information received from the user interface of the device 100 (not shown).

[0039] The system memory 230 is a component for storing instructions executed by the SOC component 204 and for storing data processed by the SOC component 204. The system memory 230 may be embodied as any type of memory, including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM), or a combination thereof.

[0040] Permanent storage 228 is a component for storing data in a non-volatile manner. Even if power is not available, permanent storage 228 retains data. Permanent storage 228 may be embodied as a read-only memory (ROM), flash memory, or other non-volatile random access memory device. Permanent storage 228 stores the operating system and various software applications of device 100. Permanent storage 228 may also store one or more machine learning models, such as regression models, random forest models, support vector machines (SVMs) such as kernel SVMs, and artificial neural networks (ANNs) such as convolutional networks (CNNs), recurrent networks (RNNs), autoencoders, and long short-term memory (LSTMs). Machine learning models may be independent models that work with various software applications or sensors of neural processor circuit 218 and device 100. Machine learning models may also be part of software applications. Machine learning models may perform various tasks, such as facial recognition, image classification, object, concept and information classification, speech recognition, machine translation, sound recognition, voice command recognition, text recognition, text and context analysis, other natural language processing, prediction and suggestions.

[0041] The various machine learning models stored in the device 100 may be fully trained, untrained, or partially trained to allow the device 100 to enhance or continue to train the machine learning model while the device 100 is in use. The operation of the machine learning model includes various calculations in training the model and determining runtime results using the model. For example, in one case, the device 100 captures a facial image of the user and uses the image to continue to improve the machine learning model used to lock or unlock the device 100.

[0042] SOC component 204 is embodied as one or more integrated circuit (IC) chips and performs various data processing processes. SOC component 204 may include, among other subcomponents, an image signal processor (ISP) 206, a central processing unit (CPU) 208, a network interface 210, a sensor interface 212, a display controller 214, a neural processor circuit 218, a graphics processor (GPU) 220, a memory controller 222, a video encoder 224, a storage controller 226, and a bus 232 connecting these subcomponents. SOC component 204 may include, among other subcomponents, an image signal processor (ISP) 206, a central processing unit (CPU) 208, a network interface 210, a sensor interface 212, a display controller 214, a neural processor circuit 218, a graphics processor (GPU) 220, a memory controller 222, a video encoder 224 Figure 2 More or fewer subcomponents than those shown.

[0043] ISP 206 is a circuit that performs various stages of the image processing pipeline. In some embodiments, ISP 206 may receive raw image data from image sensor 202 and process the raw image data into a form usable by other subcomponents of SOC component 204 or components of device 100. ISP 206 may perform various image manipulation operations, such as image translation operations, horizontal and vertical scaling, color space conversion, and / or image stabilization transformations.

[0044] CPU 208 may be implemented using any suitable instruction set architecture, and may execute instructions defined in the instruction set architecture. CPU 208 may be a general purpose or embedded processor using any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, RISC, ARM, or MIPS ISAs, or any other suitable ISA. Figure 2 A single CPU is illustrated in FIG. 2 , but SOC component 204 may include multiple CPUs. In a multi-processor system, each CPU may collectively implement the same ISA, but this is not required.

[0045] GPU 220 is a graphics processing circuit for performing graphics data. For example, GPU 220 may render objects to be displayed into a frame buffer (e.g., a frame buffer including pixel data for an entire frame). GPU 220 may include one or more graphics processors that may execute graphics software to perform some or all graphics operations or hardware acceleration of certain graphics operations.

[0046] The neural processor circuit 218 is a circuit that performs various machine learning operations based on calculations including multiplication, addition, and accumulation. Such calculations can be arranged to perform various types of tensor products, such as tensor products and convolutions of input data and kernel data, for example. The neural processor circuit 218 is a configurable circuit that performs these operations in a fast and power-efficient manner while relieving the CPU 208 of resource-intensive operations associated with neural network operations. The neural processor circuit 218 can receive input data from the sensor interface 212, the ISP 206, the persistent storage device 228, the system memory 230, or other sources such as the network interface 210 or the GPU 220. The output of the neural processor circuit 218 can be provided to various components of the device 100 such as the ISP 206, the system memory 230, or the CPU 208 for various operations. The structure and operation of the neural processor circuit 218 are referred to below. Figure 3 Detailed description.

[0047] The network interface 210 is a subcomponent that supports the exchange of data between the device 100 and other devices via one or more networks (e.g., carriers or proxy devices). For example, video or other image data may be received from other devices via the network interface 210 and stored in the system memory 230 for subsequent processing (e.g., via a back-end interface to the ISP 206) and display. The network may include, but is not limited to, a local area network (LAN) (e.g., an Ethernet or corporate network) and a wide area network (WAN). The image data received via the network interface 210 may be subjected to an image processing process by the ISP 206.

[0048] The sensor interface 212 is a circuit for interfacing with the motion sensor 234. The sensor interface 212 receives sensor information from the motion sensor 234 and processes the sensor information to determine the orientation or movement of the device 100.

[0049] The display controller 214 is a circuit for sending image data to be displayed on the display 216. The display controller 214 receives image data from the ISP 206, the CPU 208, the graphic processor, or the system memory 230, and processes the image data into a format suitable for display on the display 216.

[0050] Memory controller 222 is a circuit for communicating with system memory 230. Memory controller 222 can read data from system memory 230 for processing by ISP 206, CPU 208, GPU 220, or other subcomponents of SOC component 204. Memory controller 222 can also write data to system memory 230 received from various subcomponents of SOC component 204.

[0051] The video encoder 224 is hardware, software, firmware, or a combination thereof for encoding video data into a format suitable for storage in the permanent storage 228 or for passing the data to the network interface 210 for transmission over a network to another device.

[0052] Compiler 240 may be software for performing compilation operations associated with a neural network. Compiler 240 may be a code module stored in, for example, system memory 230. When compiler 240 is executed by, for example, CPU 280, a task schedule is generated that lists task descriptors of tasks to be performed by a neural engine in neural processor circuit 218, as described below with reference to Figure 6B Detailed description. Figures 7 to 11 The details of compiler 240 and its operation are described in detail. In other embodiments, compiler 240 may be implemented as a combination of software, hardware, or firmware.

[0053] In some embodiments, one or more subcomponents of SOC component 204 or some functionality of these subcomponents may be performed by a software component executing on neural processor circuit 218, ISP 206, CPU 208, or GPU 220. Such software components may be stored in system memory 230, persistent storage 228, or another device that communicates with device 100 via network interface 210.

[0054] Example Neural Processor Circuit

[0055] The neural processor circuit 218 is a programmable circuit that performs machine learning operations on input data to the neural processor circuit 218. The machine learning operations may include different calculations for training a machine learning model and for performing inference or prediction based on the trained machine learning model.

[0056] Taking CNN as an example of a machine learning model, the training of CNN may include forward propagation and back propagation. The neural network may include an input layer, an output layer, and one or more intermediate layers, which may be referred to as hidden layers. Each layer may include one or more nodes, which may be fully or partially connected to other nodes in an adjacent layer. In forward propagation, the neural network performs calculations in the forward direction based on the output of the previous layer. The operation of the node may be defined by one or more functions. The function that defines the operation of the node may include various computational operations, such as data convolution using one or more kernels, pooling of layers, tensor multiplication, etc. The function may also include an activation function that adjusts the weight of the output of the node. Nodes in different layers may be associated with different functions. For example, CNN may include one or more convolutional layers mixed with a pooling layer and followed by one or more fully connected layers.

[0057] Each of the functions in the machine learning model (including the kernel) can be associated with different coefficients that can be adjusted during training. In addition, some nodes in the neural network can also be associated with an activation function that determines the weight of the output of the node in the forward propagation. Common activation functions may include step functions, linear functions, sigmoid functions, hyperbolic tangent functions (tanh), and rectified linear unit functions (ReLU). After a batch of training sample data passes through the neural network in the forward propagation, the results can be compared with the training labels of the training samples to calculate the loss function of the network, which represents the performance of the network. In turn, the neural network performs backpropagation by adjusting the coefficients in each function using coordinate descent such as stochastic coordinate descent (SGD) to improve the value of the loss function.

[0058] During training, device 100 may use neural processor circuit 218 to perform all or some of the operations in forward propagation and back propagation. Multiple rounds of forward propagation and back propagation may be performed by neural processor circuit 218 alone or in coordination with other processors such as CPU 208, GPU 220, and ISP 206. Training may be completed when the loss function no longer improves (e.g., the machine learning model has converged) or after a predetermined number of rounds for a particular training sample. While using device 100, device 100 may continue to collect additional training samples for the neural network.

[0059] To predict or infer, the device 100 may receive one or more input samples. The neural processor circuit 218 may take the input samples and perform forward propagation to determine one or more results. The input samples may be images, speech, text files, sensor data, or other data.

[0060] Data and functions in machine learning (e.g., input data, kernels, functions, layer outputs, gradient data) can be stored and represented by one or more tensors. Common operations related to the training and run-time of machine learning models may include tensor products, tensor transpositions, tensor element-wise operations, convolutions, application of activation functions, automatic differentiation to determine the gradients of values ​​in tensors, statistics and aggregations (e.g., mean, variance, standard deviation), tensor rank and size manipulation, etc.

[0061] Although the training and runtime of a neural network is discussed as an example, the neural processor circuit 218 may also be used for operation of other types of machine learning models, such as kernel SVM.

[0062] See also Figure 3, the example neural processor circuit 218 may include, among other components, a neural task manager 310, neural engines 314A to 314N (hereinafter collectively referred to as "neural engines 314"), a core direct memory access (DMA) 324, a data processor circuit 318, a data processor DMA 320, and a plane engine 340. The neural processor circuit 218 may include fewer components or Figure 3 Additional components not shown.

[0063] Each of the neural engines 314 performs computational operations for machine learning in parallel. Depending on the operational load, the entire set of neural engines 314 may be operating, or only a subset of the neural engines 314 may be operating while the remaining neural engines 314 are placed in a power saving mode to save power. Each of the neural engines 314 includes components for storing one or more kernels, for performing multiply-accumulate operations, and for post-processing to generate output data 328, as described below with reference to Figure 4A Detailed description. The neural engine 314 can be specialized to perform computationally intensive operations, such as convolution operations and tensor product operations. Convolution operations can include different kinds of convolutions, such as cross-channel convolutions (convolutions that accumulate values ​​from different channels), communication-by-communication convolutions, and transposed convolutions. Different neural engines 314 can process different tensor inputs. Alternatively, one neural engine 314 can process different tensor inputs.

[0064] The plane engine 340 may be specialized in performing simpler computational operations, the speed of which may depend primarily on the input and output (I / O) speed of data transfer rather than the computational speed within the plane engine 340. Those computational operations may be referred to as I / O-constrained computations. In contrast, the neural engine 314 may focus on complex computations, the speed of which may depend primarily on the computational speed within each neural engine 314. For example, the plane engine 340 is efficient for performing operations within a single channel, while the neural engine 314 is efficient for performing operations across multiple channels that may involve heavy accumulation of data. It is not possible to use the neural engine 314 to calculate I / O-constrained computations efficiently in terms of both speed and power consumption. In one embodiment, the input data may be a tensor with a rank greater than three (e.g., having three or more dimensions). A set of dimensions (two or more) in the tensor may be referred to as a plane, while another dimension may be referred to as a channel. The neural engine 314 may convolve the data of the plane in the tensor using a kernel, and accumulate the results of the convolution of different planes across different channels. On the other hand, the plane engine 340 may be specialized for operations within a plane.

[0065] The circuitry of the plane engine 340 can be programmed to operate in one of a variety of modes, including pooling mode, element-by-element mode, and reduction mode. In pooling mode, the plane engine 340 reduces the spatial size of the input data. In element-by-element mode, the plane engine 340 generates an output derived from an element-by-element operation of one or more inputs. In reduction mode, the plane engine 340 reduces the rank of a tensor. For example, a rank 5 tensor can be reduced to a rank 2 tensor, or a rank 3 tensor can be reduced to a rank 0 tensor (e.g., a scalar). In some embodiments, the plane engine 340 is omitted from the neural processor circuit 218.

[0066] The neural task manager 310 manages the overall operation of the neural processor circuit 218. The neural task manager 310 may receive a task list from a compiler executed by the CPU 208, store the tasks in its task queue, select the task to be executed, and send task commands to other components of the neural processor circuit 218 for execution of the selected task. Data may be associated with a task command indicating the type of operation to be performed on the data. The data of the neural processor circuit 218 includes input data transmitted from another source such as the system memory 230 and data generated by the neural processor circuit 218 in a previous operation cycle. Each data set may be associated with a task command that specifies the type of operation to be performed on the data. The neural task manager 310 may also perform switching of tasks when an event is detected, such as receiving an instruction from the CPU 208. In one or more embodiments, the neural task manager 310 sends rasterizer information to components of the neural processor circuit 218 to enable each of these components to track, retrieve, or process appropriate portions of the input data and kernel data. For example, the neural task manager 310 may include registers that store information about the size and rank of a data set for processing by the neural processor circuit 218. Although in Figure 3 The neural task manager 310 is illustrated as being part of the neural processor circuit 218 , but the neural task manager 310 may be a component external to the neural processor circuit 218 .

[0067] The kernel DMA 324 is a read circuit that obtains kernel data from a source (e.g., system memory 230) and sends the kernel data 326A-326N to each neural engine in the neural engine 314. The kernel data represents information from which kernel elements can be extracted. In one embodiment, the kernel data can be a compressed format that is decompressed at each neural engine in the neural engine 314. Although in some cases the kernel data provided to each neural engine in the neural engine 314 can be the same, in most cases the kernel data provided to each neural engine in the neural engine 314 is different. In one embodiment, the direct memory access nature of the kernel DMA 324 can allow the kernel DMA 324 to obtain and write data directly from the source without the involvement of the CPU 208.

[0068] The data processor circuit 318 manages data traffic and task performance of the neural processor circuit 218. The data processor circuit 318 may include data control circuits 332 and buffer memory 334. The buffer memory 334 is a temporary storage device for storing data associated with the operation of the neural processor circuit 218 and the plane engine 340, such as input data (e.g., data from a machine learning model) transmitted from the system memory 230 and other data generated within the neural processor circuit 218 or the plane engine 340. The data stored in the data processor circuit 318 may include different subsets that are sent to various downstream components, such as the neural engine 314 and the plane engine 340.

[0069] In one embodiment, the buffer memory 334 is implemented as a non-transitory memory accessible to the neural engine 314 and the plane engine 340. The buffer memory 334 may be a direct memory access buffer that stores data of the machine learning model of the device 100 without the involvement of the CPU 208. The buffer memory 334 may store input data 322A to 322N for feeding to the corresponding neural engine 314A to 314N or the plane engine 340, and output data 328A to 328N from each of the neural engines 314A to 314N or the plane engine 340 for feeding back into one or more neural engines 314 or the plane engine 340, or sending to a target circuit (e.g., the system memory 230). The buffer memory 334 may also store input data 342 and output data 344 of the plane engine 340, and allow data exchange between the neural engine 314 and the plane engine 340. For example, one or more output data 328A to 328N of the neural engine 314 is used as input data 342 to the plane engine 340. Likewise, the output data 344 of the plane engine 340 may be used as input data 322A to 322N for the neural engine 314. The input to the neural engine 314 or the plane engine 340 may be any data stored in the buffer memory 334. For example, in each operation cycle, the source data set from which one of the engines obtains as input may be different. The input to the engine may be the output of the same engine in the previous operation cycle, the output of a different engine, or any other suitable source data set stored in the buffer memory 334. In addition, the data sets in the buffer memory 334 may be divided and sent to different engines for different operations in the next operation cycle. Two data sets in the buffer memory 334 may also be joined for the next operation.

[0070] The buffer memory 334 may include a plurality of tensor buffers for storing portions of the input data 322A to 322N and portions of the output data 328A to 328N for access by one or more neural engines 314 to perform streaming convolution operations. Figure 5 , Fig. 6A and Figure 6B Details regarding the structure and operation of a buffer memory 334 for supporting streaming convolution operations at one or more neural engines 314 are described.

[0071] The data control circuit 332 of the data processor circuit 318 may control the data exchange between the neural engine 314 and the plane engine 340. The operation of the data processor circuit 318 and other components of the neural processor circuit 218 are coordinated so that input data and intermediate data stored in the data processor circuit 318 can be reused across multiple operations at the neural engine 314 and the plane engine 340, thereby reducing data transfers to and from the system memory 230. The data control circuit 332 may perform one or more of the following operations: (i) monitor the size and rank of data being processed by the neural engine 314 and the plane engine 340 (e.g., the data may be one or more tensors), (ii) determine which data subsets are transmitted to the neural engine 314 or the plane engine 340 based on task commands associated with different data subsets, (iii) determine the manner in which data is transmitted to the neural engine 314 and the plane engine 340 (e.g., the data processor circuit 318 may operate in a broadcast mode, in which the same data is fed to multiple input channels of the neural engine 314 so that multiple or all neural engines 314 receive the same data, or may operate in a unicast mode, in which different neural engines 314 receive different data), and (iv) transmit configuration commands to the plane engine 340 to instruct the plane engine 340 to program itself for operation in one of a plurality of operating modes. Figure 5 , Fig. 6A and Figure 6B Details regarding the operation of the data control circuit 332 are described.

[0072] The data of the neural processor circuit 218 stored in the buffer memory 334 may be part of image data, a histogram of orientation gradient (HOG) data, audio data, metadata, output data 328 of a previous operating cycle of the neural engine 314, and other processed data received from other components of the SOC component 204, etc.

[0073] The data processor DMA 320 includes a read circuit that receives a portion of input data from a source (e.g., system memory 230) for storage in a buffer memory 334 and a write circuit that forwards the data from the buffer memory 334 to a destination component (e.g., system memory 230). In one embodiment, the direct memory access nature of the data processor DMA 320 may allow the data processor DMA 320 to directly retrieve and write data from a source (e.g., system memory 230) without the involvement of the CPU 208. The buffer memory 334 may be a direct memory access buffer that stores data for a machine learning model of the device 100 without the involvement of the CPU 208.

[0074] The neural processor (NP) controller 350 is a control circuit that performs various operations to control the overall operation of the neural processor circuit 218. The NP controller 350 can interface with the CPU 208, program components of the neural processor circuit 218, and perform housekeeping operations by setting registers in the components. The NP controller 350 can also initialize components in the neural processor circuit 218 when the neural processor circuit 218 is turned on.

[0075] Example Neural Engine Architecture

[0076] Figure 4A 314 according to one embodiment. The neural engine 314 performs various operations to facilitate machine learning, such as convolution, tensor product, and other operations that may involve large amounts of computation. To this end, the neural engine 314 receives input data 322, performs a multiply-accumulate operation (e.g., a convolution operation) on the input data 322 based on the stored kernel data, performs further post-processing operations on the results of the multiply-accumulate operation, and generates output data 328. The input data 322 and / or output data 328 of the neural engine 314 may be single-channel or across multiple channels.

[0077] The neural engine 314 may include, among other components, an input buffer circuit 402, a compute core 416, a neural engine (NE) control 418, a kernel fetch circuit 432, an accumulator circuit 414, and an output circuit 424. The neural engine 314 may include a Figure 4A Fewer components or including Figure 4A Additional components not shown.

[0078] The input buffer circuit 402 is a circuit that stores a subset of the data of the neural processor circuit 218 when the subset is received from a source. The source can be the data processor circuit 318, the plane engine 340, or another suitable component. The input buffer circuit 402 sends the appropriate fragment 408 of the data for the current task or processing loop to the computing core 416 for processing. The input buffer circuit 402 may include a shifter 410 that shifts the read position of the input buffer circuit 402 to change the fragment 408 of the data sent to the computing core 416. By changing the fragment of the input data provided to the computing core 416 via the shift, the neural engine 314 can perform multiplication and accumulation for different fragments of the input data based on a smaller number of read operations. In one or more embodiments, the data of the neural processor circuit 218 includes data of difference convolution groups and / or input channels.

[0079] The kernel extraction circuit 432 is a circuit that receives the kernel data 326 from the kernel DMA 324 and extracts the kernel coefficients 422. In one embodiment, the kernel extraction circuit 432 references a lookup table (LUT) and uses a mask to reconstruct the kernel from the compressed kernel data 326 based on the LUT. The mask indicates the positions in the reconstructed kernel to be padded with zeros and the remaining positions to be padded with numbers. The kernel coefficients 422 of the reconstructed kernel are sent to the computation core 416 to fill the registers in the multiply-add (MAD) circuit of the computation core 416. In other embodiments, the kernel extraction circuit 432 receives the kernel data in an uncompressed format and determines the kernel coefficients without referencing the LUT or using a mask.

[0080] The computation core 416 is a programmable circuit that performs computational operations. To this end, the computation core 416 may include MAD circuits MAD0 to MADN and a post-processor 428. Each of the MAD circuits MAD0 to MADN may store an input value in a segment 408 of input data and store a corresponding kernel coefficient in a kernel coefficient 422. The input value and the corresponding kernel coefficient are multiplied in each of the MAD circuits to generate a processed value 412.

[0081] The accumulator circuit 414 is a memory circuit that receives and stores processed values ​​412 from the MAD circuit. The processed values ​​stored in the accumulator circuit 414 may be sent back as feedback information 419 for further multiplication and addition operations at the MAD circuit, or sent to the post-processor 428 for post-processing. The accumulator circuit 414 and the MAD circuit combine to form a multiply-accumulator (MAC) 404. In one or more embodiments, the accumulator circuit 414 may have sub-units (or batches), where each sub-unit sends data to a different component of the neural engine 314. For example, during an operation cycle, data stored in a first sub-unit of the accumulator circuit 414 is sent to the MAC 404 while data stored in a second sub-unit of the accumulator circuit 414 is sent to the post-processor 428.

[0082] Post-processor 428 is a circuit that performs further processing on value 412 received from accumulator circuit 414. Post-processor 428 may perform operations including, but not limited to, applying a linear function (e.g., a rectified linear unit (ReLU)), normalized cross-correlation (NCC), merging the results of neural operations performed on 8-bit data into 16-bit data, and local response normalization (LRN). The results of such operations are output from post-processor 428 to output circuit 424 as processed value 417. In some embodiments, processing at post-processor 428 is bypassed. For example, data in accumulator circuit 414 may be sent directly to output circuit 424 for access by other components of neural processor circuit 218.

[0083] The NE control 418 controls the operation of other components of the neural engine 314 based on the operating mode and parameters of the neural processor circuit 218. Depending on different operating modes (e.g., group convolution mode or non-group convolution mode) or parameters (e.g., the number of input channels and the number of output channels), the neural engine 314 may operate on different input data in different orders, return different values ​​from the accumulator circuit 414 to the MAD circuit, and perform different types of post-processing operations at the post-processor 428. To configure the components of the neural engine 314 to operate in a desired manner, the NE control 418 sends task commands, which may be included in the information 419, to the components of the neural engine 314. The NE control 418 may include a rasterizer 430 that tracks the current task or processing loop being processed at the neural engine 314.

[0084] The input data is typically divided into smaller pieces of data for parallel processing at multiple neural engines 314 or neural engines 314 and plane engines 340. A group of data for a convolution operation may be referred to as a convolution group, which may be divided into multiple smaller units. The hierarchy of smaller units (fragments) may be a convolution group, a slice, a block, a work unit, an output channel group, an input channel (Cin), a sub-Cin for input stride, and the like. For example, a convolution group may be divided into several slices; a slice may be divided into several blocks; a block may be divided into several work units; and so on. In the context of a neural engine 314, a work unit may be a fragment of input data, such as data processed by a plane engine 340 or data processed by a previous operation cycle of a neural engine 314, that has a size to generate an output value that fits into an accumulator circuit 414 of a neural engine 314 during a single operation cycle of a compute core 416. In one case, the size of each work unit is 256 bytes. In such embodiments, for example, a work unit may be shaped as one of a 16×16, 32×8, 64×4, 128×2, or 256×1 data set. In the context of plane engine 340, a work unit may be (i) a segment of input data, (ii) data from neural engine 314, or (iii) data from a previous operation cycle of plane engine 340, which may be processed simultaneously at plane engine 340.

[0085] The rasterizer 430 may perform operations associated with dividing the input data into smaller units (fragments) and regulate the processing of the smaller units through the MAC 404 and the accumulator circuit 414. The rasterizer 430 keeps track of the size and rank (e.g., group, work unit, input channel, output channel) of the fragments of the input / output data and instructs the components of the neural processor circuit 218 to properly process the fragments of the input data. For example, the rasterizer 430 operates the shifter 410 in the input buffer circuit 402 to forward the correct fragment 408 of the input data to the MAC 404 and sends the completed output data 328 to the data buffer memory 334. Other components of the neural processor circuit 218 (e.g., core DMA 324, buffer DMA 320, buffer memory 334, plane engine 340) may also have their corresponding rasterizers to monitor the division of the input data and the parallel computation of the various fragments of the input data in different components.

[0086] The output circuit 424 receives the processed values ​​417 from the post-processor 428 and interfaces with the data processor circuit 318 to store the processed values ​​417 in the data processor circuit 318. To this end, the output circuit 424 may emit the output data 328 in an order or format that is different from the order or format in which the processed values ​​417 are processed in the post-processor 428.

[0087] The components in the neural engine 314 may be configured during a configuration cycle by the NE control 418 and the neural task manager 310. To this end, the neural task manager 310 sends configuration information to the neural engine 314 during the configuration cycle. The configurable parameters and modes may include, but are not limited to, the mapping between input data elements and kernel elements, the number of input channels, the number of output channels, the execution of output strides, and enabling / selecting post-processing operations at the post-processor 428.

[0088] Example Streaming Convolution

[0089] Embodiments of the present disclosure relate to performing streaming convolution operations. In a streaming convolution operation, multiple layers of a CNN perform convolution operations in parallel, either physically or virtually. Each layer can stream the most recent computational result immediately to the next convolution layer. In addition, the buffer associated with each layer can store only a portion of the input data required for its convolution operation, rather than the entire input tensor (as is done in layer-by-layer inference). Therefore, the memory footprint required for the streaming convolution operation becomes equal to the sum of the tensor buffers used to store partial input tensors. On the other hand, the memory footprint required for layer-by-layer inference depends on the layer that requires the maximum total memory size to store the input and output tensors simultaneously, which may be much larger than the memory footprint required for the streaming convolution. In addition, performing convolution operations in a streaming manner can also improve the overall latency of the CNN. In the case of a streaming convolution operation, once enough input data is fed to the neural engine circuit, the first output element (e.g., pixel value) of the output tensor of the CNN can be calculated. Thus, the first pixel to first pixel latency of a CNN implemented as a streaming convolution operation at the neural engine circuitry may be significantly better than the first pixel to first pixel latency of a CNN implemented as a layer-by-layer convolution operation at the neural engine circuitry.

[0090] Figure 4B Illustrated are example convolution operations performed in a streaming manner at the neural engine 314 according to one embodiment. Figure 4B An example convolution operation is a convolution of kernel coefficients 422 of size 3×3×1 with input data 322 (e.g., input tensor) of size 10×10×1 (e.g., monochrome image data), which generates output data 328 (e.g., output tensor) of size 10×10×1. Figure 4B An example convolution operation of can be a convolution operation of one of a plurality of convolutional layers in a CNN. Segments 408 of input data can be streamed from a previous layer (e.g., in a raster scan, from left to right and then from top to bottom). Alternatively, segments 408 of input data can be received from system memory 230 or from image signal processor 206. To compute output element 434 in output data 328, neural engine 314 will only process segments 408 of input data. Thus, segments 408 of input data corresponding only to a portion of an input tensor (e.g., two rows and two input elements of input data 322) can be stored in, for example, buffer memory 334 to generate output element 434.

[0091] In the next computation cycle, new input elements of input data 322 will arrive (e.g., from buffer memory 334) as generated from the previous layer, and thus, neural engine 314 will compute the next output element of output tensor 328. However, the size of the portion of the input tensor stored in buffer memory 334 does not change, and older input elements of input data 322 may be evicted from buffer memory 334 because they are no longer used for processing. Thus, for a streaming convolution operation, only a portion of the input tensor (e.g., two rows and two input elements of input data 322) may be stored in buffer memory 334, instead of buffering the entire input data 322.

[0092] Figure 5 An example streaming inference 500 performed on multiple convolutional layers according to one embodiment is illustrated. Streaming inference 500 may include multiple groups of convolution operations, each group of convolution operations performed on a corresponding layer 505(1), 505(2), ..., 505(N). Layer 505(1) may be a layer of the lowest level, and layer 505(N) may be a layer of the highest level. And layer 505(n+1) may be a layer of a higher level than layer 505(n), n=1, 2, ..., N-1. The neural engine 314 may perform a first convolution operation on a first input tensor (e.g., input data 322) of layer 505(1) to generate a first output tensor. The neural engine 314 may also perform a second convolution operation on a second input tensor of layer 505(2) at a higher level than layer 505(1) to generate a second output tensor, the second input tensor corresponding to the first output tensor. And (e.g., for N>2), the neural engine 314 may perform an Nth convolution operation on the Nth input tensor of layer 505(N) at a higher level than layer 505(N-1) to generate output data 328, the Nth input tensor corresponding to the (N-1)th output tensor.

[0093] Each output tensor of the corresponding layer 505(n) (n=1, 2, ..., N-1) is not calculated in a layer-by-layer manner, but rather a partial output tensor is calculated by layer 505(n) before starting the convolution operation of the next layer 505(n+1) using the partial output tensor generated by layer 505(n) as an input to layer 505(n+1). Partial tensors 510(1) to 510(N) may be processed (or generated) before partial tensors 515(1) to 515(N) are processed (or generated). That is, processing (or generating) partial tensors 510(2) to 510(N) may be performed before processing partial tensor 515(1). Partial tensors 510(1) to 510(N) may correspond to N layers of a first pass through streaming inference 500, and partial tensors 515(1) to 515(N) may correspond to N layers of a second pass through streaming inference 500 after the first pass.

[0094] Example Neural Task Manager for Streaming Convolutions

[0095] Fig. 6A is a block diagram of a neural task manager 310 according to one embodiment. The neural task manager 310 can store and manage a list of task descriptors for performing streaming convolution operations at one or more neural engines 314 (e.g., streaming inference 500). In some embodiments, the compiler 240 generates a list of task descriptors and stores the generated list of task descriptors in, for example, a task file. The task file can be stored in the system memory 230, the permanent storage device 228, the buffer memory 334, some other non-transitory computer-readable storage medium of the device 100, or some combination thereof. Alternatively, a hardware component of the neural processor circuit 218 (e.g., the NP controller 350, the data control circuit 332, or some other circuit) can generate the list of task descriptors. The neural task manager 310 can include a task DMA 604, a task memory 606 coupled to the task DMA 604 (e.g., via a multiplexer 612), and a task manager controller 610 coupled to the task DMA 604 (e.g., via a multiplexer 612). The neural task manager 310 can include a task DMA 604, a task memory 606 coupled to the task DMA 604 (e.g., via a multiplexer 612). Fig. 6A Fewer components than those illustrated in the example, or including Fig. 6A Additional components not shown.

[0096] The task DMA 604 may load a list of task descriptors from, for example, the system memory 230, the permanent storage device 228, the buffer memory 334, some other non-transitory computer-readable storage medium of the device 100, or some combination thereof. During each computation cycle (e.g., a clock cycle), the task DMA 604 may receive data 602 including at least one task descriptor. Each task descriptor may identify a corresponding set of convolution operations of one or more tensor layers in a CNN.

[0097] When the task DMA 604 reads the new data 602 (e.g., from the system memory 230), the header of the new data 602 may include information about whether the payload of the new data 602 includes a task descriptor. In the case where the payload of the new data 602 includes a task descriptor, the header of the new data 602 may also include an address 614 where the payload of the new data 602 (e.g., the task descriptor 616) should be stored in the task memory 606. In this case, the task DMA 604 may send the task descriptor 616 and the address 614 where the task descriptor 616 should be stored in the task memory 606 to the task memory 606. The information about the address 614 may be provided to the task memory 606 as an address 618, for example, via the multiplexer 612.

[0098] The task memory 606 may store a list of task descriptors. During a computation cycle (e.g., a clock cycle), the task memory 606 may receive one or more task descriptors 616 from the task DMA 604 and store the one or more task descriptors 616 at one or more addresses 618 in the task memory 606. The task memory 606 may also be coupled to one or more control registers of the neural engine 314 (e.g., registers of the NE control 418). The task memory 606 may receive first data 622 from the one or more control registers and, after each task is completed, update the corresponding task descriptor in the task memory 606 using the received first data 622. Additionally or alternatively, the task memory 606 may pass second data 622 to the one or more control registers, the second data having information about a specific task descriptor in the task memory 606, for configuring the neural engine 314 to perform the next task associated with the specific task descriptor. The task memory 606 may be implemented as any type of memory, including, for example, DRAM, SDRAM, DDR, RDRAM, SRAM, or a combination thereof. The size of the task memory 606 may be large enough to accommodate, for example, dozens of task descriptors. The size of each task descriptor may be, for example, about 120 bytes, and the size of the task memory 606 may be, for example, about 5K bytes or less than 10K bytes.

[0099] The task manager controller 610 may control the operation of the task DMA 604 and the task memory 606. The task manager controller 610 may also configure the neural engine 314 to execute each task represented by each task descriptor stored in the task memory 606. When unprocessed task descriptors are still stored in the task memory 606, the task manager controller 610 may control the operation of the task DMA 604 by inhibiting the task DMA 604. When the task memory 606 becomes empty, the task manager controller 610 may send a request signal 634 to the task DMA 604 to read the next data 602 from an external source (e.g., the system memory 230).

[0100] The task manager controller 610 may be responsible for starting the execution of the task and updating the corresponding task descriptor in the task memory 606 after the task is executed. The task manager controller 610 may start reading the task descriptors one by one from the task memory 606. To start executing the task, the task manager controller 610 may read an index (or task index). The task manager controller 610 may then use the index to generate a read address 628 for reading the corresponding data 622 from the corresponding task descriptor in the task memory 606 identified by the index. The data 622 read from the corresponding task descriptor may be used to update the one or more control registers (e.g., registers of the NE control 418) of the neural engine 314 to prepare the neural engine 314 for executing the task.

[0101] When executing a task, the task manager controller 610 may also update one or more parameters in the corresponding task descriptor with data 636 read from a register of the neural engine 314 (e.g., a register of the NE control 418). The data 636 received by the task manager controller 610 may also include information that the execution of the task has been completed. The task manager controller 610 may update the corresponding task descriptor in the task memory 606 with the address 630 of the partial tensor data for use by the next task represented by the next task descriptor. The task manager controller 610 may provide the updated address 630 to the corresponding task descriptor as part of the information within the address 618 provided to the task memory 606 via the multiplexer 612 by activating the selection signal 632.

[0102] This step helps to update the corresponding task descriptors in the task memory 606 to be ready for the next time the next task identifying the corresponding task descriptor will be executed for additional rounds, and thus minimizes the amount of information each task descriptor should contain.

[0103] In some embodiments, each task description also includes one or more subtask descriptors, and each task is further divided into one or more subtasks. In some embodiments, each subtask is a subset of elements in the same tensor layer. In some embodiments, each subtask is a single element of a specific tensor layer.

[0104] Figure 6B An example task memory 606 in the neural task manager 310 according to one embodiment is illustrated. The task memory 606 can store task descriptors (e.g., task descriptors 602(1), 602(2), ..., 602(N), where N is the number of convolutional layers (e.g., in Figure 5Each task descriptor 602(n) (n=1, 2, ..., N) can therefore identify a corresponding set of convolution operations of a corresponding convolution layer. The task descriptor 602(n) can include an input size identifier (ID) 604(n), an output size ID 606(n), a kernel size ID 608(n), and one or more pointers 610(n), n=1, 2, ..., N. The task descriptor 602(n) can include Figure 6B 602(n). Alternatively, some of the fields of the task descriptor 602(n) may be grouped into a single field in the task descriptor 602(n). The input size ID 604(n) may identify the size of the partial input tensor to be used for the next subset of convolution operations on the corresponding portion of the nth layer. The output size ID 606(n) may identify the size of the partial output tensor to be generated by the next subset of convolution operations. The kernel size ID 608(n) may identify the size of the kernel to be used for the next subset of convolution operations. The pointer 610(n) may include data for one or more registers in the neural engine 314 (e.g., registers in the NE control 418) for configuring the neural engine 314 to perform the next subset of convolution operations, such as information about the address of the partial input tensor in the buffer memory 334 for the next subset of convolution operations.

[0105] Example architecture of the compiler

[0106] Figure 7 2 is a block diagram of a compiler 240 that may be implemented at a processor, such as a system processor of a device, for example, a CPU 208 and / or a GPU 220 of the device 100. The compiler 240 includes a tensor separator 702, a dependency identifier 704, an initial task scheduler 706, a buffer allocator 708, a task descriptor generator 712, a metric generator 710, a task aggregator 714, and an update task scheduler 716. The tensor separator 702 spatially divides a tensor into a plurality of partitions. In some embodiments, the spatial division of the tensor includes dividing the tensor in a raster scan manner. Reference will be made to FIG. 20 for details. Figure 8 Additional details regarding spatial partitioning are discussed further.

[0107] The dependency identifier 704 identifies the dependencies of the partitions in the tensor. In some embodiments, as a result of its processing, the dependency identifier 704 generates a dependency graph representing the identified dependencies of the partitions. FIG. 9A to FIG. 9B and Fig.10 Additional details regarding identifying dependencies of partitions are discussed further.

[0108] The initial task scheduler 706 assigns each partition to a task and schedules the resulting tasks based on the dependency graph, thereby performing the neural network operation in a streaming manner. In other embodiments, the initial task scheduler 706 may assign a preset number of partitions to a single task. For example, the preset number may be determined so that the data associated with the preset number of partitions does not exceed a logical size unit of the buffer memory 334 that can be accessed simultaneously for a read or write operation.

[0109] The buffer allocator 708 allocates memory space in the buffer memory 334 to the tasks. For example, based on the timing constraints associated with the completion time, the tasks are grouped into multiple subsets. The subset of tasks with completion times within a predetermined time is allocated to the same portion of the buffer memory 334, so that after the subset of tasks is completed, the entire portion of the memory can be released. In this way, the subset of tasks occupies a portion of the buffer memory for a shortened amount of time and is flushed more quickly to make room for subsequent tasks. Fig.11 and FIG. 12A to FIG. 12C Additional details regarding buffer allocation are discussed further.

[0110] The task descriptor generator 712 generates a task descriptor for each task. During runtime, the task descriptors may be loaded into the neural task manager 310 to configure the components of the neural processor circuit 218 to perform neural network operations in a streaming manner.

[0111] When a particular task schedule is deployed and executed on the neural processor circuit 218, the metric generator 710 determines one or more metrics indicative of the hardware performance of the neural processor circuit 218. The metric may indicate the occupancy of memory space in the buffer memory 334 used to perform compilation operations by the neural processor circuit 218. Alternative or additional metrics may also be generated, such as the total completion time of the compilation operation, power consumption, and / or the cumulative operating time of the neural engine 314.

[0112] The task aggregator 714 aggregates multiple tasks into a smaller number of tasks to improve one or more metrics determined by the metric generator 710. The tasks combined by the task aggregator 714 can be associated with partitions of adjacent or continuous tensors. For example, when memory occupancy is used as a metric, aggregation can be performed to increase the memory usage of the buffer memory 334 to a predetermined amount by increasing the size of the updated tasks generated by the aggregated tasks. The aggregation process can be repeated multiple times until one or more criteria are met (e.g., the maximum memory occupancy is greater than a specific size). In some cases, the task aggregator 714 can reduce the number of partitions in each task, which is a reverse aggregation process. For example, when the memory footprint of the compilation operation exceeds a certain percentage of the space in the buffer memory 334, the number of partitions in each task can be reduced.

[0113] like Figure 7 The illustrated components of compiler 240 are merely illustrative. Compiler 240 may include additional instruction modules or firmware modules to perform additional functions or omit certain components (eg, metric generator 710, task aggregator 714, and update task scheduler 716).

[0114] Tensor example splitting and memory allocation

[0115] Figure 8 An example of spatial partitioning of tensor 800 is illustrated, according to one embodiment. Figure 8 The tensor 800 is a 10×8 matrix including 10 columns and 8 rows. In one or more embodiments, the tensor 800 can be partitioned in a raster scan manner, where each partition includes the same number of consecutive elements. Figure 8 As illustrated, the tensor 800 is partitioned into 20 partitions P0 to P19 in a raster scan manner (e.g., in a zigzag manner from left to right and from top to bottom), wherein each partition includes four consecutive elements. For example, the first partition P0 includes the first four elements in the first row of the tensor 800, the second partition P1 includes the last four elements in the first row of the tensor 800, the third partition P2 includes the last two elements in the first row of the tensor 800 and the first two elements in the second row, and so on.

[0116] The direction of the raster scan used to partition tensor 800 may be consistent with the order in which the elements of tensor 800 were generated in an operation prior to the operation at neural processor 218. For example, tensor 800 may represent image pixels captured by image sensor 202 and processed by image signal processor 206. In this case, image signal processor 206 may generate the processed pixels in a raster manner that is consistent with the order in which the elements were provided to and processed by neural processor circuit 218. In this manner, the amount of memory to buffer the elements of tensor 800 for processing at neural processor circuit 218 may be reduced.

[0117] Partitions in the same tensor layer may have dependencies. In some embodiments, each partition in the same tensor layer is processed sequentially. For example, P1 will be processed before P2, P2 will be processed before P3, and so on. Further, different divisions in different layers of the tensor also have specific dependency requirements. For example, when the next tensor layer is generated based on the convolution calculation of the elements in the current layer, this dependency requirement is based on the convolution kernel. In addition, in addition to the dependency requirements associated with elements and convolution kernels, here, the dependency requirements are also associated with partitions, each partition including multiple elements.

[0118] Fig. 9A and Fig. 9B An example of a dependency relationship between a partition in an N-th layer tensor and a partition in an (N+1)-th layer tensor according to one embodiment is illustrated. Fig. 9A Elements in the Nth layer are illustrated. Fig. 9B The elements in the (N+1)th layer are illustrated. To process the partition P6 in the (N+1)th layer (e.g. Fig. 9B As shown), each of the four elements in partition P6 is read. Assuming the convolution kernel is 3×3, each of the four elements P6 of the (N+1)th layer involves reading and processing nine elements from the Nth layer. Therefore, to process P6, a 5×3 submatrix of elements in the Nth layer (belonging to partitions P3, P4, P6, P7, P9, and P10 in the Nth layer) is read. In addition, to process elements in partition P6, elements in P5 are read first; and to process elements in partition P9, elements in partition P8 are read first. Therefore, the dependencies of partition P6 in the (N+1)th layer include partitions P3 to P10 in the Nth layer. In some embodiments, a dependency graph can be generated based on the identified dependencies between partitions of different tensor layers.

[0119] Fig.10 An example dependency graph representing dependency relationships between partitions or tasks in multiple tensor layers according to one embodiment is illustrated. Fig.10As illustrated, multiple tensor layers include an N-th layer of tensors, an (N+1)-th layer of tensors, and an (N+2)-th layer of tensors. Each of the N-th, (N+1)-th, and (N+2)-th layer of tensors includes multiple tasks. Each task corresponds to one or more partitions. For example, in the N-th layer, there are tasks 1002, 1004, 1006, 1008, 1010, 1012, 1016, 1020, 1026, 1028, 1032, and 1038, and so on. Dependency relationships are represented by lines linking different tasks. For example, there are multiple lines linking tasks 1002, 1004, 1006, 1008, 1010, 1012 in the N-th layer and task 1014 in the (N+1)-th layer. Therefore, task 1014 cannot be completed until the results from tasks 1002, 1004, 1006, 1008, 1010, 1012 are all completed.

[0120] In each layer, tasks may be executed sequentially, although tasks in different layers may be executed simultaneously in a streaming manner. For example, in the Nth layer, task 1002 needs to be executed before task 1004, and task 1004 needs to be executed before task 1006, and so on. Therefore, tasks 1002, 1004, 1006, 1008, 1010, 1012, 1016, 1020, 1026, 1028, 1032, 1038 in the Nth layer tensor are calculated sequentially. Similarly, tasks 1014, 1018, 1022, 1024, 1030, 1034, 1040, 1044 in the (N+1)th layer are also calculated sequentially. For example, after sequentially calculating tasks 1002, 1004, 1006, 1008, 1010, 1012 in the Nth layer tensor, tasks 1014, 1018, 1022, 1024, 1030, 1034 in the (N+1)th layer may then be sequentially calculated. At the same time, tasks 1016, 1020, 1026, 1028, 1032, 1038 in the Nth layer may also be sequentially calculated.

[0121] The exact order for executing tasks in the Nth layer or the (N+1)th layer may be determined by the initial task scheduler 706 or the updated task scheduler 716 of the compiler 240. For example, in some embodiments, task 1002 in the Nth layer and task 1014 in the (N+1)th layer may be scheduled to execute simultaneously; task 1004 in the Nth layer and task 1018 in the (N+1)th layer may be scheduled to execute simultaneously, and so on.

[0122] After the tasks 1014, 1018, 1022, 1024, 1030, 1034 in the (N+1)th layer are completed, the tasks 1036, 1042, 1046, 1048, 1058, 1060, 1062, 1064 in the (N+2)th layer may be executed sequentially. At the same time, the tasks 1040, 1044, 1050, 1052, 1054, 1056 in the (N+1)th layer may also be executed sequentially. Again, the exact order for executing the tasks in the Nth layer or the (N+1)th layer may be determined by the initial task scheduler 706 or the updated task scheduler 716 of the compiler 240. For example, task 1036 in the (N+2)th layer, task 1040 in the (N+1)th layer, and task 1038 in the Nth layer may be executed simultaneously; task 1042 in the (N+2)th layer and task 1044 in the (N+1)th layer may be executed simultaneously, etc. This process may be repeated as many times as needed until all tasks in each of the tensor layers are completed.

[0123] When performing different tasks according to the task schedule, the partition associated with the task is loaded into the part of the storage buffer 334. After some tasks are completed, a part of the memory buffer for storing tasks is released, so as to make room for subsequent tasks. In some embodiments, multiple tasks that are scheduled to be completed in a predetermined time frame are assigned to the same part of the buffer memory 334, to utilize the buffer memory efficiently. For example, in some embodiments, tasks are grouped into multiple subsets based on their completion time. Then, the subset of the grouping of tasks is stored in the same logical part of the buffer memory 334.

[0124] Fig.11 An example of buffer allocation between tasks in different tensor layers according to one embodiment is illustrated. Fig.11 As illustrated, T0-N, T1-N, T2-N, T3-N, T4-N, T5-N, T6-N represent tasks in the Nth tensor layer; T0-(N+1), T1-(N+1), T2-(N+1) represent tasks in the (N+1)th tensor layer; T0-(N+2) represents partitions or tasks in the (N+2)th tensor layer. Each task includes one or more partitions in a particular tensor layer, and each partition includes one or more elements in a particular tensor layer. Elements in the (N+1)th layer are calculated based on elements calculated in the Nth layer, and elements in the (N+2)th layer are calculated based on elements in the (N+1)th layer.

[0125] like Fig.11As illustrated, tasks T0-N, T1-N, T2-N all have completion times that may be the same or may be different but all fall within the time frame FT0. Therefore, tasks T0-N, T1-N, T2-N are assigned to the same first portion of the buffer memory (referred to as buffer_0), and all three tasks partially overlap in processing time. Once all tasks T0-N, T1-N T2-N are completed, the entire portion buffer_0 of the memory can be released. On the other hand, tasks T3-N, T4-N have completion times that are different but all fall within the time frame FT1. These tasks are all assigned to the same second portion of the buffer memory (referred to as buffer_1). Similarly, tasks T0-(N+1), T1-(N+1) and T2-(N+1) are assigned to the same third part of the buffer memory (called buffer_2); tasks T5-N and T6-N are assigned to the fourth same part of the buffer memory (called buffer_3), and task T0-(N+2) is assigned to the fifth same part of the buffer memory (called buffer_4).

[0126] like Fig.11 The illustrated memory allocation is only illustrative. In some cases, not only a subset of tasks assigned to the same portion of the buffer memory, but also different tasks assigned in different portions of the buffer buffer_0, buffer_1, buffer_2, buffer_3, buffer_4 may be partially executed simultaneously. In addition, some tasks assigned to the same portion of the buffer memory may not overlap in terms of execution time. For example, a smaller task may start processing after a larger task, but if the completion times of both tasks are within a predetermined time frame, the two tasks are still eligible to be assigned to the same portion of the buffer memory.

[0127] In some embodiments, only tasks from the same layer can be assigned to the same portion of the buffer memory. Alternatively, in some embodiments, tasks from different layers can also be assigned to the same portion of the buffer memory.

[0128] FIG. 12A to FIG. 12C 334 is illustrated for storing a portion of the allocation buffer memory 334 according to one embodiment. Fig.11 The memory space 1202 may represent a virtual or logical memory space that is mapped to the physical memory space of the buffer memory 334. Therefore, the memory space 1202 that appears to be continuous in the figure may not actually be continuous in the physical memory space of the buffer memory 334.

[0129] Fig. 12APortions of memory buffer_0, buffer_1, buffer_2 allocated for storing data associated with tasks are illustrated. In some embodiments, a first portion of memory buffer_0 having a boundary 1206 is first allocated for storing data for tasks T0-N, T1-N, and T2-N; thereafter, a second portion of memory buffer_1 having a boundary 1208 is allocated for storing data for tasks T3-N and T4-N; thereafter, a third portion of memory buffer_2 having a boundary 1210 is allocated for storing data for tasks T0-(N+1), T1-(N+1), and T2-(N+1). The total memory usage during this configuration is represented by patterned row 1232.

[0130] refer to Fig.11 , the subset of tasks T0-N, T1-N, T2-N stored in the first portion of memory (buffer_0) completes before the subset of tasks T5-N, T6-N in the fourth portion of memory (buffer_3) begins. Therefore, the first portion of memory, buffer_0, can be freed before the fourth portion of memory (buffer_3) is allocated. The freed portion of memory can be reallocated to store data for other tasks. Fig. 12B The release of the first portion of memory, buffer_0, is illustrated. After the release of the first portion of memory (buffer_0), the fourth portion of memory (buffer_3) with boundary 1212 stores data for tasks T5-N, T6-N. The total memory usage during this configuration is represented by patterned row 234.

[0131] Likewise, re-referencing Fig.11 , the subset of tasks T3-N and T4-N stored in the second portion of memory (buffer_1) completes before the task T0-(N+2) stored in the fifth portion of memory (buffer_4) starts. Therefore, the second portion of memory (buffer_1) can be freed before storing data in the fifth portion of memory (buffer_4). The freed portion of memory can be reallocated to store data for other tasks. Fig. 12C The second portion of memory (buffer_1) is illustrated as being released. After releasing the second portion of memory (buffer_1), a fifth portion of memory (buffer_4) having boundary 1214 is allocated for storing data for task T0-(N+2). The total memory usage during this configuration is represented by patterned row 1236.

[0132] This process can be repeated as many times as necessary. The total memory usage 1232, 1234, 1236 fluctuates as the neural network operation proceeds. The maximum memory usage 1232, 1234, 1236 can be determined as the memory occupancy, which should be kept below the maximum memory capacity of the buffer memory 334. However, if the memory occupancy is much less than the maximum memory capacity of the buffer memory 334, the task agglomerator 714 aggregates tasks to increase the memory occupancy and increase the efficiency of the neural network operation.

[0133] Initial task scheduler 706 generates the first task schedule, and this first task schedule has less memory occupation and lower maximum memory use, and wherein each task only comprises single partition.After being gathered and merged by task aggregator, each task can comprise multiple partitions.Alternatively, initial task scheduler 706 can generate the first task schedule, and wherein task comprises two or more partitions.In this case, task aggregator 714 can gather and merge tasks so that larger number of partitions are included in single task.If memory occupation is too large, then task aggregator 714 can divide single task with multiple partitions into multiple tasks, and each task has less partitions.

[0134] Example procedure for compiling streaming operations

[0135] Fig.13 2 is a flowchart illustrating a method of compiling operations associated with a neural network according to one or more embodiments. The method can be performed by a processor (e.g., CPU 208) in a device including a neural processor circuit or by a device that does not include a neural processor circuit. In the latter case, the device can compile tasks and send the generated task schedule to another device with a neural processor circuit.

[0136] The processor determines 1302 to spatially partition a first tensor and a second tensor associated with the neural network into a plurality of partitions. The second tensor is derived by performing a convolution on the first tensor by the neural processor. For example, the first tensor is an N-th layer tensor, and the second tensor is an (N+1)-th layer tensor. In some embodiments, the first tensor and the second tensor are spatially partitioned into the plurality of partitions based on a raster scan manner. Determining the spatial partitioning of the first tensor and the second tensor includes reading units of a predetermined size of the first tensor or the second tensor in a raster scan manner. Each of the partitions may include the same number of consecutive elements in the tensor. When the tensor represents an image, the elements of the tensor may be pixels, and the pixels of the image are partitioned into a plurality of partitions.

[0137] The processor determines 1304 dependencies of the tasks. Each task in the tasks corresponds to one or more partitions in the plurality of partitions. In some embodiments, the dependencies are based on the dimensions of the convolution kernel. As a result of determining the dependencies of the tasks, a dependency graph representing the dependencies of the tasks can be generated.

[0138] The processor generates 1306 a task schedule of tasks that satisfies the determined dependencies of the tasks (also referred to as a “first task schedule”), and assigns 1308 a subset of tasks (also referred to as a “first subset of tasks”) that satisfies timing constraints associated with completion times of the subset of tasks (also referred to as “first timing constraints”) to the same portion (also referred to as a “first portion”) of a buffer memory (e.g., buffer memory 334) in the neural processor circuit 218.

[0139] Fig.14 1402 is a flowchart illustrating a method of compiling operations associated with a neural network according to one or more embodiments. The processor spatially partitions 1402 a first tensor and a second tensor associated with the neural network into initial partitions, each partition having a size corresponding to the number of elements in a block that can be simultaneously read from or written to a buffer memory.

[0140] The processor then determines 1404 dependencies of tasks, each task corresponding to each partition in the plurality of partitions. In some embodiments, a task dependency graph is generated that describes the dependencies of the tasks.

[0141] The processor then generates 1406 an initial task schedule of tasks that satisfies the dependencies of the tasks. The processor then allocates 1408 a portion of the memory in the buffer memory (also referred to as the "first portion") to the subset of tasks that meet the time constraint (also referred to as the "first time constraint") for storage. The processor may also allocate a second portion of the memory in the buffer memory to the subset of tasks that meet the second time constraint for storage. Once the first subset or the second subset of tasks is completed, the first portion or the second portion of the memory is released.

[0142] The processor may identify 1410 a memory footprint of a buffer memory used to execute the initial task schedule. It is then determined 1412 whether the initial task schedule meets the memory footprint criteria, and the initial task schedule is then determined as the final task schedule. If not, the process continues by aggregating 1414 the tasks into fewer updated tasks. Thereafter, the processor determines 1416 dependencies of the updated tasks and generates 1418 an updated task schedule 1418 for the updated tasks. After aggregating the tasks, the memory footprint of the updated task schedule will tend to be greater than the memory footprint of the initial task schedule.

[0143] Thereafter, the process returns to allocating 1408 memory to the updated tasks as described above, and then identifying 1410 the memory footprint of the updated task schedule. If the updated task schedule meets the memory footprint criteria, the updated task schedule is determined to be the final task schedule, and the process terminates. If not, the merging 1414 of tasks by identifying 1410 memory footprints is repeated until the memory footprint criteria is met.

[0144] As referenced above Figure 13 to Figure 14 The embodiments of the described process are only illustrative. In addition, the order of the process can be modified or omitted. For example, the process of allocating 1408 memory and identifying 1410 can be performed simultaneously. In addition, the process of determining 1412 whether the memory occupancy standard is met by generating 1418 updated task schedules can be omitted.

[0145] While specific embodiments and applications have been illustrated and described, it should be understood that the invention is not limited to the precise construction and components disclosed herein, and that various modifications, changes and variations that will be apparent to those skilled in the art may be made to the arrangement, operation and details of the methods and apparatus disclosed herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for compiling a neural network operation associated with a neural network, the method comprising: determining a spatial partitioning of a first tensor and a second tensor associated with a neural network, the spatial partitioning dividing the first tensor and the second tensor into a plurality of partitions, the second tensor being derived by performing a convolution on the first tensor by a neural processor; determining dependencies of tasks, each of the tasks corresponding to one or more partitions of the plurality of partitions; Generating a first task schedule of the task that satisfies the dependency of the task; as well as A first subset of the tasks having completion times at the neural processor that satisfy a first timing constraint are assigned to a same first portion of memory in the neural processor for storage.

2. The method of claim 1 , wherein generating the first task schedule for the tasks further comprises assigning the second subset of the tasks that satisfy a second timing constraint associated with a completion time of the second subset of the tasks at the neural processor to the same second portion of the memory in the neural processor for storage, the first timing constraint requiring the first subset of the tasks to have a completion time within a first time frame, and the second timing constraint requiring the second subset of the tasks to have a completion time within a second time frame.

3. The method of claim 2, wherein the tasks are executed in the neural processor in a streaming manner such that execution of at least one of the tasks corresponding to a first partition in the first tensor and execution of at least one of the tasks corresponding to a second partition in the second tensor partially overlap with each other.

4. The method according to claim 2, further comprising: releasing the first portion of the memory after the first time frame has ended when the first subset of the tasks is completed, and The second portion of the memory is released after the second time frame ends when the second subset of the tasks is completed.

5. The method according to claim 2, further comprising: The number of partitions in each of the tasks is adjusted according to a hardware configuration of the neural processor. The method of claim 5 , wherein the hardware configuration is associated with a size of a memory of the neural processor.

7. The method of claim 5, wherein adjusting the number of partitions in each of the tasks according to the hardware configuration of the neural processor comprises: merging two or more of the tasks to generate an updated task; determining dependencies of the updated tasks; as well as A second task schedule of the updated task is generated that satisfies the dependency of the updated task.

8. The method according to claim 7, further comprising: determining a first value indicative of a metric of hardware performance when implementing the first task schedule; determining a second value of the metric indicative of hardware performance when implementing the second task schedule; comparing the first value and the second value to determine whether the first task schedule or the second task schedule produces higher hardware performance; as well as One of the first task schedule or the second task schedule that produces the higher hardware performance is selected for operating the neural processor.

9. The method of claim 8, wherein the metric indicates occupancy of the memory for execution of a portion of the task by the neural processor.

10. The method of claim 1, wherein determining to spatially partition the first tensor and the second tensor into the plurality of partitions comprises: The neural processor is configured to read cells of a predetermined size of the first tensor or the second tensor in a raster scan manner, each of the partitions comprising a same number of consecutive elements. 11 . The method of claim 1 , wherein determining the dependencies of the tasks comprises generating a dependency graph representing the dependencies of the tasks corresponding to the plurality of partitions.

12. A non-transitory storage medium storing instructions thereon which, when executed by a processor, cause the processor to: determining a spatial partitioning of a first tensor and a second tensor associated with a neural network, the spatial partitioning dividing the first tensor and the second tensor into a plurality of partitions, the second tensor being derived by performing a convolution on the first tensor by a neural processor circuit; determining dependencies of tasks, each of the tasks corresponding to one or more partitions of the plurality of partitions; Generating a first task schedule of the task that satisfies the dependency of the task; as well as A first subset of the tasks having completion times at the neuro-processor circuit that satisfy a first timing constraint are assigned to a same first portion of memory in the neuro-processor circuit for storage.

13. A non-transitory storage medium according to claim 12, wherein the instructions for generating the first task schedule for the tasks include instructions for assigning the second subset of the tasks that satisfy a second timing constraint associated with the completion time of the second subset of the tasks at the neural processor circuit to the same second portion of the memory in the neural processor circuit for storage, the first timing constraint requiring the first subset of the tasks to have a completion time within a first time frame, and the second timing constraint requiring the second subset of the tasks to have a completion time within a second time frame.

14. The non-transitory storage medium of claim 13, wherein the tasks are executed in the neural processor circuit in a streaming manner such that execution of at least one of the tasks corresponding to a first partition in the first tensor and execution of at least one of the tasks corresponding to a second partition in the second tensor partially overlap with each other.

15. The non-transitory storage medium of claim 13, wherein the instructions further cause the processor to: releasing the first portion of the memory after the first time frame has ended when the first subset of the tasks is completed, and The second portion of the memory is released after the second time frame ends when the second subset of the tasks is completed.

16. The non-transitory storage medium of claim 13, wherein the instructions further cause the processor to: The number of partitions in each of the tasks is adjusted according to a hardware configuration of the neural processor circuit, the hardware configuration being associated with a size of the memory of the neural processor circuit.

17. The non-transitory storage medium of claim 16, wherein the instructions to adjust the number of partitions cause the processor to: merging two or more of the tasks to generate an updated task; determining dependencies of the updated tasks; as well as A second task schedule of the updated task is generated that satisfies the dependency of the updated task.

18. The non-transitory storage medium of claim 17, wherein the instructions further cause the processor to: determining a first value indicative of a metric of hardware performance when implementing the first task schedule, the metric indicative of occupancy of the memory for execution of a portion of the task by the neuro-processor circuit; determining a second value of the metric indicative of hardware performance when implementing the second task schedule; comparing the first value and the second value to determine whether the first task schedule or the second task schedule produces higher hardware performance; as well as One of the first task schedule or the second task schedule that produces the higher hardware performance is selected for operating the neural processor circuit.

19. The non-transitory storage medium of claim 12, wherein the instructions to determine the spatial partitioning of the first tensor and the second tensor cause the processor to: The neural processor circuit is configured to read cells of a predetermined size of the first tensor or the second tensor in a raster scan manner, each of the partitions including a same number of consecutive elements.

20. An electronic device, comprising: System memory; a neural processor circuit coupled to the system memory, the neural processor circuit including memory; and A system processor, the system processor being configured to: determining a spatial partitioning of a first tensor and a second tensor associated with a neural network for processing in the neural processor circuit, the spatial partitioning dividing the first tensor and the second tensor into a plurality of partitions, the second tensor being derived by performing a convolution on the first tensor by the neural processor; determining dependencies of tasks, each of the tasks corresponding to one or more partitions of the plurality of partitions; Generating a first task schedule of the task that satisfies the dependency of the task; as well as A first subset of the tasks having completion times at the neuro-processor circuit that satisfy a first timing constraint are assigned to a same first portion of memory in the neuro-processor circuit for storage.

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