Generating tile visibility information by sharing GPU hardware and generating

Abstract

The present disclosure relates to methods and apparatus for sharing GPU hardware to and occur into bin visibility information for graphics processing. The apparatus may cause a processor to store, in a GMEM, first data associated with a first graphics processing pass for a first frame of graphics data and second data associated with a second graphics processing pass for a second frame of graphics data. The apparatus may also cause a geometry processor to perform the first graphics processing pass using the first data, and cause a second processor to concurrently perform the second graphics processing pass using the second data, such that the first graphics processing pass and the second graphics processing pass share the geometry processor. In some aspects, the apparatus may switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional patent application No. 17 / 934,978, entitled “APPARATUS AND METHOD FOR GENERATING TILE VISIBILITY INFORMATION CONCURRENTLY BY SHARING GPU HARDWARE” and filed on September 23, 2022, which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically utilize a graphics processing unit (GPU) or a central processing unit (GPU) to accelerate the rendering of graphics data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smart phones, embedded systems, personal computers, tablet computers, and video game consoles. The GPU executes a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The CPU can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize a GPU during execution. Devices that provide content for visual presentation on a display typically include a GPU.

[0005] Typically, the GPU of a device is configured to perform processes in a graphics processing pipeline. However, with the increasing complexity of rendered content and the physical constraints of GPU memory, an increasing need for improved computer or graphics processing has developed. Summary of the invention

[0006] A simplified summary of one or more aspects is presented below in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0007] The present disclosure relates to a method and apparatus for graphics processing. The apparatus includes a memory, at least one processor, the at least one processor including: a graphics memory (GMEM), a geometry processor coupled to the GMEM, and a second processor coupled to the GMEM, and at least one processor is coupled to the memory. The processor is configured to store first data associated with a first graphics processing pass for a first frame of graphics data in the GMEM. The processor is also configured to store second data associated with a second graphics processing pass for a second frame of graphics data in the GMEM. The processor is further configured to cause the geometry processor to perform a first graphics processing pass using the first data. The processor is further configured to cause the second processor to perform a second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. The first graphics processing pass and the second graphics processing pass share the geometry processor.

[0008] Another further aspect of the subject matter described in the present disclosure can be implemented in a method for graphics processing. The method includes storing in a GMEM first data associated with a first graphics processing pass for a first frame of graphics data. The method also includes storing in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data. The method further includes causing a geometry processor to perform a first graphics processing pass using the first data. The method further includes causing a second processor to perform a second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. The first graphics processing pass and the second graphics processing pass share a geometry processor.

[0009] Another further aspect of the subject matter described in the present disclosure can be implemented in an apparatus for graphics processing. The apparatus includes means for storing in a GMEM first data associated with a first graphics processing for a first frame of graphics data, wherein the means for causing is further configured to: store in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data, and cause a geometry processor to perform the first graphics processing pass using the first data, wherein the means for causing is further configured to: cause a second processor to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. The first graphics processing pass and the second graphics processing pass share a geometry processor.

[0010] Another further aspect of the subject matter described in the present disclosure can be in a non-transitory computer-readable medium storing computer executable code, the computer executable code including stored communication instructions executable by a processor to: store in a GMEM first data associated with a first graphics processing pass for a first frame of graphics data; store in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data; cause a geometry processor to perform the first graphics processing pass using the first data; and cause a second processor to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. The first graphics processing pass and the second graphics processing pass share a geometry processor.

[0011] To achieve the foregoing and related purposes, one or more aspects include features fully described below and specifically pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The details of one or more aspects of the subject matter described in the present disclosure are set forth in the accompanying drawings and the following description. However, the accompanying drawings illustrate only some typical aspects of the present disclosure and are therefore not to be considered as limiting its scope. Other features, aspects, and advantages will become apparent from the specification, drawings, and claims.

[0013] Figure 1A is a block diagram illustrating an example of a content generation system in accordance with one or more techniques of this disclosure.

[0014] Figure 1B is a block diagram illustrating an example of a content generation system in accordance with one or more techniques of this disclosure.

[0015] Figure 2 An example GPU in accordance with one or more techniques of this disclosure is illustrated.

[0016] Figure 3 An example architecture for performing a shared concurrent binning method in accordance with one or more techniques of this disclosure is illustrated.

[0017] Figure 4 An example diagram for graphics processing in accordance with one or more techniques of this disclosure is illustrated.

[0018] Figures 5 to 13 Example flow diagrams illustrating various example methods for graphics processing in accordance with one or more techniques of this disclosure.

[0019] The same reference numbers and designations in different drawings indicate the same elements. DETAILED DESCRIPTION

[0020] The following description relates to some specific aspects in order to describe the innovative aspects of the present disclosure. However, those skilled in the art will readily appreciate that the teachings herein can be applied in many different ways.

[0021] Aspects of the present disclosure can reduce GPU area overhead because implementing an additional geometry processor for bin visibility can add a significant percentage of GPU area. For example, aspects of the present disclosure can share GPU hardware for processing using selection of primitives associated with a first set of primitives for a first graphics processing pass and primitives associated with a second set of primitives for a second graphics processing pass. By doing so, when aspects of the present disclosure perform two graphics processing passes, the two graphics processing passes share the GPU. Thus, aspects of the present disclosure can save or conserve rendering or processing resources by using a workload selection process for sharing a GPU.

[0022] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functionality, or structures and functionality in addition to or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0023] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0024] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0025] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as processing units). One or more processors in a processing system may execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language or other names, software may be broadly understood to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc. The term "application" may refer to software. As described herein, one or more technologies may refer to applications configured to perform one or more functions, i.e., software. In such examples, applications may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, hardware may access code from a memory and execute code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be an individual component or a subcomponent of a single component.

[0026] Therefore, in one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.

[0027] In general, this disclosure describes techniques for sharing a graphics processing pipeline for concurrent generation of tile visibility information in a single device or multiple devices. This results in improved rendering of graphics content and / or reduced load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0028] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0029] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to synthesize, blend or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently blended.

[0030] In general, a GPU can be used to render a three-dimensional (3D) scene. Because such rendering of a 3D scene can be very memory bandwidth intensive, a dedicated graphics memory ("GMEM") can be used. The GMEM can be located close to the graphics processing core of the GPU so that it has very high memory bandwidth (i.e., read and write access to the GMEM is fast). The scene can be rendered to the GMEM by the graphics processing core of the GPU, and the scene can be parsed from the GMEM to a memory (e.g., a frame buffer) so that the scene can then be displayed at a display device. The rendering of an entire frame (e.g., in this manner) can be referred to as immediate mode rendering. However, the size of the GMEM is limited due to physical memory constraints, so that the GMEM may not have enough memory capacity to contain the entire three-dimensional scene (e.g., an entire frame).

[0031] In some examples, the GPU or other processing device may be configured to divide the 3D scene into tiles so that each tile that makes up the scene can fit into GMEM. This is called tile-based rendering or "binning". As an example, if GMEM is capable of storing 512kB of data, the scene can be divided into tiles so that the pixel data contained in each tile is less than or equal to 512kB. In this way, the GPU or a second processor (e.g., a pixel processor in the GPU) can render the scene by dividing the scene into tiles that can be rendered into GMEM and rendering each tile of the scene into GMEM individually, storing the rendered tiles from GMEM into a frame buffer, and repeating the rendering and storage for each tile of the scene. Therefore, the GPU or second processor can use multiple rendering passes (also called bin rendering passes) to render the scene tile by tile to render each tile of the scene.

[0032] In an exemplary implementation, tile-based rendering may be performed in several steps. For example, a GPU or other processor implementing a tile-based architecture (e.g., a geometry processor in a GPU) may initially process or pre-process the entire scene during a binning pass (also referred to as a bin visibility pass) to define several bins or "tiles." The binning pass may be followed by a series of bin rendering passes during which each of the defined tiles is rendered. In some examples, each rendering pass is completed in three stages: (1) clear / unresolve, (2) render, and (3) resolve. During the clear / unresolve stage, the GPU may initialize GMEM for the new tile and store values ​​that have been read from external memory into GMEM. During rendering, the GPU or other processor (e.g., a geometry processor in a GPU dedicated to bin rendering passes) may recreate polygons associated with the current tile. The GPU or a second processor (e.g., a pixel processor) may also generate pixel values ​​and complete the current tile so that it can be displayed on a display. The parsing step may involve the GPU copying the contents of on-chip memory (GMEM) to system memory external to the GPU, such as a buffer used by a display when displaying the completed scene.

[0033] During a binning pass, a GPU or a geometry processor (e.g., a second geometry processor in a GPU dedicated to a bin visibility pass) may generate polygons (e.g., triangles) that make up a scene and classify the polygons into a plurality of bins, which may be considered tiles of a final scene presented on a display. For example, each bin represents a portion of a final scene (e.g., a predefined portion of a frame of video data, a computer-generated graphics image, a static image, etc.). Each of the tiles that make up the scene may be associated with a bin in a memory (GMEM) that stores primitives included in each respective tile. Thus, a binning pass may classify the primitives that make up the scene into appropriate bins. In addition, a binning pass (bin visibility pass) may also create a visibility stream for each bin of a frame, which indicates whether any primitive in a bin will be visible in the final rendered scene. Thus, a visibility stream is a stream of bits that is configured as an input for a rendering pass to indicate whether a primitive is visible in each tile when rendered. If the visibility stream for a bin indicates that the bin does not contain any visible primitives (i.e., all primitives in the bin will not be visible in the final rendered scene), performance may be improved if the GPU does not render the primitives in the bin by skipping execution of instructions in the indirect buffer associated with the bin.

[0034] The GPU architecture may support tile-based deferred rendering (TBDR), which will be explained in more detail below. TBDR can be performed sequentially or concurrently. In the concurrent scheme, the GPU starts a binning or bin visibility (BV) pass concurrently with the bin rendering (BR) pass of the previous frame / render target. To achieve this, separate bin visibility (or binning) pipeline hardware is added to support concurrency. In other words, dedicated geometry processing is required in the CB architecture to generate bin visibility. The BV and BR pipelines run in parallel with the BV pipeline working on subsequent frames, while the BR pipeline works on the current frame.

[0035] Concurrent binning can be performed by sharing the geometry processing pipeline for BR and BV. Instead of having two dedicated geometry processors, concurrent binning can use one geometry processor that is shared to perform BR or BV without starving the pixel processor for BR.

[0036] Figure 1A1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of this disclosure. As generally shown, according to an exemplary aspect, the content generation system 100 includes a processing unit 127 configured to render a 3D scene, a GPU 120, and a system memory 124. The processing unit 127 may execute a software application 111, an operating system (OS) 113, and a graphics driver 115. In addition, the system memory 124 may include an indirect buffer that stores a command stream for rendering primitives and secondary commands to be executed by the GPU 120. The GPU 120 may include a graphics memory (GMEM) 121, which may be "on-chip" with the GPU 120 coupled to a geometry processor 123 and a pixel processor 125. As described with respect to FIG. Figure 1B Described in more detail, the components of the content generation system 100 can be part of a device including, but not limited to, a video device, a media player, a set-top box, a wireless handset such as a mobile phone and so-called smart phones, a personal digital assistant (PDA), a desktop computer, a laptop computer, a game console, a video conferencing unit, a tablet computing device, etc.

[0037] Processing unit 127 may be a central processing unit (CPU). GPU 120 may be a processing unit configured to perform graphics-related functions (e.g., generate and output graphics data for presentation on a display) and to perform non-graphics-related functions that utilize the large amount of processing parallelism provided by GPU 120. Because GPU 120 may provide general processing capabilities in addition to graphics processing capabilities, GPU 120 may be referred to as a general-purpose GPU (GP-GPU). Examples of processing unit 127 and GPU 120 include, but are not limited to, a digital signal processor (DSP), a general-purpose microprocessor, an application-specific integrated circuit (ASIC), a field programmable logic array (PGA), or other equivalent integrated or discrete logic circuits. In some examples, GPU 120 may be a microprocessor designed for a specific purpose (e.g., providing massively parallel processing for processing graphics and for executing non-graphics-related applications). In addition, although processing unit 127 and GPU 120 are illustrated as separate components, aspects of the present invention are not limited thereto and may, for example, reside in a common integrated circuit (IC).

[0038] Software application 111 executing on processing unit 127 may include instructions for processing unit 127 to render graphics data to a display ( Figure 1AIn some examples, the graphics rendering instructions may include software instructions that may conform to a graphics application programming interface (API). To process the graphics rendering instructions, processing unit 127 may issue one or more rendering commands to GPU 120 (e.g., via graphics driver 115) to cause GPU 120 to perform some or all of the rendering of the graphics data. In some examples, the graphics data to be rendered may include a list of graphics primitives (e.g., points, lines, triangles, quadrilaterals, triangle strips, etc.).

[0039] GPU 120 may be configured to perform graphics operations to render one or more graphics primitives to a display. Thus, when one of the software applications executing on processing unit 127 requires graphics processing, processing unit 127 may provide graphics commands and graphics data to GPU 120 for rendering to a display. The graphics data may include, for example, drawing commands, state information, primitive information, texture information, etc. In some cases, GPU 120 may be constructed with a highly parallel structure that provides more efficient processing of complex graphics-related operations than processing unit 127. For example, GPU 120 may include multiple processing elements configured to operate on multiple vertices or pixels in a parallel manner.

[0040] GPU 120 may be directly coupled to GMEM 121. In other words, GPU 120 may process data locally using local storage rather than off-chip memory. This allows GPU 120 to operate in a more efficient manner by eliminating the need for GPU 120 to read and write data via, for example, a shared bus, which may experience heavy bus traffic. GMEM 121 may include one or more volatile or non-volatile memories or storage devices, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), and one or more registers.

[0041] GMEM 121 may also be directly coupled to at least a geometry processor 123 and a second processor (e.g., a pixel processor 125). In some cases, GPU 120 may utilize geometry processor 123 to process polygons and perform transformations, such as translation, scaling, rotation, field of view, and depth testing for near and far field clipping, for an image to be produced, and utilize pixel processor 125 to associate data with pixels of the image to be produced. Geometry processor 123 may be configured to perform a bin visibility pass in tile-based deferred rendering, such as applying at least geometric transformations to vertices of primitives, marking which bins or tiles of a frame contain visible primitives (e.g., polygons, such as triangles), and generating a visibility stream. Pixel processor 125 may be configured to perform a bin rendering pass in tile-based deferred rendering, such as rendering a frame at least one bin or tile at a time using the visible primitives indicated in the visibility stream. Geometry processor 123 may also be configured to perform a box rendering pass in tile-based deferred rendering, such as transforming at least primitives and performing shading calculations to be used for subsequent rendering by pixel processor 125. In some aspects, the processor performing the above functions may be a general purpose processor (e.g., a CPU).

[0042] The geometry processor 123 may be a CPU, a GPU, a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the geometry processor 123 may be integrated into the motherboard of the device 104. In some examples, the geometry processor 123 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The geometry processor 123 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the geometry processor 123 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0043] The pixel processor 125 may be a CPU, a GPU, a GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the pixel processor 125 may be integrated into the motherboard of the device 104. In some examples, the pixel processor 125 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The pixel processor 125 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, ALUs, DSPs, discrete logic pieces, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the pixel processor 125 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0044] Processing unit 127 and / or GPU 120 may store rendered image data in frame buffer 128, which may be a separate memory or may be allocated within system memory 124. A display processor may retrieve the rendered image data from frame buffer 128 and display the rendered image data on a display.

[0045] System memory 124 may be a memory in a device and may reside external to processing unit 127 and GPU 120, i.e., off-chip with respect to processing unit 127 and off-chip with respect to GPU 120. System memory 124 may store applications executed by processing unit 127 and GPU 120. In addition, system memory 124 may store data operated on by the executed applications and data generated from the applications.

[0046] System memory 124 may store program modules, instructions, or both that are executable by processing unit 127, data used by programs executed on processing unit 127, or two or more of these. For example, system memory 124 may store a window manager application used by processing unit 127 to present a graphical user interface (GUI) on a display. In addition, system memory 124 may store user applications and application surface data associated with the applications. As explained in detail below, system memory 124 may act as device memory for GPU 120 and may store data to be operated by GPU 120 and data originating from operations performed by GPU 120. For example, system memory 124 may store any combination of texture buffers, depth buffers, stencil buffers, vertex buffers, frame buffers, and the like.

[0047] Examples of system memory 124 include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or other media that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer or processor. As an example, system memory 124 can be removed from a device and moved to another device. As another example, a storage device substantially similar to system memory 124 can be inserted into the device.

[0048] Figure 1B is a more detailed block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. Note that Figure 1B The content generation system 100 shown corresponds to Figure 1A In this regard, Figure 1B The content generation system 100 includes a processing unit 127, a GPU 120, and a system memory 124.

[0049] As further shown, the content generation system 100 includes a device 104, which may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a GPU 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include multiple additional and / or optional components, such as a communication interface 126, a transceiver 132, a receiver 133, and a transmitter 130, and one or more displays 131. Reference to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. In a further example, the result of the graphics processing may not be displayed on the device, for example, the display 131 may not receive any frame for presentation thereon. Instead, the frame or graphics processing result may be passed to another device. In some aspects, this may be referred to as hybrid rendering.

[0050] The GPU 120 includes a graphics memory (GMEM) 121. The GPU 120 may be configured to perform graphics processing, for example, in the graphics processing pipeline 107. The graphics processing pipeline 107 may include at least a bin visibility pass and a bin rendering pass. The GPU 120 may be configured to perform these passes in the graphics processing pipeline 107 using at least the GMEM 121, a geometry processor 123 coupled to the GMEM 121, and a second processor (e.g., a pixel processor 125) coupled to the GMEM 121. The content encoder / decoder 122 may include an internal memory 129. In some examples, the device 104 may include a display processor (such as a processing unit 127) to perform one or more display processing techniques on one or more frames generated by the GPU 120 before being presented by one or more displays 131, as described above. The processing unit 127 may be configured to perform display processing. The one or more displays 131 may be configured to display or otherwise present frames processed by the processing unit 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0051] Memory external to GPU 120 and content encoder / decoder 122, such as system memory 124 as described above, may be accessible to GPU 120 and content encoder / decoder 122. For example, GPU 120 and content encoder / decoder 122 may be configured to read from and / or write to external memory, such as system memory 124. GPU 120 and content encoder / decoder 122 may be communicatively coupled to system memory 124 via a bus. In some examples, GPU 120 and content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0052] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0053] According to some examples, GMEM 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be interpreted to mean that GMEM 121 or system memory 124 is non-removable or that its contents are static. For example, system memory 124 may be removed from device 104 and moved to another device. For another example, system memory 124 may not be removable from device 104.

[0054] The GPU may be configured to perform graphics processing according to the exemplary techniques as described herein. In some examples, the GPU 120 may be integrated into the motherboard of the device 104. In some examples, the GPU 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The GPU 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, ALUs, DSPs, discrete logic pieces, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are partially implemented in software, the GPU 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, and may use one or more processors to execute instructions in hardware to perform the techniques of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0055] The content encoder / decoder 122 may be any processing unit configured to perform content encoding / decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, ASICs, FPGAs, ALUs, DSPs, video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 129), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0056] In some aspects, the content generation system 100 may include an optional communication interface 126. The communication interface 126 may include a receiver 133 and a transmitter 130. The receiver 133 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 133 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending function described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 133 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and / or sending function described herein with respect to the device 104.

[0057] Reference again Figure 1AIn some aspects, the processing unit 127 may include a control component 198 configured to control a processor (including a CPU or a GPU) or a general purpose processor to perform a bin visibility pass and a bin rendering pass using a shared geometry processor. In addition, the control component 198 may be configured to store in GMEM first data associated with a first graphics processing pass for a first frame of graphics data; and also store in GMEM second data associated with a second graphics processing pass for a second frame of graphics data. In one aspect, the control component 198 is further configured to cause the geometry processor to perform a first graphics processing pass using the first data and cause a second processor (e.g., a pixel processor) to perform a second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. In another aspect, control component 198 may be configured to receive a first command for processing a first set of primitive indices using a first graphics processing pass, receive a second command for processing a second set of primitive indices using a second graphics processing pass; determine whether the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass; and store first data and second data in the GMEM based on determining that the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass and the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass. In yet another aspect, control component 198 may be configured to switch the geometry processor from being used for the second graphics processing pass to being used for the first graphics processing pass at a primitive batch boundary of at least one second batch of primitives, the switching being triggered in response to the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to a threshold. In another aspect, control component 198 may be configured to: determine whether a second graphics processing pass is being performed before a primitive batch boundary of at least one second primitive batch based on the number of primitives associated with a second set of primitive indices stored in GMEM being at least equal to a threshold; cause the geometry processor to perform a first graphics processing pass in response to the switch or based on the determination to start at the primitive batch boundary; and control the second processor to perform a second graphics processing pass using second data while the geometry processor is performing the first graphics processing pass.

[0058] In some aspects, the control component 198 may be further configured to: at a primitive batch boundary of at least one first primitive batch, switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass, the switch being triggered in response to the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to a threshold, wherein the threshold is based on an amount of time taken between: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass and storing data output from the geometry processor in the GMEM after the switch. The control component 198 may be further configured to: determine whether the first graphics processing pass is being performed before a primitive batch boundary of at least one first primitive batch based on the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to the threshold; and cause the geometry processor to perform the second graphics processing pass in response to the switch or based on determining to start at the primitive batch boundary of at least one first primitive batch. In some aspects, the control component 198 may also be configured to: determine whether the number of primitives stored in the GMEM is less than an upper threshold and greater than a lower threshold, determine whether the geometry processor is currently performing a first graphics processing pass or a second graphics processing pass; and cause the geometry processor to continue to perform the first graphics processing pass or the second graphics processing pass based on the determination. In addition, the control component 198 may be configured to control the GPU to: determine whether the first set of primitive indices does not include at least one first primitive batch for the first graphics processing pass and whether the second set of primitive indices includes at least one second primitive batch for the second graphics processing pass, and cause the geometry processor to perform the second graphics processing pass based on the determination.

[0059] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, it may be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.

[0060] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shaders, or constant data, which can adjust how the graphics context will be processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, there can be a bit indicating which workload belongs to the context register. In addition, multiple functions or programs can be run simultaneously and / or in parallel. For example, a function or program can describe an operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0061] The context state may be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To do this, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads, such as vertex or pixel workloads, in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) may use these states to determine certain functions, such as how to aggregate vertices. Since these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workload corresponding to the mode or state may follow the changed mode or state.

[0062] Figure 2 2 illustrates an exemplary GPU 200 in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, an L2 cache (UCHE) 238, and a system memory 124. Although Figure 2 The GPU 200 is shown to include processing units 220 to 238, but the GPU 200 may include multiple additional processing units. Additionally, the processing units 220 to 238 are only examples, and any combination or order of processing units may be used by the GPU according to the present disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0063] In this context, the GPU may process multiple types of data in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and drawing cell data. Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. Further, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0064] The GPU can render images in a variety of different ways. In some cases, the GPU can render images using rendering or tile rendering. In tile rendering, the image can be divided or separated into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning pass, the image can be divided into different boxes or tiles. In addition, during the binning pass, different primitives can be shaded in certain boxes, for example, using draw calls. In some aspects, during the binning pass, a visibility stream can be constructed in which visible primitives or draw calls can be identified.

[0065] In some aspects, the GPU may apply a drawing or rendering process to different boxes or tiles. For example, the GPU may render for one box and then perform all drawing for the primitives or pixels in the box. Additionally, the GPU may render for another box and perform drawing for the primitives or pixels in the box. Therefore, in some aspects, there may be a small number of boxes (e.g., four boxes) that cover all the drawing in a surface. In addition, the GPU may loop through all the drawing in a box, but perform drawing of visible drawing calls, i.e., drawing calls containing visible geometry. In some aspects, a primitive visibility stream may be generated, for example, in a binning pass, to determine visibility information for each primitive in an image or scene. For example, a primitive visibility stream may identify whether a primitive is visible. In some aspects, this information may be used to remove invisible primitives, for example, during a rendering process. In addition, at least some of the primitives identified as visible may be rendered during a rendering process.

[0066] Some types of GPUs or GPU architectures may support different types of tile rendering, such as tile-based deferred rendering (TBDR). TBDR is a process that optimizes performance and efficiency. TBDR may refer to rendering primitives or triangles one screen or box at a time. Therefore, rendering may be performed on a box-by-box basis until all primitives or triangles have been rendered. In some aspects, a GPU operating TBDR may select a specific box or region (e.g., a rectangle) of an image and render all primitives or triangles that fall into the box or region. In some aspects of TBDR rendering, the potential rendering area may be divided into smaller tiles called bins so that specific data such as depth and color data may be present in an on-chip graphics memory (GMEM). The rendering of the next box may then be performed after one box. This in turn may reduce memory bandwidth and improve performance and power.

[0067] TBDR can be performed sequentially or concurrently. In some aspects of tile rendering or TBDR, there can be multiple processing stages or passes. For example, the TBDR process can occur in two passes, a tile classification pass (also known as a bin visibility pass) and a tile rendering pass (also known as a bin rendering pass). The tile classification pass uses the geometry processing pipeline to check primitive visibility and is configured to classify primitives into various bins and generate bin-level primitive visibility information. The tile rendering pass uses the bin-level primitive visibility information generated in the binning pass and renders the screen space by fetching one bin at a time using the geometry processing pipeline and the pixel processing pipeline.

[0068] In another example, rendering can be performed in two passes, such as a visibility or bin visibility pass and a rendering or bin rendering pass. During the visibility process, the GPU can input the rendering workload, record the location of the primitives or triangles, and then determine which primitives or triangles fall into which bin or region. In certain aspects of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering process, the GPU can input the visibility stream and process one bin or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or vertices of primitives are visible or invisible, and therefore, the visible primitives or vertices of primitives can be processed. By doing so, the GPU can reduce unnecessary workload of processing or rendering invisible primitives or triangles.

[0069] In some aspects, during the visibility process, certain types of primitive geometry may be processed, for example, only positioned geometry. Additionally, primitives may be classified into different bins or regions based on the position or positioning of the primitives or triangles. In some instances, the classification of primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, the GPU may determine visibility information for each primitive in each bin or region or write it to, for example, system memory. The visibility information may be used to determine or generate a primitive visibility stream. During the rendering process, the primitives in each bin may be rendered separately. In these cases, the primitive visibility stream may be extracted from a memory for discarding primitives that are not visible to the bin.

[0070] In some aspects, TBDR in some GPU architectures can be supported in a concurrent binning (CB) scheme. In the CB scheme, the GPU starts binning or bin visibility (BV) passes concurrently with the bin rendering (BR) pass of the previous frame / render target. To achieve this, separate bin visibility (or binning) pipeline hardware is added to support concurrency. In other words, dedicated geometry processing is required in the CB architecture to generate bin visibility. The BV and BR pipelines run in parallel with the BV pipeline that works on subsequent frames, while the BR pipeline works on the current frame. In the CB scheme, optimal performance is achieved when BV passes overlap or are fully executed before BR passes. In order to ensure that the CB scheme provides a good performance per area (PPA) benefit, the area of ​​dedicated BV pipeline hardware is reduced by reducing the entire BV pipeline and by reserving area-intensive hardware (e.g., shader processors) from the bin rendering pipeline for BV pipeline operations.

[0071] However, the CB architecture has several disadvantages. First, the additional geometry processing pipeline for the BV pass adds a significant percentage of the GPU area. Second, for scaling down to low levels, the fixed area cost of the BV pipeline becomes a higher percentage of the total GPU area and can result in a PPA loss. Scaling up to high levels requires increasing the entire BV pipeline so that the BV pass can overlap with the BR pass in additional areas, which can potentially result in a PPA loss. Third, in order to reduce area overhead, dedicated BV pipeline area-intensive hardware function blocks (e.g., stream processors) from the BR pipeline are reserved for the BV pipeline and cannot be used for BR pass operations. This fixed reservation of stream processors may result in a slowdown of the BR pass and reduce overall performance, and does not provide scalable performance.

[0072] As mentioned above, in the box rendering pass, most primitives are visible primitives because the selected primitives are marked as invisible in the visibility stream. For visible primitives, most workloads show a high pixel-to-triangle ratio. Due to this ratio, the geometry processor is either stalled due to a highly loaded pixel processing pipeline or is inactive.

[0073] Figure 3 An example architecture for executing a shared concurrent binning method according to one or more techniques of the present disclosure is illustrated. Specifically, Figure 3 An example architecture 300 is shown for sharing an underutilized BR geometry processing processor for a BR processing pass and a BV processing pass. Rather than having two dedicated geometry processing pipelines, the example architecture 300 utilizes a single geometry processing pipeline (geometry processor) that is time shared to perform either a BR processing pass (shown in dashed lines) or a BV processing pass (shown in dashed lines).

[0074] like Figure 3 As shown in , the example architecture 300 includes index fetch and primitive batch generation stages 304, 306, BR / BV selection stage 308, geometry processing pipeline 310 (geometry processor), vertex storage 312, pixel processing pipeline 316 (pixel processor) and bin visibility generation stage 314 (executed by the geometry processor). The example architecture 300 also includes bin rendering commands 301 and bin visibility commands 303.

[0075] In this example architecture 300, the bin rendering commands 301 and bin visibility commands 303 are fed from separate command processing and index fetching for the BV and BR pipelines so that the BV and BR pipelines can each proceed concurrently until the index fetching (304 and 306). The bin rendering commands 301 and bin visibility commands 303 are kept separate to keep the workload ready. Each command generates a batch of primitives for one frame. For example, one bin visibility command will generate a batch of primitives and visibility streams for one frame, and one bin rendering command will generate a batch of primitives for pixel processing in one frame. Each of these batches of primitives will be associated with a unique index, and each command will have a one-to-one association. In addition, one command can have multiple batches of primitives, which can have multiple indexes. After enough batches of primitives (with associated indexes), these commands are received from the CPU and processed by the GPU.

[0076] The BR / BV selection stage 308 is responsible for selecting the BV and BR primitive indices from the corresponding index fetch paths. This approach allows the geometry processing pipeline 310 to be shared by both BR processing passes and BV processing passes while ensuring that one workload does not block the progress of the other. To ensure that one workload does not block the progress of the other, both the BV and BR outputs from the geometry processing control (GPC) pipeline are pre-computed and allocated to be drained in the on-chip memory vertex store. Therefore, the BR pipeline input to the pixel processing pipeline 316 and the BV pipeline input to the bin visibility generation stage 314 are sent from the vertex store 312.

[0077] The selection of BR primitive index or BV primitive index to be processed using the time-shared geometry processing pipeline hardware is critical to improving performance. The workload selection algorithm ensures that the pixel processing pipeline 316 is not starved.

[0078] Since the geometry processing pipeline 310 is time-shared for both BR and BV workloads at the switching boundary, the various caches in the geometry processing pipeline 310 can be invalidated. This means that the switching granularity should be large enough so that it has minimal impact on the caches and overall performance within the geometry processing pipeline 310. However, if the switching granularity is too large, starvation of BR pixel slices may result because the BV workload takes too long to reach the switching granularity point.

[0079] Therefore, the example architecture 300 uses primitive batch boundaries as the BR / BV switching granularity. GPU optimization relies on the fact that primitives are processed and connected sequentially and assembled sequentially. In order to prevent excessive overhead and starvation of box rendering or pixel processing, it should be balanced by using the primitive batch size as the switching granularity, because the primitive batch size changes depending on box rendering or box visibility. A primitive batch is a group of consecutive numbers of primitives, where the number of primitives can be different for BR and BV pipelines. Therefore, the primitive batch boundary corresponds to the boundary associated with two adjacent primitive batches. As a non-limiting example, a BR primitive may have X primitives and a BV primitive batch may have Y primitives. In the example provided above, in order to achieve a proper balance, X primitives may be twice the number of Y primitives, because BR is generally slower, so BV should be smaller to avoid starvation.

[0080] In some aspects, the BR workload also makes most primitives visible because invisible primitives are removed in the bin visibility pass. Workloads with higher pixel-to-triangle ratios show more benefit from TBDR (e.g., two-pass binning and bin rendering), and these workloads are submitted in concurrent binning mode. Due to the higher pixel-to-triangle ratio, the bin rendering pass and pixel processing pipeline 316 take much more time to process primitive batches than the geometry processing pipeline 310.

[0081] Although reference is made to different graphics processing passes in the context of allowing a bin rendering pass and a bin visibility pass to share a geometry processor, the method in the example architecture 300 should not be construed as limited to use with only bin rendering commands and bin visibility commands. Rather, the example architecture 300 can be used for any other different combination of graphics processing passes, such as immediate mode rendering passes, remote rendering passes, shading passes, etc.

[0082] Figure 4 An example diagram for graphics processing according to one or more techniques of the present disclosure is illustrated. Specifically, Figure 4 An example diagram 400 is illustrated of sharing a geometry processing pipeline using a watermarking scheme for selecting BR or BV.

[0083] like Figure 4As shown, when both BR and BV primitive indices are ready to use the geometry processor, the selection algorithm selects one of them to use the geometry processor. In some aspects, when there is at least one primitive index set 401 for the BR processing pass and at least one primitive index set 403 for the BV processing pass, the BR and BV primitive indices are considered ready for use. In diagram 400, BR is initially selected to use the geometry processing pipeline 405 (geometry processor). Due to slow progress, in the vertex storage (e.g., Figure 3 Pixel slice primitives are accumulated in vertex storage 312 (shown in ), and the selection algorithm is configured to track the number of primitives in GMEM (e.g., vertex RAM) 407.

[0084] When the number of primitives in GMEM reaches an upper threshold 413 (e.g., enough primitives are accumulated in the vertex GMEM for bin rendering), the pixel processing pipeline (pixel processor) can process those primitives from GMEM, and the geometry processing pipeline can be used for BV workload. In other words, the upper threshold 413 indicates that there are enough polygons or vertices stored in the vertex store that pixel processing should continue and switch to BV on the geometry processing pipeline. In this case, pixel slicing is not urgently needed because the BR that exists at the same time can satisfy its own work.

[0085] After reaching an upper threshold 413 of primitives in the vertex RAM, the selection algorithm uses the geometry processing pipeline for the BV workload. In some aspects, the upper threshold 413 is determined based on the memory capacity associated with the BR processing pass. While the BV workload is being processed in the geometry processing pipeline, the BR pixel processing pipeline continues to process primitives from the vertex RAM, causing the number of primitives in GMEM to decrease. As the number of BR primitives in GMEM decreases toward a lower threshold 415, bin visibility (e.g., bin sorting) occurs batch by batch.

[0086] When the BR primitives in GMEM reach a lower threshold 415, the selection algorithm stops the BV workload at the primitive batch boundary and allows the BR workload to take over the geometry processing pipeline. The lower threshold 415 indicates a point where there may be no points left in the vertex store for pixel processing (e.g., starvation) if bin visibility (e.g., bin sorting) continues. At the switching point, the number of primitives in GMEM continues to decrease due to the latency 417 involved between the polygons generated in the graphics and in the actual rendering / pixel processing pipeline 409. Therefore, more pixel processing will occur before the vertex store begins to store more polygons, and therefore the number of primitives increases after the latency 417.

[0087] To this end, lower threshold 415 is designed to accommodate latency 417. In some aspects, the latency is the GPC BR pipeline latency. After the switch occurs, draining (e.g., a reduction in the number of primitives in GMEM) may continue to occur until the primitive data provided by the geometry processor is stored in GMEM, after which draining stops and the number of primitives increases back toward upper threshold 413. In some aspects, lower threshold 415 can be based on the amount of time brought about between switching the geometry processor from being used for BV processing passes to being used for BR processing passes and storing the data output from the geometry processor into GMEM after the switch. In some aspects, lower threshold 415 is determined based on the time it takes to drain the primitives to the pixel slices, thereby allowing the BR workload to pass through the geometry processing pipeline and also be ready in vertex RAM for the pixel pipeline so that the pixel pipeline does not see any starvation.

[0088] like Figure 4 As shown, the BV processing pass can also be processed in the geometry processor in a shared manner with the BR processing pass without starving the pixel processing pipeline. This balanced approach of switching between BR and BV allows concurrent processing of bin rendering and bin visibility (or bin classification primitives) without starvation effects.

[0089] Advantages of this process include at least scalability and adaptability of BV / BR performance to workloads. Figure 3 The example architecture 300 shown in FIG. 1 naturally scales both up and down because the BV time shares the BR geometry processing pipeline. In addition, both BV and BR can potentially achieve the same geometry processing throughput and can change adaptively based on the workload time sharing of the geometry processors. Since there is no fixed reservation of hardware resources, this scheme also eliminates the performance disadvantages of existing CB schemes as well as the area benefits. The architecture also eliminates the need for the software complexity of running binning passes on BR hardware because the BV pipeline throughput is adaptively adjusted depending on the workload to ensure that the binned workload execution is fully overlapped with the BR.

[0090] Figure 5 An example flow chart illustrating an example method 500 for graphics processing according to one or more techniques of the present disclosure is shown. The method 500 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 500 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 500 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory).

[0091] At block 502, method 500 includes storing, in GMEM, first data associated with a first graphics processing pass for a first frame of graphics data. At block 504, method 500 includes storing, in GMEM, second data associated with a second graphics processing pass for a second frame of graphics data. In one aspect, the first graphics processing pass may be a bin visibility pass, and the second graphics processing pass may be a bin rendering pass. In another aspect, the first graphics processing pass may be a bin rendering pass, and the second graphics processing pass may be a bin visibility pass. In some other aspects, the first graphics processing pass may be a first bin rendering pass, and the second graphics processing pass may be a second bin rendering pass. In other aspects, the first frame is a current frame, and the second frame is a subsequent frame. In some aspects, the first graphics processing pass may be a bin rendering pass or a bin visibility pass, and the second graphics processing pass may be an immediate mode rendering pass. In other aspects, the first graphics processing pass may be an immediate mode rendering pass, and the second graphics processing pass may be a bin rendering pass or a bin visibility pass.

[0092] At block 506, method 500 includes causing a geometry processor to perform a first graphics processing pass using the first data. At block 508, method 500 includes causing a second processor to perform a second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data. In some aspects, the first graphics processing pass and the second graphics processing pass may share a geometry processor. In some aspects, the second processor corresponds to a pixel processor.

[0093] In some aspects, a first set of primitive indices in at least one first batch of primitives for a first graphics processing pass may include a first number of indices, and a second set of primitive indices in at least one second batch of primitives for a second graphics processing pass may include a second number of indices. In some aspects, the first number of indices may be different from the second number of indices.

[0094] Figure 6 An example flow chart illustrating an example method 600 for graphics processing in accordance with one or more techniques of the present disclosure is shown. The method 600 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 600 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 600 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 600, blocks 506 and 508 are described above in conjunction with Figure 5 Perform as described.

[0095] At block 602, method 600 includes receiving a first command for processing a first set of primitive indices using a first graphics processing pass. At block 604, method 600 includes receiving a second command for processing a second set of primitive indices using a second graphics processing pass.

[0096] At block 606 , method 600 includes determining whether the first set of primitive indices includes at least one first batch of primitives for a first graphics processing pass and whether the second set of primitive indices includes at least one second batch of primitives for a second graphics processing pass.

[0097] At block 608, method 600 includes storing first data and second data in the GMEM based on a determination that the first set of primitive indices includes at least one first batch of primitives for a first graphics processing pass and the second set of primitive indices includes at least one second batch of primitives for a second graphics processing pass. In some aspects, the first data may include primitives associated with the first set of primitive indices, and the second data may include primitives associated with the second set of primitive indices.

[0098] Figure 7 An example flow chart illustrating an example method 700 for graphics processing according to one or more techniques of the present disclosure is shown. The method 700 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 700 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 700 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 700, blocks 602, 604, 606, and 608 are described above in combination. Figure 6 Perform as described.

[0099] At block 710, method 700 includes switching a geometry processor from being used for the second graphics processing pass to being used for the first graphics processing pass at a primitive batch boundary of at least one second primitive batch. In some aspects, the switching may be triggered in response to a number of primitives associated with a second set of primitive indices stored in GMEM being at least equal to a threshold. In other aspects, the threshold may be based on a memory capacity associated with the second graphics processing pass.

[0100] Figure 8An example flow chart illustrating an example method 800 for graphics processing according to one or more techniques of the present disclosure is shown. The method 800 may be performed by a device, such as the control component 198 described above. In some implementations, the method 800 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 800 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 800, blocks 602, 604, 606, and 608 are described above in combination. Figure 6 is performed as described above, and block 710 is combined with Figure 7 Perform as described.

[0101] At block 812 , method 800 includes determining whether a second graphics processing pass is being performed before a primitive batch boundary of at least one second primitive batch based on the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to a threshold.

[0102] At block 814 , method 800 includes causing the geometry processor to perform a first graphics processing pass in response to the switch or based on determining to start at a primitive batch boundary.

[0103] At block 816, method 800 includes causing a second processor to perform a second graphics processing pass using the second data while the geometry processor is performing the first graphics processing pass. In some aspects, the second processor corresponds to a pixel processor.

[0104] Fig. 9 An example flow chart illustrating an example method 900 for graphics processing according to one or more techniques of the present disclosure is shown. The method 900 may be performed by a device, such as the control component 198 described above. In some implementations, the method 900 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 900 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 900, blocks 602, 604, 606, and 608 are described above in combination. Figure 6 is performed as described above, and block 506 is combined with Figure 5 Perform as described.

[0105] At block 912, method 900 includes switching a geometry processor from being used for a first graphics processing pass to being used for a second graphics processing pass at a primitive batch boundary of at least one first primitive batch. In some aspects, the switching may be triggered in response to a number of primitives associated with a first set of primitive indices stored in GMEM being less than or equal to a threshold. In other aspects, the threshold may be based on an amount of time entailed between switching the geometry processor from being used for a first graphics processing pass to being used for a second graphics processing pass and storing data output from the geometry processor in GMEM after the switching.

[0106] Fig.10 An example flow chart illustrating an example method 1000 for graphics processing in accordance with one or more techniques of the present disclosure is shown. The method 1000 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 1000 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 1000 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 1000, blocks 602, 604, 606, and 608 are described above in conjunction with Figure 6 is performed as described above, and block 506 is combined with Figure 5 Perform as described.

[0107] At block 1012, method 1000 includes switching a geometry processor from being used for a first graphics processing pass to being used for a second graphics processing pass at a primitive batch boundary of at least one first primitive batch. In some aspects, the switching may be triggered in response to a number of primitives associated with a first set of primitive indices stored in GMEM being less than or equal to a threshold. In other aspects, the threshold may be based on an amount of time entailed between switching the geometry processor from being used for a first graphics processing pass to being used for a second graphics processing pass and storing data output from the geometry processor in GMEM after the switching.

[0108] At block 1014 , method 1000 includes determining whether a first graphics processing pass is being performed before a primitive batch boundary of at least one first primitive batch based on the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to a threshold.

[0109] At block 1016 , the method 1000 includes causing the geometry processor to perform a second graphics processing pass in response to the switch or based on the determination to start at a primitive batch boundary of the at least one first primitive batch.

[0110] Fig.11An example flow chart illustrating an example method 1100 for graphics processing according to one or more techniques of the present disclosure is shown. The method 1100 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 1100 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 1100 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 1100, blocks 602, 604, 606, and 608 are described above in combination. Figure 6 Perform as described.

[0111] At block 1110, method 1100 includes determining whether the number of primitives stored in GMEM is less than an upper threshold and greater than a lower threshold. In some aspects, the upper threshold is based on a memory capacity associated with a BV processing pass. In some aspects, the lower threshold is based on an amount of time taken between switching a geometry processor from being used for a BV processing pass to being used for a BR processing pass and storing data output from the geometry processor in GMEM after the switch.

[0112] At block 1112 , method 1100 includes determining whether the geometry processor is currently performing a first graphics processing pass or a second graphics processing pass.

[0113] At block 1114 , method 1100 includes causing the geometry processor to continue performing the first graphics processing pass or the second graphics processing pass based on the determination.

[0114] Fig.12 An example flow chart illustrating an example method 1200 for graphics processing according to one or more techniques of the present disclosure is shown. The method 1200 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 1200 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 1200 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory). In such a method 1200, blocks 602, 604, 606, and 608 are described above in combination. Figure 6 Perform as described.

[0115] At block 1210 , method 1200 includes determining whether the first set of primitive indices does not include at least one first batch of primitives for a first graphics processing pass and whether the second set of primitive indices includes at least one second batch of primitives for a second graphics processing pass.

[0116] At block 1212 , method 1200 includes causing the geometry processor to perform a second graphics processing pass based on the determination.

[0117] Fig.13 An example flow chart illustrating an example method 1300 for graphics processing according to one or more techniques of the present disclosure is shown. The method 1300 may be performed by an apparatus, such as the control component 198 described above. In some implementations, the method 1300 is performed by processing logic including hardware, firmware, software, or a combination thereof. In some implementations, the method 1300 is performed by a processor executing code stored in a non-transitory computer-readable medium (e.g., a memory).

[0118] As shown in block 1301, the method 1300 includes receiving a BR command process and an index acquisition. As shown in block 1303, the method 1300 includes receiving a BV command process and an index acquisition.

[0119] As shown in block 1305, method 1300 includes determining whether BV and BR primitive indexes are ready. As described above, the BV and BR primitive indexes are ready when the first set of primitive indexes includes at least one first primitive batch for a BV processing pass and the second set of primitive indexes includes at least one second primitive batch for a BR processing pass. If neither the BV nor the BR primitive indexes are ready, as shown in block 1307, method 1300 includes determining whether the BR primitive indexes are ready. If the BV and BR primitive indexes are ready, as shown in block 1309, method 1300 includes determining whether the number of primitives in the vertex RAM is greater than an upper threshold. In some aspects, the upper threshold is based on a memory capacity associated with the BV processing pass.

[0120] If the number of primitives in the vertex RAM is greater than the upper threshold, then as shown in block 1315, method 1300 includes determining whether the BR workload is using the geometry processing pipeline. If the number of primitives in the vertex RAM is not greater than the upper threshold, then as shown in block 1311, method 1300 includes determining whether the number of primitives in the vertex RAM is less than or equal to a lower threshold. In some aspects, the lower threshold is based on the amount of time taken between switching the geometry processor from being used for BV processing passes to being used for BR processing passes and storing data output from the geometry processor in GMEM after the switch.

[0121] If the BR workload is using the geometry processing pipeline, as shown in blocks 1319 and 1325, method 1300 includes finding the next BR batch boundary and starting or continuing the BR workload. As shown in block 1305, method 1300 includes returning to determine whether both the BV and BR primitive indexes are ready. If the BR workload is not using the geometry processing pipeline, as shown in block 1325, method 1300 includes starting or continuing the BV workload. As shown in block 1305, method 1300 includes returning to determine whether both the BV and BR primitive indexes are ready.

[0122] If the number of primitives in the vertex RAM is less than or equal to the lower threshold, as shown in box 1317, method 1300 includes determining whether the BV workload is using the geometry processing pipeline. If the BV workload is not using the geometry processing pipeline, as shown in box 1323, method 1300 includes starting or continuing the BR workload. As shown in box 1305, method 1300 includes returning to determine whether both BV and BR primitive indexes are ready. If the BV workload is using the geometry processing pipeline, as shown in box 1321, method 1300 includes finding the next BV batch boundary, and as shown in box 1323, starting or continuing the BR workload. As shown in box 1305, method 1300 includes returning to determine whether both BV and BR primitive indexes are ready.

[0123] If the number of primitives in the vertex RAM is not less than or equal to the lower threshold, as shown in block 1313, method 1300 includes determining whether the BR workload is using the geometry processing pipeline. If the BR workload is not using the geometry processing pipeline, as shown in block 1325, method 1300 includes starting or continuing the BV workload. If the BR workload is using the geometry processing pipeline, as shown in block 1323, method 1300 includes starting or continuing the BR workload. As shown in block 1305, method 1300 includes returning to determining whether both the BV and BR primitive indexes are ready.

[0124] The subject matter described herein can be implemented to achieve one or more beneficial effects or advantages. For example, the techniques disclosed herein enable the GPU 120 to implement a shared concurrent binning method using a shared geometry processor between two graphics processing passes. Therefore, compared to other concurrent binning methods, the GPU does not require an additional dedicated geometry processor for executing two graphics processing passes. In addition, since the BV pipeline throughput is adaptively adjusted according to the workload to ensure that the binning workload execution is fully overlapped with the BR, this also eliminates the need for software complexity to run the binning processing pass on the BR hardware.

[0125] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a server, client, GPU, CPU, or some other processor that can perform computer or graphics processing to implement the sharing technology described herein. Compared with other computer or graphics processing techniques, this can also be implemented at a low cost. In addition, the computer or graphics processing techniques herein can improve or accelerate data processing or execution. In addition, the computer or graphics processing techniques herein can improve resource or data utilization and / or resource efficiency.

[0126] Some additional examples

[0127] Aspects described herein may also include one or more of the following implementation examples described in the following numbered clauses.

[0128] Example 1 is a device for graphics processing, the device being configured to: store first data associated with a first graphics processing pass for a first frame of graphics data in a GMEM; store second data associated with a second graphics processing pass for a second frame of graphics data in the GMEM; cause a geometry processor to perform the first graphics processing pass using the first data; and cause a second processor to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data.

[0129] Example 2 may be an apparatus according to Example 1, and is further configured to: receive a first command for processing a first set of primitive indices using the first graphics processing pass; receive a second command for processing a second set of primitive indices using the second graphics processing pass; determine whether the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass; and cause the GPU to store the first data and the second data in GMEM based on determining that the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass and the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass, and that the first data includes primitives associated with the first set of primitive indices and the second data includes primitives associated with the second set of primitive indices.

[0130] Example 3 may be an apparatus according to Example 2, and is further configured to: switch the geometry processor from being used for the second graphics processing pass to being used for the first graphics processing pass at a primitive batch boundary of the at least one second primitive batch, the switching being triggered in response to the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to a threshold, and the threshold being based on a memory capacity associated with the second graphics processing pass.

[0131] Example 4 may be an apparatus according to Example 3, and is further configured to: determine whether the second graphics processing pass is being performed before the primitive batch boundary of the at least one second primitive batch based on the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to the threshold; cause the geometry processor to perform the first graphics processing pass starting at the primitive batch boundary in response to the switch or based on the determination; and cause the pixel processor to perform the second graphics processing pass using the second data while the geometry processor is performing the first graphics processing pass.

[0132] Example 5 may be an apparatus according to Example 2, and is further configured to: switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary of the at least one first primitive batch, the switching being triggered in response to the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to a threshold, and the threshold being based on the amount of time brought about between: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass, and storing data output from the geometry processor in the GMEM after the switching.

[0133] Example 6 may be an apparatus according to Example 5, and is further configured to: determine whether the second graphics processing pass is being performed before the primitive batch boundary of the at least one second primitive batch based on the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to the threshold; and cause the geometry processor to perform the second graphics processing pass starting at the primitive batch boundary of the at least one first primitive batch in response to the switching or based on the determination.

[0134] Example 7 may be an apparatus according to Example 2, and is further configured to: determine whether the number of primitives stored in the GMEM is less than an upper threshold and greater than a lower threshold; determine whether the geometry processor is currently executing the first graphics processing pass or the second graphics processing pass; and cause the geometry processor to continue executing the first graphics processing pass or the second graphics processing pass based on the determination.

[0135] Example 8 may be an apparatus according to Example 2, and is further configured to: determine whether the first set of primitive indices does not include the at least one first primitive batch for the first graphics processing pass, and whether the second set of primitive indices includes the at least one second primitive pass for the second graphics processing pass; and cause the geometry processor to perform the second graphics processing pass based on the determination.

[0136] Example 9 may be an apparatus according to Example 2, and the first set of primitive indices in the at least one first primitive batch for the first graphics processing pass includes a first number of indices, and the second set of primitive indices in the at least one second primitive batch for the second graphics processing pass includes a second number of indices, the first number of indices being different from the second number of indices.

[0137] Example 10 may be the apparatus of Example 1, and the first graphics processing pass is a bin visibility pass and the second graphics processing pass is a bin rendering pass.

[0138] Example 11 may be the apparatus of Example 1, and the first graphics processing pass is a bin rendering pass and the second graphics processing pass is a bin visibility pass.

[0139] Example 12 may be the apparatus of Example 1, and the first graphics processing pass causes a first bin rendering pass and the second graphics processing pass is a second bin rendering pass.

[0140] Example 13 may be an apparatus according to Example 1, and the first graphics processing pass is a box visibility pass for a current frame, and the second graphics processing pass is a box visibility pass for a subsequent frame.

[0141] Example 14 may be the apparatus of Example 1, and the first graphics processing pass is a bin rendering pass or a bin visibility pass, and the second graphics processing pass is an immediate mode rendering pass.

[0142] Example 15 may be the apparatus of Example 1, and the first graphics processing pass is an immediate mode rendering pass, and the second graphics processing pass is a bin rendering pass or a bin visibility pass.

[0143] Example 16 may be an apparatus according to Example 1, and the second processor corresponds to a pixel processor.

[0144] Example 17 may be the apparatus according to Example 1, and the at least one processor further comprises a CPU and a GPU.

[0145] According to the present disclosure, the term "or" may be interpreted as "and / or" if the context does not indicate otherwise. Additionally, although phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings if the context does not specify otherwise.

[0146] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the technology described in this disclosure. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage device, magnetic disk storage device, or other magnetic storage device. As used herein, disk and disc include: compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0147] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0148] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or groups of ICs (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units may be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware.

Claims

1. A device for graphics processing, the device comprising: Memory; and At least one processor, the at least one processor comprising: Graphics Memory (GMEM), a geometry processor coupled to the GMEM, and a second processor coupled to the GMEM, wherein the at least one processor is coupled to the memory and is configured, based at least in part on information stored in the memory, to: storing in the GMEM first data associated with a first graphics processing pass for a first frame of graphics data; storing in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data; causing the geometry processor to perform the first graphics processing pass using the first data; and The second processor is caused to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data, wherein the first graphics processing pass and the second graphics processing pass share the geometry processor.

2. The apparatus of claim 1 , wherein the at least one processor is further configured to: receiving a first command for processing a first set of primitive indices using the first graphics processing pass; receiving a second command for processing a second set of primitive indices using the second graphics processing pass; determining whether the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass; as well as storing the first data and the second data in the GMEM based on determining that the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass and the second set of primitive indices includes at least one second primitive for the second graphics processing pass, The first data includes primitives associated with the first set of primitive indices, and the second data includes primitives associated with the second set of primitive indices.

3. The apparatus of claim 2, wherein the at least one processor is further configured to: switching the geometry processor from being used for the second graphics processing pass to being used for the first graphics processing pass at a primitive batch boundary of the at least one second primitive batch, the switching being triggered in response to a number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to a threshold, Wherein the threshold is based on a memory capacity associated with the second graphics processing pass.

4. The apparatus of claim 3, wherein the at least one processor is further configured to: determining whether the second graphics processing pass is being performed before the primitive batch boundary of the at least one second primitive batch based on the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to the threshold; causing the geometry processor to perform the first graphics processing pass starting at the primitive batch boundary in response to the switching or based on the determining; as well as The second processor is caused to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass.

5. The apparatus of claim 2, wherein the at least one processor is further configured to: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary of the at least one first primitive batch, the switching being triggered in response to a number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to a threshold, Where the threshold is based on the amount of time taken between: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass, and After the switching, data output from the geometry processor is stored in the GMEM.

6. The apparatus of claim 5, wherein the at least one processor is further configured to: determining whether the first graphics processing pass is being performed before the primitive batch boundary of the at least one first primitive batch based on the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to the threshold; and The geometry processor is caused to perform the second graphics processing pass starting at the primitive batch boundary of the at least one first primitive batch in response to the switching or based on the determining.

7. The apparatus of claim 2, wherein the at least one processor is further configured to: Determining whether the number of primitives stored in the GMEM is less than an upper threshold and greater than a lower threshold; determining whether the geometry processor is currently executing the first graphics processing pass or the second graphics processing pass; as well as The geometry processor is caused to continue performing the first graphics processing pass or the second graphics processing pass based on the determination.

8. The apparatus of claim 2, wherein the at least one processor is further configured to: determining whether the first set of primitive indices does not include the at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes the at least one second batch of primitives for the second graphics processing pass; and The geometry processor is caused to perform the second graphics processing pass based on the determination.

9. The apparatus of claim 2 , wherein the first set of primitive indices in the at least one first batch of primitives for the first graphics processing pass comprises a first number of indices, and the second set of primitive indices in the at least one second batch of primitives for the second graphics processing pass comprises a second number of indices, the first number of indices being different from the second number of indices.

10. The apparatus of claim 1, wherein the first graphics processing pass is a bin visibility pass and the second graphics processing pass is a bin rendering pass.

11. The apparatus of claim 1, wherein the first graphics processing pass is a bin rendering pass and the second graphics processing pass is a bin visibility pass.

12. The apparatus of claim 1, wherein the first graphics processing pass is a first bin rendering pass and the second graphics processing pass is a second bin rendering pass.

13. The apparatus of claim 1, wherein the first frame is a current frame and the second frame is a subsequent frame.

14. The apparatus of claim 1, wherein the first graphics processing pass is a bin rendering pass or a bin visibility pass, and the second graphics processing pass is an immediate mode rendering pass.

15. The apparatus of claim 1, wherein the first graphics processing pass is an immediate mode rendering pass and the second graphics processing pass is a bin rendering pass or a bin visibility pass.

16. The device of claim 1, wherein the second processor corresponds to a pixel processor.

17. The apparatus of claim 1, wherein the at least one processor further comprises a central processing unit (CPU) and a graphics processing unit (GPU).

18. A method for graphics processing, the method comprising: storing, in graphics memory (GMEM), first data associated with a first graphics processing pass for a first frame of graphics data; storing in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data; causing a geometry processor to perform the first graphics processing pass using the first data; as well as Cause a second processor to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data, wherein the first graphics processing pass and the second graphics processing pass share the geometry processor.

19. The method according to claim 18, further comprising: receiving a first command for processing a first set of primitive indices using the first graphics processing pass; receiving a second command for processing a second set of primitive indices using the second graphics processing pass; determining whether the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes at least one second batch of primitives for the second graphics processing pass; as well as storing the first data and the second data in the GMEM based on determining that the first set of primitive indices includes at least one first batch of primitives for the first graphics processing pass and the second set of primitive indices includes at least one second primitive for the second graphics processing pass, The first data includes primitives associated with the first set of primitive indices, and the second data includes primitives associated with the second set of primitive indices.

20. The method according to claim 19, further comprising: switching the geometry processor from being used for the second graphics processing pass to being used for the first graphics processing pass at a primitive batch boundary of the at least one second primitive batch, the switching being triggered in response to a number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to a threshold, Wherein the threshold is based on a memory capacity associated with the second graphics processing pass.

21. The method according to claim 20, further comprising: based on the number of primitives associated with the second set of primitive indices stored in the GMEM being at least equal to the threshold, determining whether the second graphics processing pass is being performed before the primitive batch boundary of the at least one second primitive batch; causing the geometry processor to perform the first graphics processing pass starting at the primitive batch boundary in response to the switching or based on the determining; as well as The second processor is caused to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass.

22. The method according to claim 19, further comprising: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary of the at least one first primitive batch, the switching being triggered in response to a number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to a threshold, Where the threshold is based on the amount of time taken between: switching the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass, and After the switching, data output from the geometry processor is stored in the GMEM.

23. The method according to claim 22, further comprising: Based on the number of primitives associated with the first set of primitive indices stored in the GMEM being less than or equal to the threshold, determining whether the first graphics processing pass is being performed before the primitive batch boundary of the at least one first primitive batch; as well as The geometry processor is caused to perform the second graphics processing pass starting at the primitive batch boundary of the at least one first primitive batch in response to the switching or based on the determining.

24. The method according to claim 19, further comprising: Determining whether the number of primitives stored in the GMEM is less than an upper threshold and greater than a lower threshold; determining whether the geometry processor is currently executing the first graphics processing pass or the second graphics processing pass; as well as The geometry processor is caused to continue performing the first graphics processing pass or the second graphics processing pass based on the determination.

25. The method of claim 19, further comprising: determining whether the first set of primitive indices does not include the at least one first batch of primitives for the first graphics processing pass, and whether the second set of primitive indices includes the at least one second batch of primitives for the second graphics processing pass; as well as The geometry processor is caused to perform the second graphics processing pass based on the determination.

26. The method of claim 18, wherein the first set of primitive indices in the at least one first batch of primitives for the first graphics processing pass comprises a first number of indices, and the second set of primitive indices in the at least one second batch of primitives for the second graphics processing pass comprises a second number of indices, the first number of indices being different from the second number of indices.

27. The method of claim 18, wherein the first graphics processing pass is a bin visibility pass and the second graphics processing pass is a bin rendering pass.

28. The method of claim 18, wherein the first graphics processing pass is a bin rendering pass and the second graphics processing pass is a bin visibility pass.

29. The method of claim 18, wherein the first graphics processing pass is a first bin rendering pass and the second graphics processing pass is a second bin rendering pass.

30. A non-transitory computer readable medium storing computer executable code, which, when executed by a processor, causes the processor to: storing, in graphics memory (GMEM), first data associated with a first graphics processing pass for a first frame of graphics data; storing in the GMEM second data associated with a second graphics processing pass for a second frame of graphics data; causing a geometry processor to perform the first graphics processing pass using the first data; as well as Cause a second processor to perform the second graphics processing pass using the second data concurrently with the geometry processor performing the first graphics processing pass using the first data, wherein the first graphics processing pass and the second graphics processing pass share the geometry processor.

Images