Methods for manufacturing semiconductor bodies, semiconductor bodies, and power semiconductor devices

Abstract

According to one embodiment, a method for manufacturing a semiconductor body (10) includes the steps of providing a first semiconductor layer (1) of SiC, introducing carbon into the first semiconductor layer to make at least a portion of the first semiconductor layer a C-rich region (11), and growing a second semiconductor layer (2) of SiC on the first semiconductor layer including at least a C-rich region.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor body, a semiconductor body, and a power semiconductor device. Summary of the Invention

[0002] An improved method for manufacturing semiconductor bodies is needed, such as a method that allows the manufacture of semiconductor bodies with high charge carrier mobility. Another objective is to provide an improved semiconductor body, such as a semiconductor body with high charge carrier mobility. A further objective is to provide a power semiconductor device having such a semiconductor body.

[0003] Embodiments of this disclosure relate to an improved method for manufacturing a semiconductor body, an improved semiconductor body, and an improved power semiconductor device.

[0004] According to one embodiment, a method for manufacturing a semiconductor body includes the steps of providing a first semiconductor layer of silicon carbide (SiC), introducing carbon (C) into the first semiconductor layer to make at least a portion of the first semiconductor layer a carbon-rich region (C-rich region), and growing a second semiconductor layer of SiC on the first semiconductor layer including at least one C-rich region.

[0005] This invention is particularly based on the understanding that carbon vacancies are the most important point defects in SiC (e.g., n-type 4H-SiC). Carbon vacancies generate two electrically active levels in the band gap, denoted as Z0 and Z1 respectively. 1 / 2 and EH 6 / 7 They are located at 0.65 eV and 1.6 eV below the edge of the conduction band, respectively. Specifically, Z... 1 / 2 It is considered a recombination center, which affects the lifespan of bipolar devices.

[0006] The inventors of this invention conceived of forming at least one carbon-rich region within a semiconductor layer sequence. This carbon-rich region will eventually release carbon from interstitials, which will subsequently anneal to create carbon vacancies. Because at least one carbon-rich region is formed during the formation of the semiconductor layer sequence (i.e., after the provision of the first semiconductor layer and before the growth of the second semiconductor layer), a carbon-rich region can be formed within the semiconductor layer sequence, thereby providing carbon from carbon interstitials to all regions of the semiconductor layer sequence more efficiently.

[0007] Furthermore, as described herein, forming at least one C-rich region during the formation of the semiconductor layer sequence is advantageous compared to forming a C-rich region after the semiconductor layer sequence has fully grown. This is because, in the latter case, a C-rich region must be formed within the semiconductor layer sequence via deep C ion implantation, which requires high implantation energy. This makes the process costly and also amorphizes the crystal, thus creating more electroactive energy levels. The method proposed in this paper is cheaper and gentler, i.e., it produces far fewer active energy levels compared to deep ion implantation.

[0008] The first semiconductor layer can be provided as a continuous layer, for example, without interruption. Providing the first semiconductor layer may include the step of growing (e.g., epitaxial growth) the first semiconductor layer on a substrate. The first semiconductor layer can be grown by chemical vapor deposition (CVD). For example, the substrate is made of SiC. The substrate can be doped, for example, n-type doped. The doping concentration in the substrate can be at least 10. 18 cm -3 .

[0009] The thickness of the first semiconductor layer is, for example, at least 1 µm, at least 2 µm, or at least 5 µm. Alternatively, the thickness of the first semiconductor layer may be at most 30 µm or at most 20 µm. The thickness of the substrate may be greater than the thickness of the first semiconductor layer. For example, the thickness of the substrate may be at least 100 µm or at least 300 µm and / or at most 600 µm or at most 400 µm.

[0010] Here, the thickness of a layer, region, or substrate refers to its extension in the vertical direction (i.e., in the direction perpendicular to the main extension plane of the first semiconductor layer). The SiC of the various semiconductor layers and / or substrates described herein is, for example, 4H-SiC, particularly n-type doped 4H-SiC.

[0011] The first semiconductor layer may be doped, for example, with n-type doping. For example, the average and / or maximum doping concentration in the first semiconductor layer is less than the average and / or minimum doping concentration in the substrate, for example, by at least one, two, or three orders of magnitude. For instance, the average doping concentration of the first semiconductor layer is in the range of 10-1. 14 cm -3 and 10 17 cm -3 Between. The first semiconductor layer may have already been n-type doped when it is provided. For example, the first semiconductor layer is doped during its growth process.

[0012] The introduction of carbon into the first semiconductor layer is accomplished by having at least a portion of the first semiconductor layer become at least one C-rich region. A C-rich region is understood herein as a region where the carbon concentration is greater than that in an ideal SiC crystal. For example, in a C-rich region, additional carbon atoms (C atoms) or carbon ions (C ions) are located at interstitial sites.

[0013] For example, a C-rich region is defined herein as a region in which the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 100 times, at least 1000 times, or at least 10000 times greater, respectively, than the maximum and / or average concentration in the remainder of the first semiconductor layer or in the first semiconductor layer prior to the carbon introduction step. The carbon at the interstitial sites is typically charged, therefore the interstitial sites are predominantly C ions.

[0014] Here, the minimum concentration in a region or layer refers to the lowest concentration that can be found in the aforementioned region or layer. Therefore, the maximum concentration in a region or layer refers to the highest concentration that can be found in the aforementioned region or layer. The average concentration in a region or layer is the average concentration over the entire volume of the aforementioned region or layer.

[0015] For example, only a portion, rather than the entire first semiconductor layer, becomes a C-rich region. For instance, only the region at the exposed surface (through which carbon enters the first semiconductor layer) becomes C-rich. For example, at most 10%, at most 5%, or at most 1% of the volume of the first semiconductor layer becomes at least one C-rich region.

[0016] "At least one C-rich region" means that only one continuous region of the first semiconductor layer is a C-rich region, or that multiple spatially separated regions of the first semiconductor layer are all C-rich regions. All features disclosed herein for a C-rich region are also disclosed for all other C-rich regions.

[0017] Introducing carbon into the first semiconductor layer can be done by C ion implantation, annealing in a C-rich environment (e.g., CO2, CH4, etc.), or via PIII. Once carbon is introduced, it can be diffused through thermal annealing.

[0018] The second semiconductor layer is also made of SiC and is grown on the first semiconductor layer after at least one C-rich region has been formed. That is, the second semiconductor layer is grown on the first semiconductor layer, which already includes at least one C-rich region. Specifically, the second semiconductor layer is grown such that it partially or completely covers at least one C-rich region. The main extension plane of the second semiconductor layer may be parallel to the main extension plane of the first semiconductor layer.

[0019] The second semiconductor layer can be epitaxially grown on the first semiconductor layer. For example, the second semiconductor layer can be grown directly on the first semiconductor layer, i.e., adjacent to the first semiconductor layer (especially at at least one C-rich region). The growth technique can be the same as that used for the first semiconductor layer.

[0020] After growth, the second semiconductor layer may have a thickness of at least 2 µm or at least 5 µm. Alternatively, the thickness of the second semiconductor layer may be at most 30 µm or at most 20 µm. The second semiconductor layer may be grown, for example, as a continuous layer without interruption. It may extend over the entire lateral extension of the first semiconductor layer. Here, lateral is the direction parallel to the main extension plane of the first semiconductor layer.

[0021] During the growth process, the second semiconductor layer can be doped, for example, with n-type doping. The doping concentration is, for example, the same concentration specified for the first semiconductor layer.

[0022] According to another embodiment, a carbon-rich region is formed on the exposed side of the first semiconductor layer. That is, the carbon-rich region is formed to be adjacent to the top side of the first semiconductor layer, through which carbon is introduced, and then the second semiconductor layer is grown thereon.

[0023] According to another embodiment, the C-rich region is formed such that, after the growth of the second semiconductor layer, the C-rich region lies between the remaining portion of the first semiconductor layer that has not become C-rich and the second semiconductor layer. In other words, the C-rich region is formed such that it does not extend over the entire thickness of the first semiconductor layer. For example, the depth (thickness) of the C-rich region is at most 10%, at most 5%, or at most 1% of the thickness of the first semiconductor layer.

[0024] According to another embodiment, carbon is introduced into the first semiconductor layer using plasma ion immersion implantation (PIII). PIII is a particularly mild implantation method that can produce very shallow implanted regions, i.e., implanted regions with small depths (thickness). Due to the special implanted shape generated by PIII and the presence of additional material from one or more precursors used, SIMS can detect the use of PIII in the final semiconductor bulk.

[0025] According to another embodiment, the method includes a further step of implanting a first type of dopant into a sequence of semiconductor layers, the semiconductor layer sequence including a first semiconductor layer and a second semiconductor layer. That is, the first type of dopant is implanted after the second semiconductor layer is grown. In addition to the first and second semiconductor layers, the semiconductor layer sequence implanted with the first type of dopant may also include one or more additional semiconductor layers. For example, at least one additional semiconductor layer may be grown before the growth of the first semiconductor layer and / or after the growth of the second semiconductor layer.

[0026] For example, after the growth of the semiconductor layer sequence is complete, i.e., after all growth steps for fabricating the semiconductor body have been performed, implantation of a first type of dopant is performed. For example, the first type of dopant is implanted into the semiconductor layer sequence via a side of the semiconductor layer sequence closer to the second semiconductor layer than the first semiconductor layer. For example, the first type of dopant is implanted at a depth such that it does not reach the C-rich region and / or the first semiconductor layer. For example, the first type of dopant is implanted into the second semiconductor layer. The first type of dopant can be a p-type dopant, such as boron. For example, a p-well is formed during the first type of dopant implantation step.

[0027] According to another embodiment, the first type of dopant is activated at a temperature of at least 1000°C or at least 1500°C. Alternatively, the temperature for activating the first type of dopant may be at most 1800°C or at most 1700°C.

[0028] Heating the semiconductor layer sequence to such temperatures also releases carbon at interstitial sites in the C-rich regions. The released carbon then recombines with carbon vacancies created during the implantation of type-1 dopant and / or with pre-existing carbon vacancies.

[0029] Alternatively, the semiconductor layer sequence can be heated to the aforementioned temperatures independently of the implantation of the first type of dopant. For example, the semiconductor layer sequence can be heated to these temperatures before implantation of the first type of dopant, or even without performing dopant implantation at all. This heating has the same effect as carbon being released from interstitial sites and eventually combining with carbon vacancies.

[0030] According to another embodiment, C ion energy is implanted in the range of 0.5 keV (inclusive) to 100 keV (inclusive), for example, between 1 keV (inclusive) and 50 keV (inclusive). With such implantation energy, the damage caused by implantation can be kept very small.

[0031] According to another embodiment, in the C-rich region, the minimum and / or average concentration of C atoms or C ions at the interstitial sites is at least 10. 14 cm -3 Or at least 10 16 cm -3 At least 10 17 cm-3 or at least 10 18 cm -3 Alternatively, in C-rich regions, the maximum concentration of C atoms or C ions at interstitial sites is at most 10. 21 cm -3Specifically, a C-rich region can be defined as a region in which the minimum concentration is present everywhere, or as a region with the average concentration.

[0032] According to another embodiment, at least one buffer region of the second semiconductor layer is adjacent to a C-rich region and is doped with a second type of dopant. The second type of dopant is, for example, an n-type dopant. Specifically, the second type of dopant differs from the first type of dopant, i.e., it has the opposite conductivity type.

[0033] According to another embodiment, the minimum and / or average concentration of the second type of dopant in at least one buffer region of the second semiconductor layer is greater than the maximum and / or average concentration of the second type of dopant in the first semiconductor layer. For example, the minimum and / or average concentration of the second type of dopant in the buffer region is at least 10 times, at least 100 times, or at least 1000 times greater than the maximum and / or uniform concentration of the second type of dopant in the first semiconductor layer. The minimum and / or average concentration of the second type of dopant in the buffer region is, for example, at least 10... 16 cm -3 Or at least 10 17 cm -3 Alternatively, the maximum and / or average concentration of the second type of dopant in the buffer region may be up to 10. 19 cm -3 Or at most 10 18 cm -3 Similarly, in this case, the buffer region can be defined by a region that satisfies either the minimum doping concentration condition or the average concentration condition everywhere.

[0034] The buffer region can be a buffer layer that extends continuously over the entire lateral extent of the second semiconductor layer, for example, without interruption.

[0035] C-rich regions can lead to strain in the crystal lattice. Buffer regions can compensate for this strain, for example, by improving the growth conditions of the rest of the second semiconductor layer.

[0036] According to another embodiment, a plurality of C-rich regions laterally spaced apart from each other are formed in a first semiconductor layer. In the step of introducing carbon into the first semiconductor layer, for example by C ion implantation, the plurality of C-rich regions are formed. The C-rich regions of the first semiconductor layer may all be arranged at the same height relative to the main extension plane of the first semiconductor layer. That is, a plane parallel to the main extension plane of the first semiconductor layer intersects each C-rich region in the first semiconductor layer.

[0037] For example, the lateral extension of each C-rich region is at most 2µm or at most 1µm and / or at least 0.5µm. For example, the distance between any two adjacent C-rich regions, measured in the lateral direction, is at most 5µm or at most 2µm and / or at least 0.5µm. The C-rich regions can be arranged at grid points of a regular grid. For example, when viewed in a plan view of the side of the first semiconductor layer where the second semiconductor layer is grown, each C-rich region is a rectangular or circular region. Alternatively, the C-rich regions of the first semiconductor layer can be formed as strips, for example, strips extending parallel to each other.

[0038] Multiple C-rich regions can be formed by using masks, for example, during a C ion implantation process.

[0039] According to another embodiment, the method includes the step of introducing carbon into a second semiconductor layer, such that at least a portion of the second semiconductor layer becomes at least one C-rich region. All features disclosed in relation to at least one C-rich region of the first semiconductor layer are also disclosed for at least one C-rich region of the second semiconductor layer. For example, one or more C-rich regions in the second semiconductor layer can be formed using the same methods as those used to form C-rich regions in the first semiconductor layer, such as PIII.

[0040] According to another embodiment, the method includes the step of growing a third semiconductor layer of SiC on the second semiconductor layer. For example, the third semiconductor layer is epitaxially grown. All features disclosed relating to the second semiconductor layer are also disclosed relating to the third semiconductor layer, particularly regarding doping and thickness.

[0041] According to another embodiment, a plurality of C-rich regions laterally spaced apart from each other are formed in the second semiconductor layer. The disclosed features relating to the plurality of C-rich regions in the first semiconductor layer are also disclosed for the plurality of C-rich regions in the second semiconductor layer.

[0042] According to another embodiment, the C-rich regions in the first semiconductor layer and the second semiconductor layer are arranged in an alternating configuration. This specifically means that the C-rich regions of the first semiconductor layer overlap with the C-rich regions of the second semiconductor layer at most partially in at least one lateral direction. For example, the C-rich regions of the first semiconductor layer do not overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. The C-rich regions of the first semiconductor layer are arranged at different heights relative to the main extension plane of the first semiconductor layer and do not overlap with each other, for example, in the vertical direction.

[0043] Next, the semiconductor body will be described. In particular, the semiconductor body can be manufactured using any of the methods described in the embodiments herein. Therefore, all features disclosed in connection with the method are also disclosed with respect to the semiconductor body, and vice versa.

[0044] According to one embodiment, the semiconductor body includes a first semiconductor layer of SiC, a second semiconductor layer of SiC on the first semiconductor layer, and at least one C-rich region in the first semiconductor layer. The C-rich region is adjacent to the second semiconductor layer. In the C-rich region, the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 10. 17 cm -3 The thickness of the C-rich region is at most 100 nm, at most 50 nm, at most 30 nm, and / or at least 10 nm or at least 15 nm. Thus, the thickness is measured along the main extension plane perpendicular to the first semiconductor layer.

[0045] According to another embodiment, the C-rich region has its maximum concentration of C atoms or C ions at interstitial sites located at the interface of the second semiconductor layer. For example, the concentration distribution in the vertical direction perpendicular to the main extension plane of the first semiconductor layer is asymmetrical with respect to the interface between the first and second semiconductor layers. For example, in the first semiconductor layer, the distance measured in the vertical direction from the interface where the concentration drops to less than 0.01 times the maximum concentration is at least two or three orders of magnitude greater than in the second semiconductor layer. For example, the aforementioned distance in the first semiconductor layer is at least 5 nm or at least 10 nm and / or at most 30 nm or at most 25 nm. The maximum concentration of C atoms / C ions at the interstitial sites in the C-rich region can be at least 10. 19 cm -3 and / or at most 10 21 cm -3 .

[0046] The minimum and / or average concentration of C atoms / C ions at interstitial sites in the C-rich region is at least 10. 18 cm -3 The thickness of the portion can be at most 30 nm or at most 25 nm and / or at least 5 nm or at least 10 nm. The minimum and / or average concentration of C atoms / C ions at the interstitial sites within the C-rich region is at least 10. 19 cm -3 The thickness of the portion can be at most 20 nm and at least 10 nm.

[0047] According to another embodiment, the maximum and / or average concentration of carbon vacancies (C vacancies for short) in the second semiconductor layer is at most 10. 12 cm -3 Or at most 10 11 cm -3 This specifically refers to Z. 1 / 2 Empty seat.

[0048] According to another embodiment, at room temperature, the average mobility of charge carriers and the second semiconductor layer is at least 100 cm⁻¹. 2 / Vs or at least 120cm 2 / Vs or at least 150cm 2 / Vs.

[0049] The specified C vacancy concentration and specified mobility in the second semiconductor layer also apply to the first semiconductor layer. When a third semiconductor layer is grown on the second semiconductor layer, these values ​​may additionally or alternatively apply to the third semiconductor layer.

[0050] Next, we will explain power semiconductor devices.

[0051] The power semiconductor device includes a semiconductor body according to any of the embodiments described herein. Furthermore, the power semiconductor device includes electrodes in electrical contact with the semiconductor body. The electrodes may be metal and / or highly doped polysilicon. For example, the power semiconductor device is a transistor, such as a MOSFET or IGBT, or a thyristor.

[0052] In the following, methods for manufacturing semiconductor bodies, semiconductor bodies, and power semiconductor devices will be explained in more detail with reference to the accompanying drawings, based on exemplary embodiments. The drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be denoted by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative and not necessarily drawn to scale. Descriptions of elements or components in each of the following figures will not be repeated as long as their functions correspond to each other in different figures. For clarity, elements may not appear with corresponding reference numerals in all figures. Attached Figure Description

[0053] Figures 1 to 8 The illustrations show different locations in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and exemplary embodiments of the power semiconductor device.

[0054] Figure 9 The DLTS measurement curve is displayed.

[0055] Figure 10 The concentration curves of C atoms or C ions at interstitial sites in the C-rich region produced by PIII are shown.

[0056] Figure 11 The concentration curves of C atoms at interstitial sites in the C-rich region generated by deep ion implantation are shown.

[0057] Figures 12 to 14 The illustrations show different locations in a second exemplary embodiment of the method, as well as exemplary embodiments of the semiconductor body and power semiconductor device.

[0058] Figures 15 to 18The illustrations show different locations in a third exemplary embodiment of the method, as well as other exemplary embodiments of the semiconductor body.

[0059] Figure 19 Another exemplary embodiment of the semiconductor body is shown. Detailed Implementation

[0060] exist Figure 1 The location provides a substrate 4, such as an n-type doped 4H-SiC substrate 4. The substrate 4 can be a standard 4° off-center substrate.

[0061] exist Figure 2 At the location specified, a first semiconductor layer of SiC, such as 4H-SiC, is epitaxially grown on substrate 4. Growth can be performed by chemical vapor deposition (CVD), for example, hot-wall chemical vapor deposition (HWCVD). For example, the first semiconductor layer 1 is grown to a thickness of approximately 10 µm. During growth, the first semiconductor layer 1 can be doped with a second type of dopant, in this case, an n-type dopant.

[0062] exist Figure 3 The growth process is interrupted at a certain location to introduce carbon into the first semiconductor layer 1, thereby creating a C-rich region 11 within the first semiconductor layer. In the C-rich region 11, C atoms or C ions accumulate at interstitial sites. The C-rich region 11 is formed only in areas of the exposed surface of the first semiconductor layer 1, i.e., at a very low depth, such that the C-rich region 11 does not extend over the entire thickness of the first semiconductor layer 1. This is achieved, for example, by implanting C ions using plasma ion immersion implantation (PIII). This implantation technique does allow for the formation of very shallow and well-defined implanted regions.

[0063] exist Figure 3 In the first semiconductor layer 1, the C-rich region 11 extends continuously across the entire exposed surface of the first semiconductor layer 1.

[0064] exist Figure 4 At the location specified, a second semiconductor layer 2 is grown on the first semiconductor layer 1 (i.e., directly on the C-rich region 11) until a semiconductor layer sequence of the desired thickness is obtained. The second semiconductor layer 2 is also SiC, such as 4H-SiC. The growth of the second semiconductor layer 2 can be performed using the same method as the first semiconductor layer 1. Furthermore, during the growth process, the second semiconductor layer 2 can be n-type doped.

[0065] exist Figure 5At the location of the first semiconductor layer 11, an implantation process is performed, in which a second type of dopant, i.e., an n-type dopant, is implanted into the second semiconductor layer 2 to form a buffer region 20 adjacent to the C-rich region 11. The average doping concentration of the buffer region 20 is higher than that of the rest of the first semiconductor layer 1 or the second semiconductor layer 2. This buffer region 20 compensates for the strain caused by carbon in the C-rich region 11.

[0066] and Figure 5 Conversely, buffer region 20 can be generated during the growth of the second semiconductor layer 2.

[0067] exist Figure 6 At the location, a further implantation process is performed, in which a first type of dopant (a p-type dopant in this example) is implanted. Here, a so-called p-well is formed in the second semiconductor layer 2.

[0068] exist Figure 7 At the location, an annealing process is performed. The semiconductor body 10 is heated to a temperature in the range of 1500°C to 1700°C to activate the previously implanted first type of dopant. During this period, C atoms or C ions in the C-rich region 11 at the interstitial sites are partially released and fill the carbon vacancies in the semiconductor body 10.

[0069] exist Figure 8 The location of the final power semiconductor device 100 in the form of a MOSFET is shown. This device 100 has been created by further implanting a second type of dopant into the p-well to create a contact region and applying the main electrodes 5, 6 and the gate electrode 7 onto the semiconductor body 10.

[0070] exist Figure 9 The position of the curves shows the variation of the deep-level transient spectrum (DLTS) signal with temperature for different semiconductor bulks. Curve S9_1 shows the case of a SiC semiconductor bulk without any measures applied to reduce carbon vacancies. Curve S9_1 indicates the position of the Z-axis. 1 / 2 The prominent peak of the vacancy. Curve S9_2 shows the condition of the semiconductor body after oxidation treatment. Carbon vacancies disappear. Curve S9_3 shows the result obtained when the semiconductor body 10 is manufactured as described above (i.e., C-rich region 11 is formed by PIII). In the same case, carbon vacancies also disappear.

[0071] Figure 10The diagram shows the relationship between the concentration of C atoms / C ions at interstitial sites in the C-rich region 11 generated in the SiC layer using PIII and depth, i.e., the distance from the surface of the implanted carbon in the SiC layer. Curve S10_1 shows the concentration of C atoms / C ions at the interstitial sites before heating to a temperature between 1500°C and 1700°C, and curve S10_2 shows the concentration after heating. Due to heating, some C atoms / C ions at the interstitial sites recombine with C vacancies, thereby reducing the concentration of C atoms / C ions at the interstitial sites. It can be seen that the PIII technique produces a very shallow and sharply decreasing concentration distribution, with the maximum concentration occurring at the surface of the SiC layer where the carbon has entered the SiC layer.

[0072] In comparison, Figure 11 This shows the C atom / C ion concentration at interstitial sites when a C-rich region is formed using deep ion implantation with ion energies significantly higher than PIII. In this case, the maximum concentration is found within the SiC layer. This region is larger than... Figure 10 It is thicker and the distribution is not as steep.

[0073] Figure 12 The location in a second exemplary embodiment of the method is shown. At this location, a plurality of laterally spaced C-rich regions 11 are formed on the exposed surface of the first semiconductor layer 1. For example, such a pattern of C-rich regions 11 can be obtained by using a mask on the first semiconductor layer 1 during carbon implantation. Figure 12 The mask is not displayed.

[0074] exist Figure 13 The second semiconductor layer 2 is then grown on the first semiconductor layer 1.

[0075] Figure 14 Showing the use of Figure 12 and 13 The described method relates to an exemplary embodiment of manufacturing the final power semiconductor device 100. In this case, the power semiconductor device 100 is a power MOSFET.

[0076] Figure 15 The position shown in the third exemplary embodiment of the method is related to... Figure 12 The positions are the same.

[0077] exist Figure 16 In this process, a second semiconductor layer 2 is grown on the first semiconductor layer 1.

[0078] exist Figure 17In this process, carbon is introduced into the second semiconductor layer 2, for example, again through PIII, thereby forming laterally spaced C-rich regions 22 in the second semiconductor layer 2. Again, a mask (not shown) can be used here to obtain this C-rich region pattern.

[0079] like Figure 17 As shown, the C-rich region 22 of the second semiconductor layer 2 and the C-rich region 11 of the first semiconductor layer 1 are staggered, wherein region 11 does not overlap with region 22 in the lateral direction.

[0080] Figure 18 The location where the third semiconductor layer 3 is grown on the second semiconductor layer 2 is shown. The third semiconductor layer 3 is also made of SiC and can be grown using the same method as the first and second semiconductor layers 2.

[0081] Figure 19 Another exemplary embodiment of the semiconductor body 10 is shown, which is similar to Figure 18 However, in this case, region 22 of the second semiconductor layer 2 and region 11 of the first semiconductor layer 1 are closer to each other in the vertical direction.

[0082] like Figures 1 to 19 The embodiments shown represent exemplary embodiments; therefore, they do not constitute a complete list of all embodiments based on the improved method, improved semiconductor body, and improved power semiconductor device. For example, actual methods, semiconductor bodies, and power semiconductor devices may differ from the illustrated embodiments in terms of arrangement, components, and layer thickness.

[0083] Reference Marker

[0084] 1 First semiconductor layer

[0085] 2 Second semiconductor layer

[0086] 3 Third semiconductor layer

[0087] 4 Substrate

[0088] 5. Main Electrode

[0089] 6 Main Electrode

[0090] 7. Gate electrode

[0091] 10 Semiconductor Body

[0092] 11 Rich C Area

[0093] 20 Buffer Zone

[0094] 22 Rich C Area

[0095] 100 power semiconductor devices

[0096] Curves S9_1 to S9_3

[0097] S10_1 and S10_2 curves

Claims

1. A method for manufacturing a semiconductor body (10), comprising: An n-type doped substrate made of SiC is provided (4). A first semiconductor layer (1) of SiC is epitaxially grown directly on the substrate (4). The first semiconductor layer (1) is n-type doped, and the average and / or maximum doping concentration in the first semiconductor layer is less than the average and / or minimum doping concentration in the substrate (4). Carbon is introduced into the first semiconductor layer (1) using plasma ion immersion implantation (PIII), such that at least a portion of the first semiconductor layer (1) becomes at least one C-rich region (11), wherein the minimum and / or average concentration of C atoms or C ions at interstitial sites is at least 100 times greater than the maximum and / or average concentration in the first semiconductor layer (1) prior to the carbon introduction step, and the average concentration of C atoms or C ions at interstitial sites in the C-rich region (11) is at least 10. 17 cm -3 And the thickness of the C-rich region (11) is at most 100 nm; A second semiconductor layer (2) of SiC is epitaxially grown on the first semiconductor layer (1) including the at least one C-rich region (11), wherein the second semiconductor layer (2) is n-type doped. At least one buffer region (20) is formed in the second semiconductor layer (2), the buffer region (20) being adjacent to the C-rich region (11) and being n-type doped, the average and / or maximum doping concentration of the buffer region (20) being greater than the average and / or maximum doping concentration in the first semiconductor layer (1), the at least one buffer region (20) being a buffer layer that extends continuously and uninterruptedly over the entire lateral extension of the second semiconductor layer (2), and Further implantation process is performed to form a p-type doped p-well in the second semiconductor layer (2).

2. The method according to claim 1, wherein, The C-rich region (11) is formed on the exposed side of the first semiconductor layer (1) such that after the epitaxial growth of the second semiconductor layer (2), the C-rich region (11) is located between the remaining portion of the first semiconductor layer (1) that has not become C-rich and the second semiconductor layer (2).

3. The method according to claim 1 or 2, wherein, The thickness of the C-rich region (11) is at least 15 nm and at most 50 nm.

4. The method according to claim 1 or 2, further comprising: A first type of dopant is injected into a semiconductor layer sequence, the semiconductor layer sequence including a first semiconductor layer (1) and a second semiconductor layer (2), wherein the first type of dopant is a p-type dopant.

5. The method according to claim 4, further comprising: The first type of dopant is activated at a temperature of at least 1500°C.

6. The method according to claim 4, wherein, Implantation is performed using C ion energies ranging from 1 keV to 50 keV.

7. The method according to claim 1 or 2, wherein, Multiple C-rich regions (11) are formed in the first semiconductor layer (1) and are laterally spaced from each other.

8. The method according to claim 7, further comprising: Carbon is introduced into the second semiconductor layer (2) such that at least a portion of the second semiconductor layer (2) becomes at least one C-rich region (22). A third semiconductor layer (3) of SiC is grown on the second semiconductor layer (2).

9. The method according to claim 8, wherein, Multiple C-rich regions (22) are formed in the second semiconductor layer (2) and are laterally spaced from each other. The C-rich regions (11) in the first semiconductor layer (1) and the C-rich regions (22) in the second semiconductor layer (2) are arranged in an alternating configuration.

10. A semiconductor body (10), comprising: n-type doped substrate made of SiC (4); A first semiconductor layer (1) of SiC directly on the substrate (4), the first semiconductor layer (1) being n-type doped, and the average and / or maximum doping concentration in the first semiconductor layer being less than the average and / or minimum doping concentration in the substrate (4); A second semiconductor layer (2) of SiC is directly on the first semiconductor layer (1), and the second semiconductor layer (2) is n-type doped; At least one C-rich region (11) in the first semiconductor layer (1). At least one buffer region (20) in the second semiconductor layer (2), the buffer region (20) being adjacent to the C-rich region (11) and being n-type doped, wherein the average and / or maximum doping concentration of the buffer region (20) is greater than the average and / or maximum doping concentration in the first semiconductor layer (1), the at least one buffer region (20) being a buffer layer that extends continuously and uninterruptedly over the entire lateral extension of the second semiconductor layer (2), and The p-type doped p-well in the second semiconductor layer (2), wherein The at least one C-rich region (11) is adjacent to the second semiconductor layer (2). In the C-rich region (11), the average concentration of C atoms or C ions at the interstitial sites is at least 10. 17 cm -3 , The thickness of the C-rich region (11) is at most 100 nm.

11. The semiconductor body (10) according to claim 10, wherein, The at least one C-rich region (11) has its maximum concentration of C atoms or C ions at the gap sites at the interface with the second semiconductor layer (2).

12. The semiconductor body (10) according to claim 10 or 11, wherein, The average concentration of C vacancies in the second semiconductor layer (2) is at most 10. 12 cm -3 .

13. The semiconductor body (10) according to claim 10 or 11, wherein, At room temperature, the average mobility of charge carriers in the second semiconductor layer (2) is at least 100 cm⁻¹. 2 / Vs.

14. A power semiconductor device (100), comprising: The semiconductor body (10) according to any one of claims 10 to 13. Electrodes (5, 6, 7) that are in electrical contact with the semiconductor body (10).

Images