Semiconductor package with local interconnects and chiplet integration

Abstract

Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated having one or more cavities or air gaps filled with a low-k material, where a die-to-die routing path electrically connecting a first die and a second die includes a metal line across the one or more cavities. In other embodiments, fan-out may be utilized to create wider bump pitches for local interconnects or for local interconnects used to connect a core region of a die. A plurality of local interconnects may also be utilized to reduce electrostatic discharge.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to U.S. Patent Application No. 18 / 296,587, filed on April 6, 2023, and U.S. Provisional Application No. 63 / 376,859, filed on September 23, 2022, each of which is hereby incorporated by reference. Background Art Technical Field

[0003] Embodiments described herein relate to semiconductor packaging, and more particularly to die-to-die interconnects.

[0004] Background Information

[0005] Current market demands for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming devices, and other mobile devices require more performance and features to be integrated into smaller and smaller spaces. Therefore, multi-die packaging solutions such as multi-chip modules (MCMs), multi-chip integrated fan-outs, system-in-package (SiPs), and stacked packages (PoPs) are moving toward more complex arrangements with more sophisticated wiring requirements to effectively connect multiple dies. Specifically, various 2.5D and 3D packaging solutions have been proposed as multi-die packaging solutions to connect adjacent chips within a single package. Summary of the invention

[0006] Various semiconductor package structures and manufacturing methods including local interconnects are described, wherein the local interconnects can be used to provide die-to-die interconnects. In some specific implementations, the local interconnects can be formed of low dielectric constant (low-k) materials or include cavities that can be filled with low-k materials or air. In an embodiment, a semiconductor package includes a first die, a second die, and a local interconnect electrically connecting the first die to the second die. The local interconnect may include a base layer and a wiring layer supported by the base layer, wherein the wiring layer includes a metal wire across a cavity in the wiring layer. The die-to-die wiring path can then electrically connect the first die to the second die with the metal wire across the cavity.

[0007] In another specific implementation, fan-out can be used to create a wider bump pitch for the local interconnect. In an embodiment, a semiconductor package includes: a first die, the first die including a first plurality of contact pads adjacent to a first edge of the first die above a first input / output region; a second die, the second die including a second plurality of contact pads adjacent to a second edge of the second die above a second input / output region; and a redistribution layer (RDL) spanning over the first die and the second die. The RDL may include a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads, wherein the plurality of landing pads are characterized by a larger pad pitch between pads than the first plurality of contact pads and the second plurality of contact pads. In the embodiment, the local interconnect is bonded to the plurality of landing pads of the RDL.

[0008] In another specific implementation, a fan-out may be utilized to connect the core area of ​​the die. In an embodiment, a semiconductor package includes: a first die having a first plurality of contact pads along a central axis of the first die over a first input / output region; a second die having a second plurality of contact pads over a second input / output region of the second die; and a redistribution layer (RDL) spanning over the first die and the second die. The RDL may include a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads with fan-out wiring. In an embodiment, a local interconnect is connected to the plurality of landing pads of the RDL, the local interconnect is characterized by a longitudinal length spanning the first die and the second die, and the fan-out wiring of the RDL is orthogonal to the longitudinal length.

[0009] In yet another specific implementation, multiple local interconnects may be utilized to scale electrostatic discharge (ESD). In an embodiment, multiple independent local interconnects are used to electrically connect the first die to the second die, wherein each independent local interconnect includes a base layer and a wiring layer supported by the base layer, the wiring layer including die-to-die wiring that electrically connects the first die to the second die. In this way, a larger local interconnect may be divided into multiple smaller local interconnect chiplets, thereby reducing ESD charge accumulation and subsequently reducing ESD protection requirements for input / output (I / O) circuits of the die and / or local interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic cross-sectional side view illustration of a semiconductor package including a local interconnect according to an embodiment.

[0011] Figure 2is a schematic cross-sectional side view illustration of a semiconductor package including a local interconnect according to an embodiment.

[0012] Figure 3A is a schematic cross-sectional side view illustration of a semiconductor package redistribution layer with fan-out routing and local interconnects according to an embodiment.

[0013] Figure 3B According to the implementation plan Figure 3A Schematic top view illustration of a local interconnect.

[0014] Figure 4A is a schematic top view illustration of a loose local interconnect bump pitch according to an embodiment.

[0015] Figure 4B is a schematic cross-sectional side view illustration of a semiconductor package redistribution layer with fan-out routing to support loose local interconnect bump pitches according to an embodiment.

[0016] Figure 5A is a schematic top view illustration of a long reach local interconnect according to an embodiment.

[0017] Figure 5B is a schematic top view of a die structure with repeaters, routing or switching stations and a bonding side for local interconnects according to an embodiment.

[0018] Figure 6 is a schematic top view illustration of a plurality of local interconnects providing die-to-die interconnection according to an embodiment.

[0019] Figure 7 is a schematic cross-sectional side view illustration of a semiconductor package including an embedded local interconnect according to an embodiment.

[0020] Figure 8 is a schematic cross-sectional side view illustration of a semiconductor package including a local interconnect according to an embodiment.

[0021] Fig. 9 is a schematic cross-sectional side view illustration of a local interconnect including a cavity according to an embodiment.

[0022] Fig.10 is a schematic top view illustration of a dielectric support between cavities according to an embodiment.

[0023] Fig.11 is a schematic cross-sectional side view illustration of a local interconnect including a back-facing stacked wiring layer according to an embodiment.

[0024] Fig.12is a schematic cross-sectional side view illustration of a local interconnect including face-to-face stacked wiring layers according to an embodiment.

[0025] Fig.13 is a schematic cross-sectional side view illustration of a local interconnect including face-to-face stacked wiring layers with a base layer removed according to an embodiment.

[0026] Fig.14 is a schematic cross-sectional side view illustration of a local interconnect including two face-to-face stacked wiring layers having a cavity according to an embodiment.

[0027] Fig.15 is a schematic cross-sectional side view illustration of a local interconnect for conditional hybrid bonding according to an embodiment.

[0028] Fig.16 is a schematic cross-sectional side view illustration of a local interconnect of a stacked chiplet including hybrid bonding according to an embodiment. DETAILED DESCRIPTION

[0029] Embodiments describe semiconductor packages and fabrication methods in which local interconnects are utilized for die-to-die interconnection.

[0030] In one aspect, the embodiments describe a wafer reconstruction sequence, wherein multiple dies are reconstructed in a first packaging level, and then local interconnects are placed using suitable techniques such as microbumps, chip-on-wafer hybrid bonding, or through-hole contacts. In some embodiments, delays can be minimized by supporting direct path bonding. Alternatively, wiring fan-out can be accommodated between the die and the local interconnects. This can relax the local interconnect microbump spacing scaling.

[0031] On the other hand, the embodiments describe a local interconnect structure integrating low dielectric constant (low-k) materials or air gaps. This can reduce distance capacitance (fF / mm), thereby reducing energy requirements, improving signal integrity, and may allow for reductions in driver size and input / output area. Such lower distance capacitance can also be exchanged for higher wiring density, and can provide longer distance communications. Examples can be system-on-chip (SoC) to high bandwidth memory (HBM) links, which can span several mm. In an embodiment, the local interconnect wiring layer can be suspended on a mechanical support to hold the wire in place and support component loads. In some embodiments, the local interconnect includes a stacked wiring layer to increase bandwidth, provide additional mechanical support, or provide additional devices, such as passive devices (e.g., decoupling capacitors) or active devices. For example, active devices can support logic, memory, cache, input / output (I / O) or power management integrated circuit (PMIC) functions. For example, integration of decoupling capacitors can allow for power supplies with low noise, while integration of active devices can allow chip core-to-chip core communications, bypassing the die edge, saving on-chip SoC wiring and power and delay budgets.

[0032] On the other hand, local interconnects can be used to increase the bandwidth of die-to-die communication and reduce delay. In a specific implementation, local interconnects can be used as communication bars between logic dies. In such specific implementations, local interconnects can be oriented to communication, meeting bandwidth, power, delay and cost targets. Logic dies such as systems on chip (SOC) may include central processing units (CPUs) or graphics processing units (GPUs). In addition, the periphery of the logic die can be formatted to achieve memory integration and other input / output (I / O) to other devices. Various cost control implementations may be included. For example, logic can be moved from the logic die to the communication bar to reduce the cost of the logic die. The communication bar can also provide voltage shifting capabilities. Using the communication bar can also allow I / O terminals to be flexibly positioned on the logic die without having to be at the edge of the die. The local interconnects and communication bars according to the embodiment are not limited to connecting multiple dies. In an embodiment, the communication bar can provide a connection across a single die.

[0033] In an embodiment, the local interconnect used as a communication strip may include a deserializer, a serializer, and a plurality of repeaters (e.g., active devices) located between the deserializer and the serializer. Where appropriate, the local interconnect may also support other signaling schemes, such as pulse amplitude modulation (PAM), simultaneous bidirectional (SBD), low swing differential, etc. Where appropriate, the local interconnect may support other non-silicon technologies, such as, but not limited to, GaAs. According to an embodiment, the local interconnect may provide level conversion capabilities as needed.

[0034] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and structures. In the following description, many specific details such as specific configurations, sizes and processes are described to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, constructions or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions or characteristics may be combined in one or more embodiments in any appropriate manner.

[0035] As used herein, the terms "over," "to," "between," "across," and "on" may refer to the relative position of one layer relative to other layers. A layer that is "over," "across," or "on" or coupled "to" or "in contact with" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0036] Reference now Figure 1 , a cross-sectional side view illustration of a semiconductor package 100 including a local interconnect 106 according to an embodiment is provided. As shown, the semiconductor package 100 may include a first die 102 and a second die 104 embedded in a gap fill layer 110 (such as a polymer molding compound, an inorganic material, etc.). The die 102, 104 may perform various functions depending on a specific application, including but not limited to a graphics processing unit (GPU), a central processing unit (CPU), artificial intelligence (AI), machine learning logic, a signal processor, a power management integrated circuit (PMIC), logic, memory, a photonic device, a biochip, and any combination thereof.

[0037] In an embodiment, the die 102, 104 may be placed face up on a carrier substrate, followed by encapsulation and RDL formation, including contacting the vias 0 of the die 102, 104. Local interconnects are then attached to the RDL. Figure 1In the illustrated embodiment, a first packaging level 101 including dies 102, 104 and a gap fill layer 110 is formed during a wafer reconstitution process, wherein the dies 102, 104 are placed face down on a carrier substrate and overmolded, after which the carrier substrate is removed. Each of the dies 102, 104 may include an active device area 112 and at least one input / output area 114. In an embodiment, additional components may then be mounted to the reconstructed structure using suitable techniques such as flip chip bonding, chip-on-wafer hybrid bonding, wafer-on-wafer hybrid bonding, etc. In an exemplary embodiment, the additional components may include another active die 118, an integrated passive device 120, and a local interconnect 106. This is exemplary, and the embodiments are not limited to these specific components or component combinations.

[0038] Embodiments are compatible with both face-up and face-down sequences, where factors such as placement accuracy and cost tradeoffs may be considered in selecting the production sequence.

[0039] Still refer to Figure 1 , these components can be installed using multiple solder bumps 116 (which can be microbumps) depending on the bump spacing. This can be followed by optional filling of the bottom filling material 121, followed by a gap filling layer 122 (such as a polymer molding compound, an inorganic material, etc.). Although solder bumps are illustrated, this is not necessary. These components (including local interconnects 106) can be hybrid-bonded, or bonded with dielectric-dielectric bonding members, and interconnected with through-hole connections (e.g., in the last through-hole method). According to an embodiment, through-holes 124 (e.g., through dielectric through-holes, through-molded through-holes, etc.) and through-optional through-holes 126 (e.g., through-silicon through-holes) can be used to vertically interconnect with the first packaging level 101 through various components in the second packaging level 103. Solder bumps 128 can then be put down, followed by cutting of the package 100.

[0040] exist Figure 1 In the particular embodiment shown, the components in the second packaging level 103 are directly bonded to the dies 102, 104 in the first packaging level 101. However, this is merely exemplary and intermediate wiring may be provided. Similarly, wiring may be formed under the second packaging level 103 before applying the solder bumps 128.

[0041] Reference now Figure 2 , an intermediate layer 130 may be formed between the first packaging level 101 and the second packaging level 103. For example, the intermediate layer 130 may be, for example, a dielectric layer, an interposer layer, or a multi-layer redistribution layer (RDL). In the illustrated embodiment, the intermediate layer 130 is an organic or inorganic dielectric layer including a plurality of vertical interconnects 132, which may be vias / landing pads passing through the dielectric layer. A direct interconnect path may minimize delays.

[0042] Reference now FIG. 3A to FIG. 3B , Figure 3A is a schematic cross-sectional side view illustration of a semiconductor package redistribution layer (RDL) 140 with fan-out wiring 142 and local interconnects 106 according to an embodiment; Figure 3B According to the implementation plan Figure 3A Schematic top view illustration of the local interconnect 106. In particular, FIG. 3A to FIG. 3B The fan-out wiring 142 shown can reduce the effective area density of the bonded parts to the bonded parts. More specifically, the solder bumps 116 (microbumps) for the local interconnects 106 are not limited to the I / O area 114, but can instead encroach over the core area 117 (e.g., logic) of the dies 102, 104. In this way, the I / O area area of ​​the dies 102, 104 can be reduced.

[0043] Reference now FIG. 4A to FIG. 4B , Figure 4A is a schematic top view illustration of a loose local interconnect bump pitch according to an embodiment; Figure 4B is a schematic cross-sectional side view illustration of a semiconductor package redistribution layer with fan-out routing to support loose local interconnect bump pitches according to an embodiment. FIG. 4A to FIG. 4B Roughly corresponds to FIG. 3A to FIG. 3B . As shown, the die 102 includes a plurality of contact pads 144 characterized by a pad pitch (P1) above an input / output (I / O) region 114. The contact pads 144 may be connected to landing pads 146, 154 (and solder bumps 116) via fan-out wiring, which may, for example, be included within the RDL 140 or the local interconnect 106. As shown, the landing pads 154 may be located in the RDL 140. As shown, the reverse fan-out wiring 142 may allow the landing pads 146, 154 (and solder bumps 116) to be located outside the I / O region 114 and alternatively above another region such as a core region 117 (e.g., logic). Thus, this reverse fan-out wiring 142 may point toward the die core rather than the die edge 119 between adjacent dies. This reverse fan-out wiring 142 may also be substantially orthogonal to the die edge 119. In FIG. 4A to FIG. 4B Also shown in FIG. 1 are vertical wiring 142 ′ and forward fan-out wiring 142 ″. Furthermore, with respect to such a configuration, the pad pitch ( P2 ) of the landing pad 146 may be greater than the pad pitch ( P1 ) between the contact pads 144 above the I / O region 114 .

[0044] Fan-out routing can also facilitate long-distance local interconnects. Figure 5AIn the illustrated embodiment, the input / output (I / O) area 115 is not limited to the die edge and can be near the central axis 111 of the die. Although the central axis 111 is illustrated, the I / O area 115 area can be distributed at any internal position of the die away from the die edge. In the illustrated embodiment, the fine die-to-die wiring 108 can be located within the local interconnect 106, while the fan-out wiring 148 located outside the local interconnect 106 can extend orthogonally to the longitudinal length of the local interconnect 106 to connect the contact pad 144 of the die 102 to the landing pad 154 in the RDL 140. As such, the die area outside the I / O area can be used for other functions. The solder bump 116 can then connect the RDL 140 landing pad 154 with the landing pad 146 of the local interconnect 106, which is a die-to-die wiring that extends the longitudinal length of the local interconnect 106. Therefore, the fan-out wiring 148 may be parallel to the die edge 119 between the relative I / O regions 114. Similarly, the die-to-die wiring 108 is orthogonal to the die edge 119 between the relative I / O regions 114. According to the embodiment, the fan-out wiring 148 may be included in the RDL 140, as previously described, or even in the die 102, 104. In the case where the total die-to-die wiring 108 length reaches the order of magnitude of several millimeters, repeaters and capacitors may be included in the local interconnect 106 to maintain signal integrity and improve delay. In the illustrated embodiment, the die-to-die wiring 108 length is approximately the same. As shown, the wiring can extend from the far contact pad 144 to the near contact pad 144, and vice versa. In addition, since the fan-out distance is small (e.g., for the fan-out wiring 148), this allows connection to deeper in the die 102, 104 within a given allowable wiring distance.

[0045] Figure 5BIt is a schematic top view of a die structure with a repeater, wiring or switching station 145 and a bonding site for a local interconnect according to an embodiment. As shown, between or inside various die cores, the die structure (or wiring) can be an x-direction structure 141 and a y-direction structure 143. In the case of connecting multiple cores, a repeater, wiring or switching station 145 can be provided along the structure to include a repeater or switch, for example, when changing the wiring direction or route. According to the embodiment, a repeater, wiring or switching station 145 can provide an option of wiring vertically to a local interconnect. In the illustrated embodiment, the local interconnect can be aligned with the appropriate structure in the die, as shown by the position of the solder bump 116. The cost of doing so is to increase the interface area with the local interconnect, wherein the I / O area 115 is to be accommodated in or around the repeater, wiring or switching station 145 or structure. However, this can avoid reaching the die edge and the associated fan-out along the die coastline, which consumes delay, energy and area. Further, the local interconnects may have improved interconnect, low capacitance / mm, improved reach, delay, and energy characteristics relative to structures that are strictly on-die (eg, SoCs).

[0046] So far, the embodiments described have illustrated only a single local interconnect 106 to provide die-to-die interconnection. However, multiple local interconnects can be incorporated into all embodiments. By design, one can have a larger local interconnect where subsequent larger ESD charge accumulation requires greater ESD protection in the I / O circuits. One can break up a larger local interconnect into multiple smaller local interconnect chiplets, thereby reducing ESD charge accumulation and ESD discharge during assembly, and subsequently reducing ESD protection requirements for the I / O circuits. This reduces the I / O area area and capacitance. Figure 6 1 is a schematic top view illustration of a plurality of independent local interconnects 106A providing die-to-die interconnects according to an embodiment. In such embodiments, providing a plurality of smaller local interconnects can mitigate electrostatic discharge (ESD) buildup, allowing for smaller ESD protection circuits, thereby saving capacitance and area. The plurality of independent local interconnects 106A, 106B can additionally have different longitudinal lengths (L1, L2), such as for connecting core area 117 to core area 117 (e.g., core logic to core logic). Figure 5A 106B, and a more typical distance local interconnect connecting I / O regions 114 along adjacent die edges 119. As an example, long distance local interconnect 106B may be used to connect SoC core region 117 to HBM core region 117. In an embodiment, long distance local interconnect 106B may have thicker metal wiring layers and thicker insulator layers than those used for shorter distance local interconnects 106A (e.g., between adjacent I / O regions 114).

[0047] Local interconnects according to embodiments may also be used for intra-die connections. Figure 6 As shown in , local interconnect 106C can be used to connect multiple core areas 117, such as SoC to SoC core areas within a die. As such, the internal die-to-die wiring within local interconnect 106C is used for intra-die connections, rather than inter-die connections. Local interconnects can also be used for both intra-die connections and inter-die connections. Figure 6 As shown in FIG. 1 , local interconnect 106D may be used to connect various regions including a plurality of core regions 117 as well as core regions 117 and / or I / O regions 114 of dies 102 , 104 .

[0048] Local interconnects 106 according to embodiments may be integrated into various semiconductor packages 100 in various ways. Figure 7 1 is a schematic cross-sectional side view illustration of a semiconductor package 100 including an embedded local interconnect 106 according to an embodiment. As shown, the die 102 may be embedded in a gap fill layer 110 within a first packaging level 101, as previously described. This may be accomplished, for example, using a reconfiguration sequence. An RDL 150 may then be optionally formed over the reconfigured structure. The RDL may be a single layer, such as Figure 2 The intermediate layer 130 of the die 102, 104, or a multi-layer RDL, including some RDLs for fan-out wiring. In the illustrated embodiment, the RDL 150 includes a dielectric layer 152 and landing pads 154, 156 formed on the contact pads 144 of the die 102, 104. The local interconnect 106 can then be bonded to the landing pad 154, for example, using a solder bump 116 (e.g., a microbump). The through-hole 126 is optional. This can be followed by encapsulation using a gap fill layer 122, followed by through-hole etching and plating of the through-hole 124. Alternatively, vertical interconnects can be formed before encapsulation. A planarization operation can then be performed, followed by formation of a backside RDL 160. As shown, the backside RDL can include one or more dielectric layers 162 and a metal wiring layer 164. Solder bumps can then be placed on the landing pad 166, followed by cutting of multiple semiconductor packages 100 from the reconstructed structure.

[0049] Figure 8 is a schematic cross-sectional side view illustration of a semiconductor package 100 including an external local interconnect 106 according to an embodiment. Figure 8The semiconductor package 100 shown may include a first packaging level 101 formed using the previously described reconstruction sequence. This is followed by the optional formation of an RDL 150 that may have one or more wiring layers. In the illustrated embodiment, the RDL 150 includes a plurality of dielectric layers 152 and wiring layers 155, which may include fan-out wiring and stacked vias for more vertical interconnects. A plurality of metal stud contacts 158 may be formed on the bottom side of the RDL 150 to provide a spacing height that can accommodate the landing pads 154 that join the local interconnects 106 to the RDL 150. The local interconnects may then be optionally bottom-filled. Solder tips 129 may be placed on the stud contacts 158, followed by insulation of the plurality of semiconductor packages 100.

[0050] So far, various wiring configurations and semiconductor packages have been described. Figures 9 to 16 In the following description of the present invention, various local interconnect structures are described. It should be understood that any of the following local interconnect structures can be implemented with any of the various wiring configurations and semiconductor packages described herein.

[0051] Reference now Figures 9 and 10 , schematic cross-sectional side and top view illustrations of local interconnects including cavities according to embodiments are provided. As shown, local interconnects 106 may include a base layer 170 and a wiring layer 180. The base layer may be formed of various rigid materials including glass and semiconductors such as silicon substrates. A device layer 172 including active devices (e.g., transistors) may optionally be located in the top portion of the base layer 170. In embodiments, a deep trench capacitor (DTC) 174 may be formed into the base layer (including the device layer 172). The wiring layer 180 may include a plurality of insulator layers 182 and a metal layer forming metal lines 184. One or more cavities 185 may be formed in one or more insulator layers 182. As such, metal lines 184 may span cavities 185 in the wiring layer 180. These metal lines 184 may support the die-to-die wiring 108 paths of the previously described electrical connection dies 102, 104.

[0052] like Figures 9 and 10As shown in , one or more cavities 185 may be separated by support walls 188 formed by insulator layer 182. Metal line 184 then extends through one or more support walls 188. In an embodiment, cavity 185 is an air cavity, and thus metal line 184 is suspended over cavity 185 by support wall 188. Various low-k dielectric materials (k<3) may also be used. Exemplary materials include ultra-low-k (ULK) materials (k=2-3), extremely low-k (ELK) materials (k=2.5 or less), polymers, aerogels, and the like. According to an embodiment, cavity 185 area (air gap or filled with low-k dielectric material) may be maximized and support wall 188 area minimized to balance low dielectric constant benefits and mechanical strength. In an embodiment, cavity 185 is wider than support wall 188, so that metal line 184 spans a greater distance than cavity 185 than support wall 188.

[0053] To provide additional mechanical integrity, a dielectric cap 190 may be bonded (e.g., in the case of an air cavity) or deposited (e.g., in the case of a low-k dielectric layer) to the top side of wiring layer 180. For example, this may be performed using WoW dielectric bonding, spin coating, chemical vapor deposition, etc. In an embodiment, dielectric cap 190 is glass. Vias 192 may then be formed through dielectric cap 190 to contact a metal wiring layer in wiring layer 180. Alternatively, preformed vias 192 may be bonded to vias 186 inside wiring layer 180, as illustrated. Depending on the embodiment, support walls 188 may additionally support vias 186. Although not separately illustrated, metal-insulator-metal (MIM) capacitors may optionally be located where space permits. Fig. 9 The MIM capacitor according to the embodiment may be planar or 3-dimensional.

[0054] Fig.11 is a schematic cross-sectional side view illustration of a local interconnect 106 including a back-facing stacked wiring layer 180 according to an embodiment. So far, all local interconnects 106 have been described as a single-body structure. For example, Fig. 9 The local interconnect 106 according to an embodiment is a chiplet formed of a single base layer 170 supporting a wiring layer 180. The local interconnect 106 according to an embodiment may include a stacked chiplet 195. Fig.11 The embodiment shown is a face-to-back stacked assembly.

[0055] exist Fig.11In the illustrated embodiment, the second chiplet 195 includes a second base layer 270, a second wiring layer 280, a second optional device layer 272, a second dielectric layer 282, and a second metal line 284. The second DTC 274 may also be formed within the second base layer 270. In addition, the optional MIM capacitor 210 is illustrated as being formed in the second wiring layer 280. As shown, the back side of the second base layer 270 may be bonded to the optional dielectric cap 190 using a WoW dielectric bond. In this embodiment, the second base layer 270 may be included to achieve mechanical integrity or to support additional DTCs. In this embodiment, the second wiring layer 280 does not include the cavity 185. Alternatively, the cavity 185 may also be included in the second wiring layer 280. In another variation, the cavity 185 may be included in the second wiring layer 280 instead of the wiring layer 180. Vias 202, 286 may be formed to provide electrical wiring between multiple wiring layers and solder bumps 116 (e.g., microbumps). As shown, the vias 202 in the stacked embodiment can connect the solder bumps 116 to either (or both) of the wiring layer 180 and the second wiring layer 280. The vias 202 can also connect the wiring layer 180 to the second wiring layer 280. Depending on the embodiment, the support wall 188 can additionally support the vias 202. It should be understood that any combination of optional device layers 172, 272 and DTCs 174, 274 can be provided, such as no device layers, no DTCs, and combinations thereof.

[0056] Fig.12 is a schematic cross-sectional side view illustration of a local interconnect 106 including face-to-face stacked wiring layers according to an embodiment. In this embodiment, a second wiring layer 280 is bonded to the wiring layer 180 (e.g., a WoW dielectric bond), and a second base layer 270 is on the side of the second wiring layer 280 opposite the wiring layer 180. In this configuration, an RDL 220 including a metal wiring layer 224, a dielectric layer 226, and vias 222 may be formed over the second base layer 270 to support fan-out wiring for solder bump 116 (e.g., microbump) attachment.

[0057] It is not necessary to maintain the base layer in a stacked assembly. Fig.13 is a schematic cross-sectional side view illustration of a local interconnect 106 including face-to-face stacked wiring layers with the second substrate layer removed according to an embodiment. Fig.13 The fabrication sequence of the local interconnect 106 can be similar to Fig.12 The manufacturing sequence continues in a similar manner, and then the second base layer 270 is removed after the second wiring layer 280 is WoW-bonded to the wiring layer 180 .

[0058] As previously described, the second wiring layer 280 may also include a cavity 185 . Fig.141 is a schematic cross-sectional side view illustration of a local interconnect 106 including two face-to-face stacked wiring layers having a cavity 185 according to an embodiment. Fig.14 The fabrication sequence of the local interconnect 106 can be similar to Fig.12 The manufacturing sequence of is continued in a similar manner. However, this is exemplary, and the cavity 185 may be formed in any layer of the wiring layer 180 and / or the second wiring layer 280 .

[0059] It should be understood that although embodiments have been described and illustrated herein, solder bumps (e.g., microbumps) have been used for hybrid bonding. Fig.15 In the embodiment shown, RDL 220 includes a planarized surface 223 that spans dielectric layer 226 and landing pads 146. According to an embodiment, any of the local interconnects 106 and other features in the same packaging level may be hybrid bonded.

[0060] Fig.16 1 is a schematic cross-sectional side view illustration of a local interconnect 106 including a hybrid bonded stacked chiplet 195 according to an embodiment. As shown, in addition to bonding the dielectric layer, the face-to-face landing pads 146 may also be metal-to-metal bonded. When preparing the chiplet or local interconnect hybrid bond pads, dummy bond pads 146D may be additionally inserted along the bonding interface to ensure galvanic corrosion control.

[0061] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible to form semiconductor packages with local interconnects. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as embodiments of the claims for purposes of illustration.

Claims

1. A semiconductor package, comprising: First bare film; The second die; and a local interconnect electrically connecting the first die and the second die, wherein the local interconnect comprises a base layer and a wiring layer supported by the base layer, the wiring layer comprising metal lines spanning cavities in the wiring layer; Wherein a die-to-die routing path electrically connecting the first die and the second die includes the metal line crossing the cavity. The semiconductor package according to claim 1 , wherein the base layer is a silicon layer. 3 . The semiconductor package according to claim 1 , wherein the wiring layer includes a plurality of supporting walls, and the metal wire extends through the plurality of supporting walls. The semiconductor package according to claim 1 , wherein the cavity is an air cavity. The semiconductor package of claim 1 , wherein the cavity is filled with a material characterized by a dielectric constant less than 3. The semiconductor package of claim 1 , wherein the substrate layer comprises a plurality of deep trench capacitors. 7 . The semiconductor package according to claim 1 , wherein the wiring layer comprises a metal-insulator-metal (MIM) capacitor. 8 . The semiconductor package according to claim 1 , further comprising a second wiring layer over the wiring layer. 9 . The semiconductor package according to claim 8 , wherein the second wiring layer includes a metal-insulator-metal (MIM) capacitor. 10 . The semiconductor package according to claim 8 , further comprising a second base layer between the second wiring layer and the wiring layer. 11 . The semiconductor package according to claim 8 , further comprising a second base layer, wherein the second wiring layer is bonded to the wiring layer, and the second base layer is on a side of the second wiring layer opposite to the wiring layer. 12 . The semiconductor package according to claim 8 , further comprising a plurality of deep trench capacitors in the wiring layer or the second wiring layer and a plurality of active devices in the substrate layer.

13. The semiconductor package according to claim 1: wherein the first die includes a first plurality of contact pads along a central axis of the first die over a first input / output region and a second plurality of contact pads over a second input / output region of the first die; Also included is a redistribution layer (RDL) spanning over the first die, the redistribution layer including a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads using fan-out wiring; wherein the local interconnect is connected to the plurality of landing pads of the RDL; and Wherein the local interconnect is characterized by a longitudinal length across the first die, and the fan-out wires of the RDL are orthogonal to the longitudinal length.

14. The semiconductor package according to claim 13, wherein: said metal line of said local interconnect spans along said longitudinal length; The local interconnect is a connecting bar; The local interconnect connects a first core region of the first die to a second core region of the first die; and The local interconnect includes an active device.

15. The semiconductor package according to claim 1: The local interconnect is part of a plurality of independent local interconnects that electrically connect the first die and the second die, wherein each independent local interconnect includes a base layer and a wiring layer supported by the base layer, the wiring layer including die-to-die wiring that electrically connects the first die and the second die.

16. The semiconductor package of claim 15, wherein the plurality of independent local interconnects comprises a first local interconnect characterized by a first longitudinal length spanning the first die and the second die and a second local interconnect characterized by a second longitudinal length spanning the first die and the second die, wherein the second longitudinal length is longer than the first longitudinal length.

17. A semiconductor package, comprising: a first die including a first plurality of contact pads over a first input / output region adjacent to a first edge of the first die; a second die including a second plurality of contact pads over a second input / output region adjacent a second edge of the second die; a redistribution layer (RDL) spanning over the first die and the second die, the RDL comprising a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads, wherein the plurality of landing pads are characterized by a greater pad pitch between pads than the first plurality of contact pads and the second plurality of contact pads; and A local interconnect is bonded to the plurality of landing pads of the RDL. 18 . The semiconductor package of claim 17 , wherein a first portion of the plurality of landing pads spans over a first logic region of the first die. 19 . The semiconductor package of claim 17 , wherein the local interconnect comprises a base layer and a wiring layer supported by the base layer, the wiring layer comprising metal lines crossing cavities in the wiring layer.

20. A semiconductor package, comprising: a first die comprising a first plurality of contact pads along a central axis of the first die over a first input / output region; a second die comprising a second plurality of contact pads over a second input / output region of the second die; a redistribution layer (RDL) spanning over the first die and the second die, the RDL comprising a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads using fan-out wiring; and a local interconnect connected to the plurality of landing pads of the RDL; Wherein the local interconnect is characterized by a longitudinal length spanning the first die and the second die, and the fan-out wires of the RDL are orthogonal to the longitudinal length.

21. The semiconductor package of claim 20, wherein the local interconnect comprises die-to-die wires along the longitudinal length.

22. The semiconductor package of claim 20, wherein the local interconnect is a via bar.

23. The semiconductor package of claim 20, wherein the local interconnect connects a first core region of the first die to a second core region of the second die.

24. The semiconductor package of claim 18, wherein the local interconnect comprises an active device.

25. The semiconductor package of claim 20, further comprising an active die adjacent to the local interconnect and below the first die to provide a communication function with the first die.

26. The semiconductor package of claim 20, further comprising an integrated passive device adjacent to the local interconnect and beneath the second die.

27. A semiconductor package, comprising: a first die comprising a first plurality of contact pads along a central axis of the first die over a first input / output region and a second plurality of contact pads over a second input / output region of the first die; a redistribution layer (RDL) spanning over the first die, the RDL comprising a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads using fan-out wiring; and a local interconnect connected to the plurality of landing pads of the RDL; Wherein the local interconnect is characterized by a longitudinal length across the first die, and the fan-out wires of the RDL are orthogonal to the longitudinal length.

28. The semiconductor package according to claim 27, wherein: The local interconnects include die-to-die wires along the longitudinal length; The local interconnect is a connecting bar; The local interconnect connects a first core region of the first die to a second core region of the first die; and The local interconnects include active devices.

29. The semiconductor package of claim 27, wherein the local interconnect comprises a base layer and a wiring layer supported by the base layer, the wiring layer comprising metal lines crossing cavities in the wiring layer.

30. A semiconductor package, comprising: First bare film; The second die; and A plurality of independent local interconnects electrically connecting the first die and the second die, wherein each independent local interconnect comprises a base layer and a wiring layer supported by the base layer, the wiring layer comprising die-to-die wiring electrically connecting the first die and the second die.

31. A semiconductor package according to claim 30, wherein the plurality of independent local interconnects include a first local interconnect characterized by a first longitudinal length spanning the first die and the second die and a second local interconnect characterized by a second longitudinal length spanning the first die and the second die, wherein the second longitudinal length is longer than the first longitudinal length.

32. The semiconductor package of claim 30, wherein one or more of the plurality of independent local interconnects comprises a metal line that spans a cavity in the wiring layer.

Images