Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a first wiring, a second wiring, a channel portion, a first charge storage portion, and a second charge storage portion. The first wiring extends in a first direction, and the second wiring is adjacent to the first wiring in a second direction intersecting the first direction and extends in the first direction. The channel portion is provided between the first wiring and the second wiring, and extends in a third direction intersecting the first direction and the second direction. The first charge storage portion is provided between the first wiring and the channel portion. The second charge storage portion is provided between the second wiring and the channel portion. The first charge storage parts adjacent to each other in the third direction are provided so as to form a first gap between the first charge storage parts. The second charge storage parts adjacent to each other in the third direction are provided so as to form a second gap between the second charge storage parts. A first impurity diffusion region and a second impurity diffusion region, in which an impurity element is diffused, are provided in a channel section between adjacent first charge storage sections and between adjacent second charge storage sections.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0002] The industry discloses a semiconductor memory device having a stacked body in which insulating films and word lines are alternately stacked, and a semiconductor pillar penetrating the stacked body. However, it is expected that the electrical characteristics of the semiconductor memory device will be further improved.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 0336336 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor memory device having improved electrical characteristics.

[0008] [Technical means to solve the problem]

[0009] The semiconductor memory device of the embodiment includes a substrate, a first wiring, a second wiring, a channel portion, a first charge storage portion, a second charge storage portion, a first insulating film, and a second insulating film. The first wiring extends in a first direction. The second wiring is adjacent to the first wiring in a second direction intersecting the first direction and extends in the first direction. The channel portion is provided between the first wiring and the second wiring and extends in a third direction intersecting the first direction and the second direction. The first charge storage portion is provided between the first wiring and the channel portion. The second charge storage portion is provided between the second wiring and the channel portion. The first insulating film is provided between the first charge storage portion and the channel portion. The second insulating film is provided between the second charge storage portion and the channel portion. The first charge storage portions adjacent in the third direction are provided in such a manner as to form a first gap between the first charge storage portions adjacent in the third direction. The second charge storage portions adjacent in the third direction are provided in such a manner as to form a second gap between the second charge storage portions adjacent in the third direction. A first impurity diffusion region in which an impurity element is diffused is provided inside the channel portion between the first charge storage portions adjacent in the third direction. A second impurity diffusion region in which an impurity element is diffused is provided inside the channel portion between the second charge storage portions adjacent in the third direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a perspective view showing the structure of a semiconductor memory device according to an embodiment.

[0011] Figure 2 yes Figure 1 4 is a cross-sectional view of a region of the semiconductor memory device shown in FIG.

[0012] Figure 3 yes Figure 2 A cross-sectional view of the semiconductor memory device shown in FIG. 1 taken along line F3 - F3 .

[0013] Figure 4 Yes means Figure 2 An enlarged cross-sectional view of the first floating gate electrode FGA and its vicinity shown in FIG.

[0014] Figure 5 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 6 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Figure 7 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Figure 8 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Fig. 9 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Fig.10 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0020] Fig.11 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0021] Fig.12 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0022] Fig.13 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0023] Fig.14 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0024] Fig.15 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0025] Fig.16 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0026] Fig.17It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0027] Fig.18 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0028] Fig.19 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0029] Fig. 20 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0030] Fig.21 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0031] Fig. 22 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0032] Fig.23 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0033] Fig.24 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0034] Fig.25 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0035] Fig.26 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0036] Fig. 27 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0037] Fig.28 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0038] Fig.29 It is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0039] Fig.30 is a cross-sectional view of a semiconductor memory device showing a modification of the embodiment. DETAILED DESCRIPTION

[0040] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. In addition, repeated descriptions of these components are sometimes omitted. The accompanying drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. may not be the same as the actual object.

[0041] In this specification, "connection" is not limited to the case of physical connection, but also includes the case of electrical connection. That is, "connection" is not limited to the case of two parts being connected, but also includes the case of other parts being interposed between the two parts. "Facing" is not limited to the case of two parts being directly adjacent, but also includes the case of other parts being present between the two parts. In addition, "facing" also includes the case of parts of each of the two parts being adjacent to each other. "XX is set on YY" is not limited to the case of XX and YY being connected, but also includes the case of other parts being interposed between XX and YY. "Annular" is not limited to circular rings, but also includes rectangular rings. In this specification, "adjacent" is not limited to the case of being adjacent to each other, but also includes the case of other elements being present between the two elements as objects. "Parallel", "orthogonal", or "same" also include the cases of "approximately parallel", "approximately orthogonal", or "approximately the same", respectively. "Extending in the A direction" means, for example, that the dimension in the A direction is greater than the minimum dimension of each dimension in the following X direction, Y direction, and Z direction. The "A direction" described here is an arbitrary direction.

[0042] In addition, the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are first defined. The +X direction, -X direction, +Y direction, and -Y direction are directions along the surface of the silicon substrate 10 described below. The +X direction is one of the directions in which the bit line BL described below extends. The -X direction is a direction opposite to the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the "X direction". The +Y direction and the -Y direction are directions that intersect (for example, are orthogonal to) the X direction. The +Y direction is one of the directions in which the word line WL described below extends. The -Y direction is a direction opposite to the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the "Y direction". The +Z direction and the -Z direction are directions that intersect (for example, are orthogonal to) the X direction and the Y direction, and are the thickness direction of the silicon substrate 10. The +Z direction is a direction from the silicon substrate 10 toward the stacked body 50 described below. The -Z direction is a direction opposite to the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the "Z direction". The Z direction corresponds to a direction perpendicular to the surface of the silicon substrate 10 used to form the semiconductor memory device 1. In this specification, the "+Z direction" is sometimes referred to as "up" and the "-Z direction" is sometimes referred to as "down". However, these expressions are for convenience and do not define the direction of gravity. The +Y direction is an example of the "first direction". The +X direction is an example of the "second direction". The +Z direction is an example of the "third direction".

[0043] In the plan views and cross-sectional views in the drawings referred to below, illustration of some components such as wirings, contacts, and interlayer insulating films is appropriately omitted for ease of understanding.

[0044] (Implementation Method)

[0045] <1. Overall structure of a semiconductor memory device>

[0046] First, the overall configuration of a semiconductor storage device 1 according to the embodiment will be described. The semiconductor storage device 1 is a nonvolatile semiconductor storage device, such as a NAND flash memory.

[0047] Figure 1 1 is a perspective view showing the structure of semiconductor memory device 1. Semiconductor memory device 1 includes, for example, silicon substrate 10, lower structure 20, a plurality of pillars (columnar members) 30, a plurality of tunnel insulating films 40, stacked body 50, upper structure 70, and a plurality of contacts 80.

[0048] The silicon substrate 10 is a substrate serving as a base of the semiconductor memory device 1. At least a portion of the silicon substrate 10 is formed in a plate shape along the X direction and the Y direction. The silicon substrate 10 is formed of, for example, a semiconductor material including silicon (Si). The silicon substrate 10 is an example of a "substrate".

[0049] The lower structure 20 is provided on the silicon substrate 10. The lower structure 20 includes, for example, a lower insulating film 21, a plurality of source lines SL, an upper insulating film 25, and an insulating member 26 (see Figure 3 ). A lower insulating film 21 is provided on the silicon substrate 10. A plurality of source lines SL are provided on the lower insulating film 21. The plurality of source lines SL are adjacent to each other in the X direction and extend in the Y direction respectively. The source lines SL are formed, for example, by a conductive layer 22 provided on the lower insulating film 21, a wiring layer 23 provided on the conductive layer 22, and a conductive layer 24 provided on the wiring layer 23. An upper insulating film 25 is provided above the plurality of source lines SL. An insulating member 26 is provided between the source lines SL and the upper insulating film 25, and between the lower insulating film 21 and the upper insulating film 25.

[0050] A plurality of columns 30 are provided on the source line SL, and extend in the Z direction respectively. The plurality of columns 30 are provided so as to be separated from each other in the X direction and the Y direction. For example, when viewed from the Z direction, the plurality of columns 30 are arranged in a matrix along the X direction and the Y direction. Each column 30 includes a semiconductor material (for example, amorphous silicon (а-Si)). The column 30 is sometimes referred to as a silicon column. The lower end of each column 30 passes through the upper insulating film 25 of the lower structure 20 and is connected to the source line SL. The structure of the column 30 will be described in detail below.

[0051] The plurality of tunnel insulating films 40 are provided at least on the side surfaces in the -X direction and the side surfaces in the +X direction of each pillar 30. In the present embodiment, each tunnel insulating film 40 is formed in a ring shape surrounding the side surfaces in the -X direction, the +X direction, the -Y direction, and the +Y direction of the pillar 30. In the illustrated example, the plurality of tunnel insulating films 40 are provided intermittently along the side surfaces in the -X direction and the +X direction of each pillar 30, but the tunnel insulating film 40 may also extend continuously in the Z direction, for example, across the entire length (full height) of the pillar 30 in the Z direction.

[0052] The tunnel insulating film 40 is a film that is generally insulating, but through which a tunnel current flows when a specified voltage within the range of the driving voltage of the semiconductor memory device 1 is applied. The tunnel insulating film 40 includes, for example, silicon oxide. Hereinafter, the portion of each tunnel insulating film 40 disposed on the -X direction side of the pillar 30 is referred to as the "first tunnel insulating film 40A", and the portion disposed on the +X direction side of the pillar 30 is referred to as the "second tunnel insulating film 40B". The first tunnel insulating film 40A is disposed between a plurality of first floating gate electrodes FGA arranged in the Z direction described below and the first channel portion 31A described below. The second tunnel insulating film 40B is disposed between a plurality of second floating gate electrodes FGB arranged in the Z direction described below and the second channel portion 31B described below. The first tunnel insulating film 40A is an example of a "first insulating film", and the second tunnel insulating film 40B is an example of a "second insulating film".

[0053] The stacked body 50 is provided on the lower structure 20. The stacked body 50 includes, for example, a plurality of floating gate electrodes FG, a plurality of word lines WL, a plurality of source side selection gate electrodes 51, a plurality of source side selection gate lines SGS, a plurality of drain side selection gate electrodes 52, a plurality of drain side selection gate lines SGD, a plurality of blocking insulating films 60, an insulating member 55, and an insulating member 56 (refer to FIG. 34 ).

[0054] The floating gate electrode FG is an electrode film disposed on the side of each pillar 30. The plurality of floating gate electrodes FG include a plurality of first floating gate electrodes FGA located on the -X direction side relative to each pillar 30, and a plurality of second floating gate electrodes FGB located on the +X direction side. The plurality of first floating gate electrodes FGA are disposed separately from each other in the Z direction. The first floating gate electrode FGA is located on the side opposite to the pillar 30 relative to the first tunnel insulating film 40A. Similarly, the plurality of second floating gate electrodes FGB are disposed separately from each other in the Z direction. The second floating gate electrode FGB is located on the side opposite to the pillar 30 relative to the second tunnel insulating film 40B. The floating gate electrode FG is a film having charge storage capability. The floating gate electrode FG includes, for example, polysilicon. The first floating gate electrode FGA is an example of a "first charge storage unit". The second floating gate electrode FGB is an example of a "second charge storage unit".

[0055] The word lines WL are wirings provided on the sides of the pillars 30. The plurality of word lines WL include a plurality of first word lines WLA located on the -X direction side with respect to the pillars 30, and a plurality of second word lines WLB located on the +X direction side. The first word lines WLA are an example of "first wirings". The second word lines WLB are an example of "second wirings".

[0056] A plurality of first word lines WLA are disposed separately from each other in the Z direction. Similarly, a plurality of second word lines WLB are disposed separately from each other in the Z direction. The first word line WLA and the second word line WLB are adjacent to each other in the X direction and extend in the Y direction respectively. The first word line WLA is located on the side opposite to the pillar 30 with respect to the first floating gate electrode FGA. The second word line WLB is located on the side opposite to the pillar 30 with respect to the second floating gate electrode FGB. In other words, the first floating gate electrode FGA is disposed between the first word line WLA and the pillar 30. The second floating gate electrode FGB is disposed between the second word line WLB and the pillar 30. The first word line WLA and the second word line WLB are led out in opposite directions to each other in the Y direction, for example, and are controlled independently of each other.

[0057] When electrons are injected into the floating gate electrode FG or when electrons injected into the floating gate electrode FG are extracted from the floating gate electrode FG, a voltage is applied to the word line WL through a driving circuit (not shown), thereby applying a specified voltage to the floating gate electrode FG connected to the word line WL. The first floating gate electrode FGA changes the storage state of electrons when a voltage is applied through the first word line WLA. On the other hand, the second floating gate electrode FGB changes the storage state of electrons when a voltage is applied through the second word line WLB. The structure of the word line WL will be described in detail below.

[0058] The source side selection gate electrode 51 is an electrode film provided on the side of each pillar 30. The plurality of source side selection gate electrodes 51 include a first source side selection gate electrode 51A located on the -X direction side with respect to each pillar 30, and a second source side selection gate electrode 51B located on the +X direction side. The first source side selection gate electrode 51A is located on the side opposite to the pillar 30 with respect to the first tunnel insulating film 40A. The second source side selection gate electrode 51B is located on the side opposite to the pillar 30 with respect to the second tunnel insulating film 40B. The source side selection gate electrode 51 is provided between the floating gate electrode FG closest to the silicon substrate 10 among the plurality of floating gate electrodes FG corresponding to the same pillar 30 and the silicon substrate 10.

[0059] The source side selection gate line SGS is a wiring provided on the side of each pillar 30. The plurality of source side selection gate lines SGS include a first source side selection gate line SGSA located on the -X direction side with respect to each pillar 30, and a second source side selection gate line SGSB located on the +X direction side. The first source side selection gate line SGSA is located on the side opposite to the pillar 30 with respect to the first source side selection gate electrode 51A. The second source side selection gate line SGSB is located on the side opposite to the pillar 30 with respect to the second source side selection gate electrode 51B. The source side selection gate line SGS extends in the Y direction. When the source side selection gate line SGS is connected between the pillar 30 and the source line SL, a voltage is applied by a driving circuit (not shown) to apply a specified voltage to the source side selection gate electrode 51 connected to the source side selection gate line SGS. The source side selection gate line SGS is located between the word line WL closest to the silicon substrate 10 among the plurality of word lines WL corresponding to the same pillar 30 and the silicon substrate 10. In the present embodiment, the source side selection gate line SGS and the source side selection gate electrode 51 are referred to as a selection transistor. In addition, the selection transistor may not include the source side selection gate electrode 51.

[0060] The drain side selection gate electrode 52 is an electrode film provided on the side of each pillar 30. The plurality of drain side selection gate electrodes 52 include a first drain side selection gate electrode 52A located on the -X direction side with respect to each pillar 30, and a second drain side selection gate electrode 52B located on the +X direction side. The first drain side selection gate electrode 52A is located on the side opposite to the pillar 30 with respect to the first tunnel insulating film 40A. The second drain side selection gate electrode 52B is located on the side opposite to the pillar 30 with respect to the second tunnel insulating film 40B. The drain side selection gate electrode 52 is located at a position farther from the silicon substrate 10 than the floating gate electrode FG farthest from the silicon substrate 10 among the plurality of floating gate electrodes FG corresponding to the same pillar 30.

[0061] The drain side selection gate line SGD is a wiring provided on the side of each pillar 30. The plurality of drain side selection gate lines SGD include a first drain side selection gate line SGDA located on the -X direction side relative to each pillar 30, and a second drain side selection gate line SGDB located on the +X direction side. The first drain side selection gate line SGDA is located on the side opposite to the pillar 30 relative to the first drain side selection gate electrode 52A. The second drain side selection gate line SGDB is located on the side opposite to the pillar 30 relative to the second drain side selection gate electrode 52B. The drain side selection gate line SGD extends in the Y direction. When the drain side selection gate line SGD is connected between the pillar 30 and the bit line BL described below, a voltage is applied to the drain side selection gate line SGD through a driving circuit not shown, thereby applying a specified voltage to the drain side selection gate electrode 52 connected to the drain side selection gate line SGD. The drain side selection gate line SGD is located farther from the silicon substrate 10 than the word line WL farthest from the silicon substrate 10 among the multiple word lines WL corresponding to the same pillar 30. That is, the drain side selection gate line SGD is located on the opposite side of the silicon substrate 10 with respect to the multiple word lines WL corresponding to the same pillar 30.

[0062] In the present embodiment, the drain-side selection gate line SGD and the drain-side selection gate electrode 52 are referred to as a selection transistor. In addition, the selection transistor may not include the drain-side selection gate electrode 52.

[0063] The blocking insulating film 60 is provided between the floating gate electrode FG and the word line WL, between the source side selection gate electrode 51 and the source side selection gate line SGS, and between the drain side selection gate electrode 52 and the drain side selection gate line SGD. The blocking insulating film 60 is a film through which no current substantially flows even when a voltage is applied within the range of the driving voltage of the semiconductor memory device 1. The configuration of the blocking insulating film 60 will be described in detail below.

[0064] The insulating member 55 is provided between the columns 30 arranged in the Y direction to electrically insulate the columns 30. In other words, the word line WL and the floating gate electrode FG are not provided between two columns 30 arranged in the Y direction. Therefore, the first floating gate electrode FGA and the second floating gate electrode FGB are not connected to each other. In addition, an insulating member 56 (see FIG. 1 ) is provided between the word lines WL adjacent to each other in the X direction. Fig.29 ) to electrically insulate multiple word lines WL.

[0065] The upper structure 70 is provided on the stacked body 50. The upper structure 70 includes, for example, a plurality of bit lines BL, wiring L1 (not shown) for source-side selection gate lines SGS, wiring L2 for word lines WL, and wiring L3 for drain-side selection gate lines SGD.

[0066] The plurality of contacts 80 extend in the Z direction. The plurality of contacts 80 include, for example, a plurality of contacts 81 for the pillars 30, a plurality of contacts 82 (not shown) for the source side selection gate line SGS, a plurality of contacts 83 for the word line WL, and a plurality of contacts 84 for the drain side selection gate line SGD.

[0067] The contact 81 is provided on the pillar 30. The plurality of bit lines BL are provided to be separated from each other in the Y direction and extend in the X direction respectively. When the pillar 30 provided closest to the -X direction side among the plurality of pillars 30 arranged in the X direction is set as the first one, the odd-numbered pillars 30A are connected to the common bit line BLA via the contact 81. The even-numbered pillars 30B are connected to the common bit line BLB different from the bit line BLA via the contact 81. The pillars 30A and 30B adjacent to each other among the plurality of pillars 30 arranged in the X direction are not connected to the common bit line.

[0068] A plurality of contacts 82 (not shown) are provided at the ends of the source side selection gate line SGS in the +Y direction. A wiring L1 (not shown) is provided on the contacts 82 and extends in the Y direction. The wiring L1 is connected to the source side selection gate line SGS via the contacts 82 .

[0069] A plurality of contacts 83 are provided at the ends of the word line WL in the Y direction. The wiring L2 is provided on the contacts 83 and extends in the Y direction. The wiring L2 is connected to the word line WL via the contacts 83 .

[0070] A plurality of contacts 84 are provided at the ends of the drain-side selection gate line SGD in the +Y direction. The wiring L3 is provided on the contacts 84 and extends in the Y direction. The wiring L3 is connected to the drain-side selection gate line SGD via the contacts 84 .

[0071] <2. Structure of stacked body, word line, and pillar>

[0072] Next, the configurations of the stacked body 50 , the word lines WL, and the pillars 30 according to the present embodiment will be described in detail. Figure 2 Observed from the Z direction Figure 1 A region surrounded by a two-dot chain line F2 of the semiconductor memory device 1 shown in FIG. 1 is a cross-sectional view including the word line WL. Figure 3 yes Figure 2 0 is a cross-sectional view of the semiconductor memory device 1 taken along the line F3 - F3 shown in FIG. Figure 4 Yes means Figure 2 The enlarged cross-sectional view of the first floating gate electrode FGA and its vicinity shown in FIG. Figure 2 Hereinafter, for convenience of explanation, only four word lines WL arranged in the Z direction are shown.

[0073] <2.1 Floating Gate Electrode>

[0074] First, the plurality of floating gate electrodes FG will be described.

[0075] like Figure 2 and Figure 3 As shown, the plurality of first floating gate electrodes FGA are respectively located between the first word line WLA and the pillar 30. On the other hand, the plurality of second floating gate electrodes FGB are respectively located between the second word line WLB and the pillar 30. In the present embodiment, the plurality of floating gate electrodes FG are respectively formed into a trapezoidal shape with arc ends in the -Y direction and the +Y direction.

[0076] The first floating gate electrodes FGA adjacent in the Z direction among the plurality of first floating gate electrodes FGA are arranged in such a manner that a first gap AG1 is formed between these first floating gate electrodes FGA. In addition, the second floating gate electrodes FGB adjacent in the Z direction among the plurality of second floating gate electrodes FGB are arranged in such a manner that a second gap AG2 is formed between these second floating gate electrodes FGB. This configuration can also be expressed as follows. That is, the first gap AG1 is provided between the first floating gate electrodes FGA adjacent in the Z direction. In addition, the second gap AG2 is provided between the second floating gate electrodes FGB adjacent in the Z direction. By providing the first gap AG1 and the second gap AG2, a portion of the channel portion 31 (specifically, the first impurity diffusion region IA and the second impurity diffusion region IB) is exposed. However, when the first tunnel insulating film 40A and the second tunnel insulating film 40B extend continuously in the Z direction so as to span the entire length (height) of the pillar 30 in the Z direction, the first tunnel insulating film 40A and the second tunnel insulating film 40B are exposed through the first gap AG1 and the second gap AG2.

[0077] The first gap AG1 and the second gap AG2 may be provided between the first floating gate electrodes FGA adjacent in the Z direction or the second floating gate electrodes FGB adjacent in the Z direction, and the length of each of the first gap AG1 and the second gap AG2 in the X direction is not particularly limited. For example, the first gap AG1 and the second gap AG2 may also extend to the position of the word line WL along the X direction. In other words, the word lines WL adjacent in the Z direction may also be provided in such a manner that the first gap AG1 or the second gap AG2 is formed between these word lines WL.

[0078] <2.2 word line>

[0079] Next, the word line WL will be described.

[0080] The word line WL includes, for example, a barrier metal film 91 and a conductive component 92. The barrier metal film 91 is provided on the surface of the word line WL. The barrier metal film 91 is a film that suppresses diffusion of the material of the conductive component 92. The barrier metal film 91 includes, for example, titanium nitride (TiN). The conductive component 92 is provided inside the barrier metal film 91. The conductive component 92 includes, for example, tungsten.

[0081] <2.3 Barrier insulating film>

[0082] Next, the block insulating film 60 will be described.

[0083] The block insulating film 60 is provided, for example, between the first floating gate electrode FGA and the first word line WLA and between the second floating gate electrode FGB and the second word line WLB. The block insulating film 60 includes, for example, a first block insulating film 61 , a second block insulating film 62 , and a third block insulating film 63 .

[0084] The first blocking insulating film 61 is closest to the floating gate electrode FG among the first blocking insulating film 61, the second blocking insulating film 62, and the third blocking insulating film 63. The first blocking insulating film 61, for example, covers the side surface, the upper surface, and the lower surface of the floating gate electrode FG. The first blocking insulating film 61, for example, includes a High-k material such as silicon nitride (SiN) and hafnium oxide (HfO). In addition, the first blocking insulating film 61 may also be formed of a material including ruthenium (Ru) or aluminum (Al), titanium (Ti), zirconium (Zr), or silicon (Si).

[0085] The second blocking insulating film 62 is provided on the side opposite to the floating gate electrode FG with respect to the first blocking insulating film 61. The second blocking insulating film 62 covers the side surface, the upper surface, and the lower surface of the floating gate electrode FG, for example, via the first blocking insulating film 61. Alternatively, instead of this configuration, the second blocking insulating film 62 may cover only the side surface of the floating gate electrode FG and be provided along the surface of the word line WL. The second blocking insulating film 62 includes, for example, silicon oxide.

[0086] The third blocking insulating film 63 is provided on the side opposite to the floating gate electrode FG with respect to the first blocking insulating film 61 and the second blocking insulating film 62. The third blocking insulating film 63, for example, covers the side surface, the upper surface, and the lower surface of the floating gate electrode FG via the first blocking insulating film 61 and the second blocking insulating film 62. Alternatively, instead of this configuration, the third blocking insulating film 63 may only cover the side surface of the floating gate electrode FG and be provided along the surface of the word line WL. The third blocking insulating film 63 may be formed of a material having a relatively high dielectric constant, for example, a High-k film including an oxide film of aluminum (Al), hafnium (Hf), and zirconium (Zr). Alternatively, the third blocking insulating film 63 may be formed of silicon nitride.

[0087] <2.4 Tunnel insulation film>

[0088] Next, the tunnel insulating film 40 will be described.

[0089] The plurality of first tunnel insulating films 40A are respectively located between the first floating gate electrode FGA and the pillar 30. The plurality of second tunnel insulating films 40B are respectively located between the second floating gate electrode FGB and the pillar 30. In the present embodiment, the first floating gate electrode FGA, the blocking insulating film 60 and the first tunnel insulating film 40A form a "first memory film (first memory cell) MCA". On the other hand, the second floating gate electrode FGB, the blocking insulating film 60 and the second tunnel insulating film 40B form a "second memory film (second memory cell) MCB".

[0090] The plurality of first tunnel insulating films 40A are intermittently provided along the side surface in the -X direction of each pillar 30. The plurality of second tunnel insulating films 40B are intermittently provided along the side surface in the +X direction of each pillar 30. In addition, the plurality of first tunnel insulating films 40A and the plurality of second tunnel insulating films 40B may extend continuously in the Z direction, for example, so as to span the entire length (entire height) of the pillar 30 in the Z direction.

[0091] <2.5 columns>

[0092] Next, the column 30 will be described.

[0093] The pillar 30 is provided between the first word line WLA and the second word line WLB in the X direction. The pillar 30 includes an insulating core 32 and a channel portion 31 in order from the inner peripheral side. The channel portion 31 includes a first impurity diffusion region IA and a second impurity diffusion region IB in which impurity elements are diffused.

[0094] The insulating core 32 extends in the Z direction and has a columnar shape. The insulating core 32 is provided at a position closer to the center side of the column 30 than the channel portion 31 in the X direction and the Y direction. For example, the insulating film 32 is provided on the inner peripheral surface of the channel portion 31. The insulating core 32 includes, for example, silicon oxide. When viewed from the Z direction, the insulating core 32 is provided at the central portion including the central axis of the column 30.

[0095] The channel portion 31 is located at the outermost periphery of the column 30. The channel portion 31 extends in the Z direction in a manner spanning the entire length (full height) of the column 30 in the Z direction, and is formed, for example, in a ring shape. The channel portion 31 covers the outer side surface (peripheral surface) of the insulating core 32. The channel portion 31 includes, for example, silicon. Silicon is, for example, polycrystalline silicon obtained by crystallizing amorphous silicon. The lower end of the channel portion 31 passes through the upper insulating film 25 of the lower structure 20 and is connected to the source line SL. On the other hand, the upper end of the channel portion 31 is connected to the bit line BL via the contact 81. The channel portion 31 has a function as a flow path (so-called "channel") for carriers between the source line SL and the bit line BL when electrons are injected into the floating gate electrode FG and when electrons injected into the floating gate electrode FG are extracted from the floating gate electrode FG. The channel portion 31 may also be referred to as a "semiconductor layer" or a "silicon layer."

[0096] The channel portion 31 includes a first channel portion 31A located on the -X direction side of the channel portion 31 and a second channel portion 31B located on the +X direction side of the channel portion 31. The first channel portion 31A is provided between the first word line WLA and the second word line WLB and extends in the Z direction. The first channel portion 31A faces the first source side selection gate electrode 51A, the plurality of first floating gate electrodes FGA, and the first drain side selection gate electrode 52A via the first tunnel insulating film 40A. The second channel portion 31B is provided between the first word line WLA and the second word line WLB, is adjacent to the first channel portion 31A in the X direction, and extends in the Z direction. The second channel portion 31B faces the second source side selection gate electrode 51B, the plurality of second floating gate electrodes FGB, and the second drain side selection gate electrode 52B via the second tunnel insulating film 40B. In the present embodiment, the channel portion 31 is formed in a ring shape.

[0097] The first channel portion 31A includes a first impurity diffusion region IA in which an impurity element is diffused. The first impurity diffusion region IA is provided in the first channel portion 31A, at least between the first floating gate electrodes FGA adjacent in the Z direction. The first impurity diffusion region IA is formed by doping at least a portion of the channel portion 31 with impurities. Therefore, the first impurity diffusion region IA is exposed on the outer side surface of the first channel portion 31A. The first impurity diffusion region IA is a region in which an n-type impurity element (for example, phosphorus (P), arsenic (As), antimony (Sb), etc.) is doped from the first gap AG1 side into the first channel portion 31A. The first impurity diffusion region IA may contain two or more elements.

[0098] The second channel portion 31B includes a second impurity diffusion region IB in which impurity elements are diffused. The second impurity diffusion region IB is provided in the second channel portion 31B, at least between the second floating gate electrodes FGB adjacent in the Z direction. The second impurity diffusion region IB is formed by doping at least a portion of the channel portion 31 with impurities. Therefore, the second impurity diffusion region IB is exposed on the outer side surface of the second channel portion 31B. The second impurity diffusion region IB is a region in which n-type impurity elements (for example, phosphorus (P), arsenic (As), antimony (Sb), etc.) are doped from the second gap AG2 side into the first channel portion 31B. The second impurity diffusion region IB may contain two or more elements. The elements contained in the first impurity diffusion region IA and the elements contained in the second impurity diffusion region IB may be different or the same.

[0099] The length of the first impurity diffusion region IA in the Z direction may be longer than the distance between the first memory cells MCA adjacent in the Z direction, that is, the distance between the blocking insulating films 60 adjacent in the Z direction. Thus, the reduction of the cell current can be further suppressed. The length of the first impurity diffusion region IA in the Z direction may also be longer than the distance between the first floating gate electrodes FGA adjacent in the Z direction. Thus, the reduction of the cell current can be further suppressed.

[0100] The length of the second impurity diffusion region IB in the Z direction may be longer than the distance between the second memory cells MCB adjacent in the Z direction, that is, the distance between the blocking insulating films 60 adjacent in the Z direction. Thus, the reduction of the cell current can be further suppressed. The length of the second impurity diffusion region IB in the Z direction may also be longer than the distance between the second floating gate electrodes FGB adjacent in the Z direction. Thus, the reduction of the cell current can be further suppressed.

[0101] The thickness of the first impurity diffusion region IA and the second impurity diffusion region IG in the X direction may be respectively at least 1 / 2 of the thickness of the channel portion 31 in the X direction. From the viewpoint of suppressing the reduction of the cell current, the thickness of the first impurity diffusion region and the second impurity diffusion region in the X direction may be the same as the thickness of the channel portion 31 in the X direction.

[0102] In addition, the planar layout and cross-sectional layout of the semiconductor memory device 1 are not limited to Figure 1 to Figure 3 The layout shown may be other layouts. For example, the number and arrangement of the pillars 30, the number of word lines WL, etc. may be changed as appropriate.

[0103] <3. Function>

[0104] As described above, in the semiconductor memory device 1 of the present embodiment, the first floating gate electrodes FGA adjacent in the Z direction are arranged in a manner to form the first gap AG1. Similarly, the second floating gate electrodes FGB adjacent in the Z direction are arranged in a manner to form the second gap AG2. As a result, compared with the conventional case where an insulator such as silicon oxide is provided between the first floating gate electrodes FGA or the second floating gate electrodes FGB, the interference of the electric field between the memory cells (for example, between the adjacent first memory cells MCA) can be reduced. However, if a gap is provided only between the floating gate electrodes FG, there is a concern that the cell current will decrease with the weakening of the edge electric field effect compared with the conventional case where an insulator is provided. Therefore, in the present embodiment, by forming the first impurity diffusion region IA and the second impurity diffusion region IG inside the channel portion 31 located between the floating gate electrodes FG, the reduction of the cell current can be suppressed.

[0105] <4. Method for manufacturing semiconductor memory device>

[0106] Next, an example of a method for manufacturing semiconductor memory device 1 will be described. Figures 5 to 29 It is a diagram showing a method of manufacturing the semiconductor memory device 1 .

[0107] First, if Figure 5 As shown in FIG. 1 , a lower insulating film 21, a conductive layer 22, a wiring layer 23, and a conductive layer 24 are formed on a silicon substrate 10. Then, as shown in FIG. Figure 6 As shown, for example, dry etching is performed to selectively remove the conductive layer 22, the wiring layer 23, and the conductive layer 24. Thus, the source line SL is formed.

[0108] Then, if Figure 7 As shown, an insulating member 26 and an upper insulating film 25 are formed on the lower insulating film 21 and the source line SL. The insulating member 26 is made of, for example, silicon oxide. The upper insulating film 25 is made of, for example, silicon oxide.

[0109] Then, if Figure 8 As shown, an insulating film 57 including, for example, silicon oxide is formed on the upper insulating film 25. Then, on the insulating film 57, a first filling film 95 including silicon nitride and a second filling film 54 including polysilicon are alternately stacked by, for example, CVD (Chemical Vapor Deposition) to form a stacked intermediate 50A.

[0110] Then, if Fig. 9 As shown, on the stacked intermediate 50A, for example, silicon oxide (SiO 2 ) to form a mask 101. Then, on the mask 101, a pattern film 102 containing, for example, carbon (C), an anti-reflective film ARC (Anti Reflective Coating) 103, and a resist film 104 are formed.

[0111] Then, if Fig.10 As shown, the resist film 104 is exposed and developed to form a resist pattern 104a. Then, etching is performed to form an anti-reflection film 103a and a pattern film 102a. Then, the mask 101 is patterned to form a mask 101a. Thus, the mask 101a has an opening 101b extending in the Y direction. Then, using the mask 101a as a mask, for example, wet etching is performed to penetrate the stacked intermediate 50A in the Z direction, thereby forming a memory cell trench MT reaching the upper insulating film 25.

[0112] Then, if Fig.11 As shown in FIG. 1 , an insulating material such as silicon oxide is deposited in the memory cell trench MT and on the resist pattern 104a. Thus, an insulating film 55A to be the insulating member 55 is formed in the memory cell trench MT.

[0113] Then, if Fig.12 As shown in FIG. 1 , the unnecessary portion of the insulating film 55A located above the resist pattern 104a is removed by, for example, etching back. Then, the resist pattern 104a, the antireflection film 103a, and the pattern film 102a are removed.

[0114] Then, if Fig.13 As shown, for example, a hard mask MS is provided on the mask 101a. The hard mask MS has an opening MSa at a position corresponding to a memory hole MH described below.

[0115] Then, if Fig.14 As shown, the hard mask MS is used as a mask, and wet etching is performed, for example, to remove the portion of the stacked intermediate body 50A exposed in the opening MSa of the hard mask MS. Here, in this embodiment, an etchant is used that can leave the mask 101a under the hard mask MS without removing it. Therefore, the insulating film 57, the first filling film 95, and the second filling film 54 are not removed, and only the useless portion of the insulating film 55A is removed.

[0116] Therefore, if Fig.15 As shown in FIG. 5 , a memory hole MH is formed that penetrates the insulating film 55A in the Z direction, and the remaining portion of the insulating film 55A becomes the insulating member 55. The memory hole MH is provided between the first wiring area A1 and the second wiring area A2 in the stacked intermediate 50A. The "wiring area" may be an area where wiring has been formed, or an area where wiring is formed in a subsequent step. In the present embodiment, the first wiring area A1 is an area where the first word line WLA is formed in a subsequent step, and the second wiring area A2 is an area where the second word line WLB is formed in a subsequent step.

[0117] Then, if Fig.16 As shown, a portion of the upper insulating film 25 exposed in the memory hole MH is removed by etching, for example, to expose the source line SL.

[0118] Then, if Fig.17 As shown, wet etching is performed through the memory hole MH using, for example, hot phosphoric acid (H3PO4) as an etchant, which is a chemical solution that dissolves silicon nitride. As a result, a portion of the first filling film 95 on the memory hole MH side is removed, forming a recessed portion 111 on the side of the memory hole MH.

[0119] Then, if Fig.18 As shown, on the inner surface of the memory hole MH and the inner surface of the recessed portion 111 , for example, an insulating material is deposited to form a blocking insulating film 60 .

[0120] Then, if Fig.19As shown in FIG. 1 , for example, polysilicon is deposited on the inner peripheral surface of the stopper insulating film 60 to form a floating gate electrode film 112. At this time, the polysilicon is provided so as to fill the recess 111.

[0121] Then, if Fig. 20 As shown, unnecessary insulating materials and polysilicon are removed from the inner surface of the memory hole MH. Thus, unnecessary portions of the floating gate electrode film 112 are removed, and the floating gate electrode FG is formed.

[0122] Then, if Fig.21 As shown, on the inner surface of the memory hole MH, for example, silicon oxide is deposited to form a tunnel insulating film 40 .

[0123] Then, if Fig. 22 As shown, etching is performed, for example, to remove the bottom of the tunnel insulating film 40 so that the source line SL is exposed in the memory hole MH.

[0124] Then, if Fig.23 As shown, a semiconductor material is stacked on the inner peripheral surface of the tunnel insulating film 40 to form the channel portion 31 of the pillar 30. The channel portion 31 may be annealed at this point to crystallize the amorphous silicon, or may be annealed at a later point in time.

[0125] Then, if Fig.24 As shown, silicon oxide is deposited in the memory hole MH, thereby forming the insulating core 32 embedded in the memory hole MH. Then, etching is performed, for example, to expose the upper surfaces of the mask 101a, the channel portion 31, the tunnel insulating film 40, and the insulating core 32.

[0126] Then, if Fig.25 As shown in FIG. 1 , a slit SL is formed which penetrates the laminated intermediate body 50A in the Z direction.

[0127] Then, if Fig.26 As shown, the first filling film 95 is replaced with the word line WL. For example, first, the first filling film 95 is removed by wet etching through the slit SL. The wet etching uses an etchant that can etch silicon nitride faster than silicon oxide and polysilicon. Thereafter, a plurality of word lines WL, source side selection gate lines SGS, and drain side selection gate lines SGD are formed by arranging a barrier metal film 91 and a conductive component 92 in the space where the first filling film 95 is removed. Then, the slit SL is filled with an insulating material to form an insulating component 56A.

[0128] Then, if Fig. 27 As shown in FIG. 1 , a slit SLL is formed to penetrate the laminated intermediate body 50A in the Z direction. The slit SLL may be formed at a position such that Fig.25The formation positions of the slits SL shown are substantially the same. Then, the second filling film 54 is removed by wet etching through the slits SLL. The wet etching uses an etchant that can etch polysilicon faster than silicon oxide. By this wet etching, the first gap AG1 and the second gap AG2 are formed between the floating gate electrodes FG adjacent in the Z direction, and a portion of the tunnel insulating film 40 is exposed.

[0129] Then, if Fig.28 As shown, the exposed tunnel insulating film 40 is removed to expose a portion of the channel 30. Then, n-type impurity gas is used to dope the surface of the exposed channel 30 with n-type impurities through the slit SLL, thereby forming a first impurity diffusion region IA and a second impurity diffusion region IB having a high impurity concentration. Thereafter, the first impurity diffusion region IA and the second impurity diffusion region IB are activated by performing an annealing process on the stacked intermediate 50A.

[0130] Then, if Fig.29 As shown in FIG. 1 , the slit SLL is filled with an insulating material to form the insulating member 56. Alternatively, a conductor made of tungsten, for example, may be provided in the insulating member 56.

[0131] Through the steps described above, the stacked intermediate body 50A becomes the stacked body 50 .

[0132] Then, the bit line BL, a plurality of wirings L1, L2, L3, and a contact 80 are formed by a known method.

[0133] Thus, the semiconductor memory device 1 is formed. The manufacturing steps shown here are just examples, and other steps may be inserted between the steps.

[0134] <5. Variations of the embodiment>

[0135] Next, modified examples of the embodiment will be described.

[0136] Fig.30 1 is a cross-sectional view showing a semiconductor memory device 1A according to the present variation.

[0137] This variation is different from the present embodiment in that a third insulating film 85 is provided on the surface of each of the first word line WLA, the second word line WLB, the first floating gate electrode FGA, and the second floating gate electrode FGB in the Z direction. In addition, the third insulating film 85 is provided in a manner to cover the surface of each of the first impurity diffusion region IA and the second impurity diffusion region IB on the first gap GA1 side and the surface of the second gap GA2 side.

[0138] The configuration of this variation example other than the contents described below is the same as that of the present embodiment.

[0139] In this way, by providing the third insulating film 85 on the surfaces of the first word line WLA, the second word line WLB, the first floating gate electrode FGA, the second floating gate electrode FGB, and the exposed surfaces of the first impurity diffusion region IA and the second impurity diffusion region IB, the overall strength of the semiconductor memory device 1A can be ensured, and the exposed surfaces of the first impurity diffusion region IA and the second impurity diffusion region IB can be protected. As a result, the electrical characteristics of the semiconductor memory device 1A can be stabilized.

[0140] Several embodiments have been described above, but the embodiments are not limited to the examples described above. For example, the memory film may be a ferroelectric film included in a FeFET (Ferroelectric FET) memory that stores data using a polarization direction. The ferroelectric film is formed of, for example, hafnium oxide.

[0141] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0142] [Explanation of symbols]

[0143] 1: Semiconductor storage device

[0144] 10: Silicon substrate

[0145] 30: column

[0146] 31: Channel Department

[0147] 40: Tunnel insulation film

[0148] 40A: 1st tunnel insulating film

[0149] 40B: Second tunnel insulating film

[0150] 60: Barrier insulation film

[0151] FG: floating gate electrode

[0152] FGA: 1st floating gate electrode

[0153] FGB: Second floating gate electrode

[0154] WL: Word Line

[0155] WLA: Word Line 1

[0156] WLB: Word Line 2

[0157] SGS: Source side select gate line

[0158] SGD: drain side select gate line

[0159] IA: 1st impurity diffusion area

[0160] IB: Second impurity diffusion region.

Claims

1. A semiconductor storage device comprising: substrate; A first wiring extending in a first direction; a second wiring line adjacent to the first wiring line in a second direction intersecting the first direction and extending in the first direction; a channel portion provided between the first wiring and the second wiring and extending in a third direction intersecting the first direction and the second direction; a first charge storage portion disposed between the first wiring and the channel portion; a second charge storage portion disposed between the second wiring and the channel portion; a first insulating film disposed between the first charge storage portion and the channel portion; and a second insulating film disposed between the second charge storage portion and the channel portion; and The first charge storage portions adjacent to each other in the third direction are arranged so as to form a first gap between the first charge storage portions adjacent to each other in the third direction. The second charge storage portions adjacent to each other in the third direction are arranged so as to form a second gap between the second charge storage portions adjacent to each other in the third direction. A first impurity diffusion region in which an impurity element is diffused is provided inside the channel portion between the first charge storage portions adjacent to each other in the third direction. A second impurity diffusion region in which the impurity element is diffused is provided inside the channel portion between the second charge accumulation portions adjacent to each other in the third direction. 2 . The semiconductor memory device according to claim 1 , wherein the first impurity diffusion region and the second impurity diffusion region are exposed at a side surface of the channel portion. 3 . The semiconductor memory device according to claim 1 , wherein the impurity element is of n-type.

4. The semiconductor storage device according to claim 1, wherein the lengths of the first impurity diffusion region and the second impurity diffusion region in the third direction are respectively longer than the distance between the first charge storage units adjacent to each other in the third direction and the distance between the second charge storage units adjacent to each other in the third direction. 5 . The semiconductor memory device according to claim 1 , wherein the thickness of each of the first impurity diffusion region and the second impurity diffusion region in the second direction is equal to or greater than 1 / 2 of the thickness of the channel portion. 6 . The semiconductor memory device according to claim 1 , wherein the first insulating film and the second insulating film are provided intermittently along the side of the channel portion in the third direction.

7. The semiconductor storage device according to claim 1, wherein a third insulating film is provided in a manner to cover the surfaces of the first wiring, the second wiring, the first charge storage unit, and the second charge storage unit in the third direction, and the surfaces of the first impurity diffusion region and the second impurity diffusion region on the side of the gap.

Images