Multi-channel electroencephalogram signal acquisition system based on auditory evoked potential

Abstract

The invention discloses a multichannel electroencephalogram signal acquisition system based on auditory evoked potential. A control circuit controls to send a trigger signal to an audio generation circuit after receiving an electroencephalogram signal acquisition instruction through a communication circuit, and the audio generation circuit generates an audio signal based on a sound source obtained through a sound source interface; the audio drive circuit generates an audio drive signal containing an audio signal based on the audio signal, and the control circuit controls the audio drive circuit to output the audio drive signal with a set duration through the earphone interface, so that the earphone outputs sound stimulation to act on a collector; the audio driving circuit generates a synchronizing signal based on an audio driving signal and transmits the synchronizing signal to the signal acquisition circuit; the signal acquisition circuit acquires multi-channel electroencephalogram signals of the plurality of electroencephalogram electrodes through a signal acquisition interface and transmits the multi-channel electroencephalogram signals to the control circuit; the control circuit stores the multi-channel electroencephalogram signals in the storage circuit and uploads the multi-channel electroencephalogram signals to an upper computer through the communication circuit; the control circuit controls the system operation indicating circuit to be lightened when the system operates normally.

Description

Technical Field

[0001] The present invention relates to the technical field of electroencephalogram (EEG) signal acquisition, and in particular to a multi-channel EEG signal acquisition system based on auditory evoked potentials. Background Art

[0002] The EEG cap is worn on the head of the collector to detect the EEG signal of the collector. The EEG cap has the characteristics of comfortable wearing, good contact, and normal signal collection. The existing EEG cap for collecting EEG signals, the earphones for emitting sound stimulation, the EEG collection device containing hardware such as EEG collection circuits, and the sound stimulation device containing sound stimulation generation circuits are generally designed separately, occupying a large space and being scattered and messy. For example, the invention patent with application number CN2 01510038162.9 and the name of a portable EEG headset discloses that the EEG headset is provided with electrodes, earphones and other components. Although this existing patent integrates both the EEG electrodes and earphones on the EEG headset, it does not integrate the EEG collection device and the sound stimulation device on the EEG headset. Therefore, the present invention designs a multi-channel EEG signal collection system based on auditory evoked potentials, which integrates both the EEG collection device and the sound stimulation device on the EEG cap, which is conducive to the generation of sound stimulation and the collection of signals, and occupies a small space and is neat and orderly. Summary of the invention

[0003] In view of the problems and shortcomings of the prior art, the present invention provides a multi-channel electroencephalogram signal acquisition system based on auditory evoked potentials.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present invention provides a multi-channel electroencephalogram (EEG) signal acquisition system based on auditory evoked potentials, which is characterized in that it comprises an electroencephalogram (EEG) cap and earphones for a collector to wear, and an EEG acquisition device, wherein a plurality of EEG electrodes are mounted on the EEG cap, and the EEG acquisition device is mounted on the EEG cap, and the EEG acquisition device comprises a housing, wherein a power supply interface, a power supply circuit, a sound source interface, an audio generation circuit, an audio driving circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, a system operation indication circuit, and a communication circuit are integrated in the housing;

[0006] The power supply circuit is used to connect to an external power supply through a power supply interface, and convert the external power supply into a power supply voltage to power the control circuit, the audio generation circuit, the audio drive circuit, the signal acquisition circuit, the storage circuit, the system operation indication circuit and the communication circuit;

[0007] The control circuit is connected to the host computer through the communication circuit, the sound source interface, the audio generation circuit and the control circuit are electrically connected in sequence, the control circuit is used to control the sending of a trigger signal to the audio generation circuit after receiving an EEG signal acquisition instruction through the communication circuit, and the audio generation circuit is used to generate an audio signal based on the sound source obtained through the sound source interface after receiving the trigger signal;

[0008] The audio generation circuit is electrically connected to the audio driving circuit, the headphone interface, the audio driving circuit and the control circuit are electrically connected in sequence, the audio driving circuit is used to receive an audio signal and generate an audio driving signal containing the audio signal based on the audio signal, and the control circuit is used to control the audio driving circuit to output an audio driving signal of a set duration through the headphone interface, so that the headphone outputs a sound stimulus of the set duration to act on the collector;

[0009] The audio driving circuit is electrically connected to the signal acquisition circuit, and the EEG electrodes, the signal acquisition interface, the signal acquisition circuit and the control circuit are electrically connected in sequence. The audio driving circuit is used to generate a synchronization signal based on the audio driving signal and transmit it to the signal acquisition circuit. The signal acquisition circuit is used to collect multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface and transmit the multi-channel EEG signals to the control circuit.

[0010] The storage circuit and the communication circuit are both electrically connected to the control circuit, and the control circuit is used to store the multi-channel EEG signals of the collector in the storage circuit and upload them to the host computer through the communication circuit;

[0011] The system operation indication circuit is electrically connected to the control circuit, and the control circuit is used to control the system operation indication circuit to light up when the system operates normally.

[0012] The positive and progressive effects of the present invention are:

[0013] The present invention integrates the EEG acquisition component and the sound stimulation component to form an EEG acquisition device, and installs the EEG stimulation device on an EEG cap, which is beneficial to the generation of sound stimulation and the acquisition of signals, and occupies a small space and is neat and orderly. In addition, the present invention also optimizes the design of each circuit in the EEG acquisition device, and can more accurately acquire multi-channel EEG signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of a multi-channel EEG signal acquisition system according to a preferred embodiment of the present invention.

[0015] Figure 2-4 Schematic diagram of the structure of the EEG cap according to a preferred embodiment of the present invention.

[0016] Figure 5FIG. 4 is a schematic diagram of a power supply circuit according to a preferred embodiment of the present invention.

[0017] Figure 6 This is a circuit diagram of the main power switch of a preferred embodiment of the present invention.

[0018] Figure 7 FIG. 4 is a first DC-DC circuit diagram of a preferred embodiment of the present invention.

[0019] Figure 8 This is a diagram of a first protection circuit and a communication circuit according to a preferred embodiment of the present invention.

[0020] Fig. 9 This is a diagram of a first voltage stabilizing circuit, a first switch circuit and an audio driving circuit according to a preferred embodiment of the present invention.

[0021] Fig.10 This is a diagram of a second switch circuit and an audio generation circuit according to a preferred embodiment of the present invention.

[0022] Fig.11 FIG. 4 is a diagram of a third switch circuit and a storage circuit according to a preferred embodiment of the present invention.

[0023] Fig.12 This is a diagram of a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage stabilizing circuit and a third voltage stabilizing circuit according to a preferred embodiment of the present invention.

[0024] Fig.13 FIG. 4 is a control circuit diagram of a preferred embodiment of the present invention.

[0025] Fig.14 This is a signal acquisition interface and EEG acquisition protection circuit diagram of a preferred embodiment of the present invention.

[0026] Fig.15 The signal acquisition circuit diagram of the preferred embodiment of the present invention.

[0027] Fig.16 1 is a system operation indication circuit diagram of a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] like Figure 1-4As shown, this embodiment provides a multi-channel EEG signal acquisition system based on auditory evoked potentials, which includes an EEG cap 100 and headphones 200 for the collector to wear, and an EEG acquisition device 300, the EEG cap 100 is equipped with multiple EEG electrodes 101, the EEG acquisition device 300 is installed on the EEG cap 100, and the EEG acquisition device 300 includes a shell 301, and the shell 301 integrates a power supply interface 302, a power supply circuit 303, a sound source interface 304, an audio generation circuit 305, an audio driving circuit 306, an earphone interface 307, a signal acquisition interface 308, a signal acquisition circuit 309, a control circuit 310, a storage circuit 311, a system operation indication circuit 312 and a communication circuit 313.

[0030] The power supply circuit 303 is used to connect to an external power supply through the power supply interface 302, and convert the external power supply into a power supply voltage to power the control circuit 310, the audio generation circuit 305, the audio drive circuit 306, the signal acquisition circuit 309, the storage circuit 311, the system operation indication circuit 312 and the communication circuit 313.

[0031] The control circuit 310 is connected to the host computer through the communication circuit 313, and the sound source interface 304, the audio generation circuit 305 and the control circuit 310 are electrically connected in sequence. The control circuit 310 is used to control the issuance of a trigger signal to the audio generation circuit 305 after receiving an EEG signal acquisition instruction through the communication circuit 313. The audio generation circuit 305 is used to generate an audio signal based on the sound source obtained through the sound source interface 304 after receiving the trigger signal.

[0032] The audio generating circuit 305 is electrically connected to the audio driving circuit 306, and the headphone interface 307, the audio driving circuit 306 and the control circuit 310 are electrically connected in sequence. The audio driving circuit 306 is used to receive an audio signal and generate an audio driving signal containing the audio signal based on the audio signal. The control circuit 310 is used to control the audio driving circuit 306 to output an audio driving signal of a set duration through the headphone interface 307, so that the headphone 200 outputs a sound stimulus of a set duration to act on the collector, thereby realizing auditory evoked potentials.

[0033] The audio driving circuit 306 is electrically connected to the signal acquisition circuit 309, and the EEG electrodes 101, the signal acquisition interface 308, the signal acquisition circuit 309 and the control circuit 310 are electrically connected in sequence. The audio driving circuit 306 is used to generate a synchronization signal based on the audio driving signal and transmit it to the signal acquisition circuit 309. The signal acquisition circuit 309 is used to collect multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface 308 and transmit the multi-channel EEG signals to the control circuit 310.

[0034] The storage circuit 311 and the communication circuit 313 are both electrically connected to the control circuit 310 . The control circuit 310 is used to store the multi-channel EEG signals of the collector in the storage circuit 311 and upload them to the host computer through the communication circuit 313 .

[0035] The system operation indication circuit 312 is electrically connected to the control circuit 310 , and the control circuit 310 is used to control the system operation indication circuit 312 to light up when the system operates normally.

[0036] Among them, Figure 5 As shown, the power supply circuit 303 includes a main power supply switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage stabilizing circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage stabilizing circuit and a third voltage stabilizing circuit.

[0037] The input end of the main power switch circuit is electrically connected to the power supply interface 302 (such as a Type-C interface), and the output end of the main power switch circuit is electrically connected to the control circuit 310 through the first DC-DC circuit. The main power switch circuit is used to control the circuit 310 to turn on and output the first power supply voltage VCC_5V based on the input voltage adjustment. The first DC-DC circuit is used to convert the first power supply voltage into a second power supply voltage VCC_3.3V and provide the second power supply voltage VCC_3.3V to the control circuit 310.

[0038] The output end of the power main switch circuit is electrically connected to the communication circuit 313 through the first protection circuit to provide VBUS voltage for the communication circuit 313 , and the output end of the first DC-DC circuit is electrically connected to the communication circuit 313 to provide a second power supply voltage VCC_3.3V for the communication circuit 313 .

[0039] The output end of the main power switch circuit is electrically connected to the audio driving circuit 306 through the first voltage stabilizing circuit, the first voltage stabilizing circuit is used to stabilize the first power supply voltage VCC_5V into a regulated power supply voltage VCC1_3V3A and provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driving circuit 306, and the output end of the first DC-DC circuit is electrically connected to the audio driving circuit 306 through the first switching circuit to provide a 3.3V power supply voltage VCC1_3V3 for the audio driving circuit 306.

[0040] The output end of the first DC-DC circuit is electrically connected to the audio generation circuit 305 through the second switch circuit to provide a 3.3V power supply voltage VCC2_3V3 for the audio generation circuit 305 .

[0041] The output end of the first DC-DC circuit is electrically connected to the storage circuit 311 through the third switch circuit to provide a 3.3V power supply voltage VCC3_3V3 for the storage circuit 311 .

[0042] The output end of the first DC-DC circuit is electrically connected to the input end of the fourth switch circuit, and the output end of the fourth switch circuit is electrically connected to the signal acquisition circuit 309 through the filter circuit to provide the signal acquisition circuit 309 with a filtered voltage DVDD_33, and the output end of the fourth switch circuit is also electrically connected to the signal acquisition circuit 309 through the second DC-DC circuit and the second voltage stabilizing circuit, and is also electrically connected to the signal acquisition circuit 309 through the third voltage stabilizing circuit, so as to provide the signal acquisition circuit with a bipolar power supply voltage (AVSS and AVDD, respectively).

[0043] Among them, Figure 6 As shown, the main power switch circuit includes: a main switch K3 (model K8-5854P-L1) and a power switch chip U4 (model TPS2553DRVR). The switch end of the main switch K3 is embedded in the housing 301. The IN pin (pin 6) of the power switch chip U4 is electrically connected to the power supply interface 302, and is also electrically connected to the pin 2 of the main switch K3, and is also grounded through the capacitor C30. The EN pin (pin 4) of the power switch chip U4 is electrically connected to the pin 3 of the main switch K3 through the resistor R14, and is also grounded through the resistor R77 and the capacitor C32. The GND pin (pin 5) and EP pin (pin 7) of the power switch chip U4 are both grounded. (Pin 3) is electrically connected to the power supply interface 302 through the power status indicator light D2 and the resistor R17, the ILIM pin (pin 2) is grounded through the resistor R15, and the OUT pin (pin 1) of the power switch chip U4 is used to output the first power supply voltage VCC_5V and is also grounded through the capacitor C31.

[0044] like Figure 7As shown, the first DC-DC circuit includes: a power management chip U1 (TPS62140RGTR), two PVIN pins (pins 11 and 12), an AVIN pin (pin 10) and an EN pin (pin 13) of the power management chip U1 are electrically connected to the OUT pin (pin 1) of the power switch chip U4 to access the first power supply voltage VCC_5V, and are also grounded through series resistors R9 and resistors R12, and are also grounded through capacitors C105, C24, and C23; the FSW pin (pin 7) of the power management chip U1 is grounded through resistor R12, the DEF pin (pin 8) is grounded through resistor R11, and the SS / TR pin (pin 9) is grounded through capacitor C2 9 is grounded; the two PGND pins (pin 15 and pin 16), AGND pin (pin 6) and EP pin (pin 17) of the power management chip U1 are all grounded; the FB pin (pin 5) of the power management chip U1 is grounded through the resistor R13, and the VOS pin (pin 14) is grounded through the series resistor R10 and the resistor R13; the three SW pins (pin 1, pin 2 and pin 3) of the power management chip U1 output the second power supply voltage VCC_3.3V through the series inductor L1 and the inductor L8, the inductor L1 and the inductor L8 are grounded through the capacitor C25, the capacitor C26, the capacitor C27 and the capacitor C28 respectively, and the end of the inductor L8 away from the inductor L1 is grounded through the capacitor C108 and the capacitor C107 respectively.

[0045] like Figure 8 As shown, the first protection circuit includes: a resistor R20 and a diode D5, one end of the resistor R20 is electrically connected to the OUT pin (pin 1) of the power switch chip U4 to access the first power supply voltage VCC_5V, and the other end is electrically connected to the cathode of the diode D5, the anode of the diode D5 is grounded, and the cathode is electrically connected to the communication circuit 313 to provide the VBUS voltage.

[0046] like Fig. 9 As shown, the first voltage stabilizing circuit includes: a linear voltage regulator U8 (model SOT23-5), the VIN pin (pin 1) of the linear voltage regulator U8 is electrically connected to the OUT pin (pin 1) of the power switch chip U4 to access the first power supply voltage VCC_5V, and is also grounded through a capacitor C45 and a capacitor C46; the EN pin (pin 3) of the linear voltage regulator U8 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit, the GND pin (pin 2) is grounded, and the BP pin (pin 4) is grounded through a capacitor C49; the VOUT pin (pin 5) of the linear voltage regulator U8 is electrically connected to the audio driving circuit 306, and is also grounded through a capacitor C47 and a capacitor C48, and is used to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driving circuit 306.

[0047] like Fig. 9 As shown, the first switch circuit includes: a transistor Q3 (model DTC143ZE) and a field effect transistor M2 (model SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio driving circuit 306, is also grounded through the capacitor C39, and is also grounded through the capacitor C40, so as to provide a 3.3V voltage VCC1_3V3 for the audio driving circuit 306.

[0048] like Fig.10 As shown, the second switch circuit includes: a transistor Q1 (model DTC143ZE) and a field effect transistor M1 (model SOT1220), the base of the transistor Q1 is electrically connected to the PA3 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q1 is grounded, the source of the field effect transistor M1 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R6 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C18, the source is also electrically connected to the collector of the transistor Q1 through the resistor R7, the gate of the field effect transistor M1 is electrically connected to the collector of the transistor Q1, the drain of the field effect transistor M1 is electrically connected to the 3V3 pin (pin 1) of the audio generation chip U2 in the audio generation circuit 305, and is also grounded through the capacitor C19 and the capacitor C20, so as to provide a 3.3V voltage VCC2_3V3 for the audio generation circuit 305.

[0049] like Fig.11 As shown, the third switch circuit includes: a transistor Q4 (model DTC143ZE) and a field effect transistor M3 (model SOT1220), the base of the transistor Q4 is electrically connected to the PA7 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q4 is grounded, the source of the field effect transistor M3 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R29 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C50, the source is also electrically connected to the collector of the transistor Q4 through the resistor R30, the gate of the field effect transistor M3 is electrically connected to the collector of the transistor Q4, the drain of the field effect transistor M3 is electrically connected to the storage circuit 311, is also grounded through the capacitor C95, and is also grounded through the capacitor C51, so as to provide a 3.3V voltage VCC3_3V3 for the storage circuit 311.

[0050] like Fig.12As shown, the fourth switch circuit includes: a transistor Q5 (model DTC143ZE) and a field effect transistor M4 (model SOT1220), the base of the transistor Q5 is electrically connected to the PI9 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q5 is grounded, the source of the field effect transistor M4 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R52 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C71, the source is also electrically connected to the collector of the transistor Q5 through the resistor R53, the gate of the field effect transistor M4 is electrically connected to the collector of the transistor Q5, the drain of the field effect transistor M4 is respectively electrically connected to the filter circuit, the second DC-DC circuit and the third voltage stabilizing circuit, and is also grounded through the capacitor C72, so as to provide a 3.3V voltage VCC4_3V3.

[0051] like Fig.12 As shown, the filtering circuit includes: an inductor L2, a capacitor C73, a capacitor C74 and a capacitor C75. One end of the inductor L2 is electrically connected to the drain of the field effect transistor M4, and is also grounded through the capacitor C73 and the capacitor C74. The other end of the inductor L2 is electrically connected to the signal acquisition circuit and is also grounded through the capacitor C75, so as to provide a filtered 3.3V voltage DVDD_33 for the signal acquisition circuit.

[0052] like Fig.12 As shown, the second DC-DC circuit includes: a switching regulator chip U11 (model TPS60403DBVR), the IN pin (pin 2) of the switching regulator chip U11 is electrically connected to the drain of the field effect transistor M4 through the inductor L5, and is also grounded through the series-connected inductor L5 and capacitor C84, is also grounded through capacitor C85, and is also grounded through capacitor C86; the GND pin (pin 4) of the switching regulator chip U11 is grounded, and capacitor C83 is connected between the CFLY- pin (pin 3) and the CFLY+ pin (pin 5); the OUT pin (pin 1) of the switching regulator chip U11 is electrically connected to the second voltage stabilization circuit through the inductor L6, and is also grounded through capacitors C87 and C88 respectively.

[0053] like Fig.12As shown, the second voltage stabilizing circuit includes: a negative linear voltage stabilizing chip U12 (model LT3094EMSE), the IN1 pin (pin 1), IN2 pin (pin 2), EP pin (pin 13), PGFB pin (pin 5) and EN / UV pin (pin 3) of the negative linear voltage stabilizing chip U12 are all electrically connected to the inductor L6, and are also grounded through capacitors C89 and C90 respectively, the ILIM pin (pin 6) of the negative linear voltage stabilizing chip U12 is grounded through a resistor R57, and the GND pin (pin 9 ) is grounded, and the SET pin (pin 8) is grounded through a parallel resistor R56 and a capacitor C94 respectively. The OUTS pin (pin 10), OUT1 pin (pin 11) and OUT2 pin (pin 12) of the negative linear voltage regulator chip U12 are electrically connected to the signal acquisition circuit 309 through the inductor L7, and are also grounded through the inductor L7 and the capacitor C93 in turn, and are also grounded through the capacitor C91 and are also grounded through the capacitor C92, so as to provide the -2.5V voltage AVSS in the bipolar power supply voltage for the signal acquisition circuit.

[0054] like Fig.12 As shown, the third voltage stabilizing circuit includes: a linear voltage stabilizing chip U10 (model GM1200ACPZ), the IN pin (pin 1), IN1 pin (pin 2), PGFB pin (pin 6) and EN / UV pin (pin 3) of the linear voltage stabilizing chip U10 are all electrically connected to the drain of the field effect transistor M4 through the inductor L3, and are also grounded through the inductor L3 and the capacitor C76 in turn, and are also grounded through the capacitors C77 and C78 respectively; the ILIM pin (pin 5) of the linear voltage stabilizing chip U10 is connected to the MOSFET M4 through the resistor R54. The two GND pins (pin 8 and pin 11) are grounded, and the SET pin (pin 7) is grounded through a resistor R55 and a capacitor C82 connected in parallel; the OUTS pin (pin 9) and the OUT pin (pin 10) of the linear voltage regulator chip U10 are electrically connected to the signal acquisition circuit 309 through the inductor L4, and are also grounded through the inductor L4 and the capacitor C81 in turn, and are also grounded through the capacitor C79 and the capacitor C80, so as to provide the +2.5V voltage AVDD in the bipolar power supply voltage for the signal acquisition circuit.

[0055] In this scheme, if Fig.13As shown, the control circuit 310 includes: a main control chip U13, the main control chip U13 adopts STM32H743IIK6, the PA0 pin, PA1 pin, PA2 pin, PA3 pin, PE11 pin, PE12 pin, PE13 pin, PE14 pin, PC10 pin and PC11 pin of the main control chip U13 are all electrically connected to the audio generation circuit; the PE4 pin, PE5 pin, PE3 pin, PE6 pin, PE2 pin, PB8 pin, PB9 pin and PE1 pin of the main control chip U13 The main control chip U13 has the following pins: PB3 pin, PA15 pin, PB5 pin, PG9 pin, PG13 pin, PC13 pin, PI8 pin, PI7 pin, PC9 pin and PI9 pin, which are all electrically connected to the signal acquisition circuit; the main control chip U13 has the following pins: PB14 pin, PB15 pin, PG11 pin, PB4 pin, PC1 pin, PD7 pin, PA7 pin and PD8 pin, which are all electrically connected to the storage circuit; the main control chip U13 has the following pins: PB11 pin, PB12 pin, P The D6 pin and the PD5 pin are electrically connected to the communication circuit; the PA9 pin, PA10 pin, PA13 pin and PA14 pin of the main control chip U13 are electrically connected to the debug printing interface; the VDDA pin, VBAT pin, VREF+ pin and VDD1-VDD14 pin of the main control chip U13 are all connected to the second power supply voltage VCC_3.3V, the VSSA pin, VREF- pin and VSS1-VSS37 pins of the main control chip U13 are all grounded, and the BOOT0 pin of the main control chip U13 is connected to the second power supply voltage VCC_3.3V. Resistor R67 is grounded, the VCAP1 pin is grounded through capacitor C14, the VCAP2 pin is grounded through capacitor C17, and the PDR_ON pin is grounded through resistor R68. The NRST pin of the main control chip U13 is electrically connected to pin 2 of the touch switch K1 (model KMR221NGLFS), and is also connected to the second power supply voltage VCC_3.3V through resistor R2 and is also grounded through capacitor C16. Pin 1 and pin 4 of the touch switch K1 are both grounded, and a crystal oscillator circuit is connected between the PH0 pin and the PH1 pin of the main control chip U13.

[0056] In this scheme, if Fig.10As shown, the audio generation circuit includes: an audio generation chip U2 (model ESP32-C3), the 3V3 pin (pin 1) of the audio generation chip U2 is electrically connected to the drain of the field effect tube M1 to access the 3.3V voltage VCC2_3V3; the EN pin (pin 2) of the audio generation chip U2 is electrically connected to the drain of the field effect tube M1 through a resistor R74, and is also electrically connected to the pin 2 of the touch switch K4 (model KMR221NGLFS), and is also grounded through a capacitor C106; the touch switch K4 Pin 1 and pin 4 are grounded; the IO6 pin (pin 5) of the audio generation chip U2 is electrically connected to the PE12 pin of the main control chip U13, and the IO7 pin (pin 6) is electrically connected to the PE14 pin of the main control chip U13; the IO8 pin (pin 7) of the audio generation chip U2 is electrically connected to the PA0 pin of the main control chip U13, and is also electrically connected to the drain of the field effect transistor M1 through the resistor R75; the IO9 pin (pin 8) of the audio generation chip U2 is electrically connected to the PA1 pin of the main control chip U13, and is also electrically connected to the drain of the field effect transistor M1 through the resistor R75. The IO10 pin (pin 10) of the audio generation chip U2 is electrically connected to the PE11 pin of the main control chip U13; the RXD0 pin (pin 11) and TXD0 pin (pin 12) of the audio generation chip U2 are electrically connected to the pin 1 and pin 2 of the audio source interface J2, respectively. The audio source interface J2 is a USB communication interface or a serial communication interface, and pin 4 is grounded; the IO3 pin (pin 15 ... The PA2 pin of the audio generation chip U13 is electrically connected, the IO2 pin (pin 15) is electrically connected to the PE13 pin of the main control chip U13, the IO1 pin (pin 17) is electrically connected to the PC11 pin of the main control chip U13, and the IO0 pin (pin 18) is electrically connected to the PC10 pin of the main control chip U13; all GND pins (pin 9, pin 19, pin 20, pin 21, pin 22, pin 23, pin 24, pin 25, pin 26, pin 27) of the audio generation chip U2 are grounded.

[0057] In this scheme, if Fig. 9As shown, the audio driving circuit includes: an audio driving chip U7 (model WM8978), the LRC pin (pin 7) of the audio driving chip U7 is electrically connected to the PE4 pin of the main control chip U13, the BCLK pin (pin 8) is electrically connected to the PE5 pin of the main control chip U13, the ADCDAT pin (pin 9) is electrically connected to the PE3 pin of the main control chip U13, the DACDAT pin (pin 10) is electrically connected to the PE6 pin of the main control chip U13, and the MCLK pin (pin 11) is electrically connected to the PE2 pin of the main control chip U13; the SCLK pin (pin 16) of the audio driving chip U7 is electrically connected to the main control chip The PB8 pin of U13 is electrically connected and connected to the 3.3V voltage VCC1_3V3 through the resistor R23; the SDIN pin (pin 17) of the audio driver chip U7 is electrically connected to the PB9 pin of the main control chip U13 and connected to the 3.3V voltage VCC1_3V3 through the resistor R24; the MODE pin (pin 18) of the audio driver chip U7 is grounded through the resistor R27; the EP pin (pin 33), DGND pin (pin 12), SPKGND pin (pin 24) and AGND pin (pin 28) of the audio driver chip U7 are all grounded, and the DGND pin (pin 12) and SPKGND pin (pin 28) are all grounded. The resistor R28 is connected between the D pin (pin 24) of the audio driver chip U7; the VMID pin (pin 27) of the audio driver chip U7 is grounded through the capacitor C103; the ROUT1 pin (pin 29) of the audio driver chip U7 is electrically connected to the headphone interface J6 (i.e., the headphone interface 307) through the capacitor C43, the LOUT1 pin (pin 30) is electrically connected to the headphone interface J6 through the capacitor C44, and the LOUT1 pin (pin 30) is also electrically connected to the signal acquisition circuit 309 through the capacitor C44 and the resistor R25, for sending out a synchronization signal; the SPKVDD pin (pin 26) and the AVDD pin (pin 3 1) are electrically connected to the VOUT pin (pin 5) of the linear regulator U8; the SPKVDD pin (pin 26) of the audio driver chip U7 is grounded through parallel capacitors C36 and C41, and the AVDD pin (pin 31) is grounded through parallel capacitors C37 and C42, respectively, to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driver chip U7; the DBVDD pin (pin 14) and DCVDD pin (pin 13) of the audio driver chip U7 are both electrically connected to the drain of the field effect transistor M2, to provide a 3.3V voltage VCC1_3V3 for the audio driver chip U7.

[0058] In this solution, eight EEG electrodes 101 are arranged on the EEG cap 100 from front to back, and an EEG acquisition protection circuit is also integrated in the shell 301. The eight EEG electrodes 101 are electrically connected to the signal acquisition circuit 309 through the signal acquisition interface 308 and the EEG acquisition protection circuit.

[0059] Among them, Fig.14 As shown, the EEG acquisition protection circuit includes ESD protection circuit D6, ESD protection circuit D7 and ESD protection circuit D8.

[0060] Pin 2 of the ESD protection circuit D6 is connected to a -2.5V voltage AVSS and is also grounded through a capacitor C99, pin 3 of the ESD protection circuit D6 receives a reference signal EEG_SRB1 through a signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R40 to output a reference signal SRB1, pin 4 of the ESD protection circuit D6 receives an EEG signal EEG_IN2_P induced by the second EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R33 to output an EEG signal IN2_P, pin 5 of the ESD protection circuit D6 is connected to a +2.5V voltage AVDD and is also grounded through a capacitor C96, pin 6 of the ESD protection circuit D6 receives an EEG signal EEG_IN1_P induced by the first EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R32 to output an EEG signal IN1_P.

[0061] Pin 1 of the ESD protection circuit D7 receives the EEG signal EEG_IN3_P sensed by the third EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R34 to output the EEG signal IN3_P. Pin 2 of the ESD protection circuit D7 is connected to the -2.5V voltage AVSS and is also grounded through the capacitor C100. Pin 3 of the ESD protection circuit D7 receives the EEG signal EEG_IN4_P sensed by the fourth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R35 to output the EEG signal IN4_P. Pin 4 of the ESD protection circuit D7 receives the EEG signal EEG_IN5_P induced by the fifth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R36 to output the EEG signal IN5_P. Pin 5 of the ESD protection circuit D7 is connected to the +2.5V voltage AVDD and is also grounded through the capacitor C97. Pin 6 of the ESD protection circuit D7 receives the EEG signal EEG_IN6_P induced by the sixth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R37 to output the EEG signal IN6_P.

[0062] Pin 1 of the ESD protection circuit D8 receives the EEG signal EEG_IN7_P induced by the seventh EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R38 to output the EEG signal IN7_P. Pin 2 of the ESD protection circuit D8 is connected to a -2.5V voltage AVSS and is also grounded through a capacitor C101. Pin 3 of the ESD protection circuit D8 receives the EEG signal EEG_IN8_P induced by the eighth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R39 to output the EEG signal IN8_P. Pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R41 to output the bias signal BIAS. Pin 5 of the ESD protection circuit D8 is connected to a +2.5V voltage AVDD and is also grounded through a capacitor C98.

[0063] like Fig.15 As shown, the signal acquisition circuit 309 includes: a signal acquisition chip U9 (model ADS1299-4PAG), the SRB1 pin (pin 17) of the signal acquisition chip U9 is connected to the reference signal SRB1, the IN1P pin (pin 16) is connected to the EEG signal IN1_P, the IN2P pin (pin 14) is connected to the EEG signal IN2_P, the IN3P pin (pin 12) is connected to the EEG signal IN3_P, the IN4P pin (pin 10) is connected to the EEG signal IN4_P, the IN5P pin (pin 8) is connected to the EEG signal IN5_P, the IN6P pin (pin 6) is connected to the EEG signal IN6_P, the IN7P pin (pin 4) is connected to the EEG signal IN7_P, and the IN8P pin (pin 2) is connected to the EEG signal IN8_P; the capacitor C55 and the resistor R49 are connected in parallel between the BIASINV pin (pin 61) and the BIASOUT pin (pin 62) of the signal acquisition chip U9, and then the resistor R5 is connected. 0 is connected to the bias signal BIAS; the VCAP1 pin (pin 28) of the signal acquisition chip U9 is connected to the -2.5V voltage AVSS through the capacitor C67, the VCAP2 pin (pin 30) is connected to the -2.5V voltage AVSS through the capacitor C59, the VCAP3 pin (pin 55) is connected to the -2.5V voltage AVSS through the parallel capacitors C60 and C61, and the VCAP4 pin (pin 26) is connected to the -2.5V voltage AVSS through the capacitor C62; the RESV1 pin (pin 31) and three DGND pins (pin 33, pin 49 and pin 51) of the signal acquisition chip U9 are all grounded; the VREFP pin (pin 24) of the signal acquisition chip U9 is connected to the reference voltage VREFP, the VREFN pin (pin 25) is connected to the -2.5V voltage AVSS, and capacitors C56 and C57 are connected in parallel between the VREFP pin (pin 24) and the VREFN pin (pin 25).

[0064] The GPIO1 pin (pin 42) of the signal acquisition chip U9 is grounded through a resistor R47, the GPIO2 pin (pin 44) is grounded through a resistor R46, the GPIO3 pin (pin 45) is grounded through a resistor R45, the GPIO4 pin (pin 46) is grounded through a resistor R44, and the CLKSEL pin (pin 52) is grounded through a resistor R48.

[0065] The CLK pin (pin 37) of the signal acquisition chip U9 is electrically connected to the PC9 pin of the main control chip U13. The pin (pin 35) is electrically connected to the PI7 pin of the main control chip U13. The pin (pin 36) is electrically connected to the PI8 pin of the main control chip U13, the START pin (pin 38) is electrically connected to the PC13 pin of the main control chip U13, The pin (pin 47) is electrically connected to the PG13 pin of the main control chip U13, the DOUT pin (pin 43) is electrically connected to the PG9 pin of the main control chip U13, the DIN pin (pin 34) is electrically connected to the PB5 pin of the main control chip U13, The pin (pin 39) is electrically connected to the PA15 pin of the main control chip U13, and the SCLK pin (pin 40) is electrically connected to the PB3 pin of the main control chip U13.

[0066] The two DVDD pins (pin 48 and pin 50) of the signal acquisition chip U9 are connected to the filtered voltage DVDD_33 and are also grounded through capacitors C52 and C53 respectively; all AVSS pins (pin 20, pin 23, pin 32, pin 58 and pin 57) and AVSS1 pin (pin 53) of the signal acquisition chip U9 are connected to -2.5V voltage AVSS, and all AVDD pins (pin 19, pin 21, pin 22, pin 59 and pin 56) and AVSS1 pin (pin 54) are connected to +2.5V voltage AVDD.

[0067] like Fig.11As shown, the storage circuit 311 includes: a storage chip J7 (model TF-01A), the D0 pin (pin 7) of the storage chip J7 is electrically connected to the PB14 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC3_3V3 through a resistor R66; the D1 pin (pin 8) of the storage chip J7 is electrically connected to the PB15 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC3_3V3 through a resistor R65; the D2 pin (pin 1) of the storage chip J7 is electrically connected to the PG11 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC3_3V3 through a resistor R64; the D3 pin (pin 2) of the storage chip J7 is electrically connected to the PB4 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC3_3V3 through a resistor R63. voltage VCC3_3V3; the CLK pin (pin 5) of the memory chip J7 is electrically connected to the PC1 pin of the main control chip U13; the CMD pin (pin 3) of the memory chip J7 is electrically connected to the PD7 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC3_3V3 through the resistor R62; the CD pin (pin 9) of the memory chip J7 is electrically connected to the PD8 pin of the main control chip U13, and is also connected to the second power supply voltage VCC_3.3V through the resistor R31; the VDD pin (pin 4) of the memory chip J7 is connected to the 3.3V voltage VCC3_3V3; the VSS pin (pin 6), NC1 (pin 11), NC2 (pin 12), NC3 (pin 13) and G# pin (pin 10) of the memory chip J7 are all grounded;

[0068] like Figure 8As shown, the communication circuit 313 includes a USB to serial port chip U6 (model CH343) and a Type-C interface U5; the VIO pin (pin 1) and the VDDS pin of the USB to serial port chip U6 are both connected to the second power supply voltage VCC_3.3V and are also grounded through a capacitor C35; the GND pin (pin 2) and the EP pin (pin 17) of the USB to serial port chip U6 are grounded; the TXD pin (pin 4) of the USB to serial port chip U6 is electrically connected to the PD6 pin of the main control chip U13 through a resistor R18, and the RXD pin (pin 5) is electrically connected to the PD5 pin of the main control chip U13 through a resistor R19; the V3 pin (pin 16) of the USB to serial port chip U6 is electrically connected to the PD6 pin of the main control chip U13 through a resistor R18, and the RXD pin (pin 5) is electrically connected to the PD5 pin of the main control chip U13 through a resistor R19; 6) Connect to the second power supply voltage VCC_3.3V and also ground through capacitor C33; the UD+ pin (pin 7) of the USB-to-serial port chip U6 is electrically connected to the DP1 pin and DP2 pin of the Type-C interface U5 through resistor R58, and the UD- pin (pin 8) is electrically connected to the DN1 pin and DN2 pin of the Type-C interface U5 through resistor R59; the VBUS pin (pin 9) of the USB-to-serial port chip U6 is electrically connected to the first protection circuit; the DP1 pin and DP2 pin of the Type-C interface U5 are grounded through electrostatic protection diode D4, the DN1 pin and DN2 pin are grounded through electrostatic protection diode D3, and the GND pin is grounded.

[0069] like Fig.16 As shown, the system operation indication circuit 312 includes a resistor R16, a light-emitting diode D1 and a transistor Q2, the base of the transistor Q2 is electrically connected to the PD10 pin of the main control chip U13, the emitter is grounded, the collector is electrically connected to the cathode of the light-emitting diode D1, and the anode of the light-emitting diode D1 is connected to the 3.3V voltage VCC3_3V3 through the resistor R16.

[0070] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that these are only examples, and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A multi-channel electroencephalogram signal acquisition system based on auditory evoked potential, characterized in that: It includes an EEG cap and earphones for collectors to wear, and an EEG acquisition device, wherein the EEG cap is equipped with a plurality of EEG electrodes, the EEG acquisition device is installed on the EEG cap, and the EEG acquisition device includes a shell, wherein a power supply interface, a power supply circuit, a sound source interface, an audio generation circuit, an audio driving circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, a system operation indication circuit and a communication circuit are integrated in the shell; The power supply circuit is used to connect to an external power supply through a power supply interface, and convert the external power supply into a power supply voltage to power the control circuit, the audio generation circuit, the audio drive circuit, the signal acquisition circuit, the storage circuit, the system operation indication circuit and the communication circuit; The control circuit is connected to the host computer through the communication circuit, the sound source interface, the audio generation circuit and the control circuit are electrically connected in sequence, the control circuit is used to control the sending of a trigger signal to the audio generation circuit after receiving an EEG signal acquisition instruction through the communication circuit, and the audio generation circuit is used to generate an audio signal based on the sound source obtained through the sound source interface after receiving the trigger signal; The audio generation circuit is electrically connected to the audio driving circuit, the headphone interface, the audio driving circuit and the control circuit are electrically connected in sequence, the audio driving circuit is used to receive an audio signal and generate an audio driving signal containing the audio signal based on the audio signal, and the control circuit is used to control the audio driving circuit to output an audio driving signal of a set duration through the headphone interface, so that the headphone outputs a sound stimulus of the set duration to act on the collector; The audio driving circuit is electrically connected to the signal acquisition circuit, and the EEG electrodes, the signal acquisition interface, the signal acquisition circuit and the control circuit are electrically connected in sequence. The audio driving circuit is used to generate a synchronization signal based on the audio driving signal and transmit it to the signal acquisition circuit. The signal acquisition circuit is used to collect multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface and transmit the multi-channel EEG signals to the control circuit. The storage circuit and the communication circuit are both electrically connected to the control circuit, and the control circuit is used to store the multi-channel EEG signals of the collector in the storage circuit and upload them to the host computer through the communication circuit; The system operation indication circuit is electrically connected to the control circuit, and the control circuit is used to control the system operation indication circuit to light up when the system operates normally.

2. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 1, characterized in that: The power supply circuit includes a power supply main switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage stabilizing circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage stabilizing circuit and a third voltage stabilizing circuit; The input end of the power supply main switch circuit is electrically connected to the power supply interface, and the output end of the power supply main switch circuit is electrically connected to the control circuit through the first DC-DC circuit. The power supply main switch circuit is used to control the circuit to be turned on and to adjust the output first power supply voltage based on the input voltage. The first DC-DC circuit is used to convert the first power supply voltage into a second power supply voltage and provide the second power supply voltage for the control circuit; The output end of the power main switch circuit is electrically connected to the communication circuit through the first protection circuit to provide a VBUS voltage for the communication circuit, and the output end of the first DC-DC circuit is electrically connected to the communication circuit to provide a second power supply voltage for the communication circuit; The output end of the power supply main switch circuit is electrically connected to the audio driving circuit through a first voltage stabilizing circuit, the first voltage stabilizing circuit is used to stabilize the first power supply voltage into a regulated power supply voltage and provide the regulated power supply voltage for the audio driving circuit, and the output end of the first DC-DC circuit is electrically connected to the audio driving circuit through a first switch circuit to provide a second power supply voltage for the audio driving circuit; The output end of the first DC-DC circuit is electrically connected to the audio generation circuit through the second switch circuit to provide a second power supply voltage for the audio generation circuit; The output end of the first DC-DC circuit is electrically connected to the storage circuit through a third switch circuit to provide a second power supply voltage for the storage circuit; The output end of the first DC-DC circuit is electrically connected to the input end of the fourth switch circuit, and the output end of the fourth switch circuit is electrically connected to the signal acquisition circuit through the filter circuit to provide a filtered voltage for the signal acquisition circuit. The output end of the fourth switch circuit is also electrically connected to the signal acquisition circuit through the second DC-DC circuit and the second voltage stabilizing circuit, and is also electrically connected to the signal acquisition circuit through the third voltage stabilizing circuit, so as to provide a bipolar power supply voltage for the signal acquisition circuit.

3. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 2, characterized in that: The power main switch circuit includes: a main switch K3 and a power switch chip U4. The switch end of the main switch K3 is embedded in the housing. The IN pin of the power switch chip U4 is electrically connected to the power supply interface, and is also electrically connected to the pin 2 of the main switch K3, and is also grounded through a capacitor C30. The EN pin of the power switch chip U4 is electrically connected to the pin 3 of the main switch K3 through a resistor R14, and is also grounded through a resistor R77 and a capacitor C32. The GND pin and EP pin of the power switch chip U4 are both grounded. The power supply interface is electrically connected through the power status indicator D2 and the resistor R17, the ILIM pin is grounded through the resistor R15, and the OUT pin of the power switch chip U4 is used to output the first power supply voltage VCC_5V and is also grounded through the capacitor C31; The first DC-DC circuit includes: a power management chip U1, two PVIN pins, AVIN pin and EN pin of the power management chip U1 are electrically connected to the OUT pin of the power switch chip U4, and are also grounded through resistors R9 and R12 in series, and are also grounded through capacitors C105, C24, and C23. The FSW pin of the power management chip U1 is grounded through resistor R12, the DEF pin is grounded through resistor R11, and the SS / TR pin is grounded through capacitor C29. The two PVIN pins, AVIN pin and EN pin of the power management chip U1 are electrically connected to the OUT pin of the power switch chip U4, and are also grounded through resistors R9 and R12 in series, and are also grounded through capacitors C105, C24, and C23. The FSW pin of the power management chip U1 is grounded through resistor R12, the DEF pin is grounded through resistor R11, and the SS / TR pin is grounded through capacitor C29. The PGND pin, AGND pin and EP pin are all grounded, the FB pin of the power management chip U1 is grounded through the resistor R13, the VOS pin is grounded through the resistor R10 and the resistor R13 connected in series, and the three SW pins of the power management chip U1 output the second power supply voltage VCC_3.3V through the inductor L1 and the inductor L8 connected in series. The inductor L1 and the inductor L8 are grounded through the capacitors C25, C26, C27 and C28 respectively, and the end of the inductor L8 away from the inductor L1 is grounded through the capacitors C108 and C107 respectively.

4. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 3, characterized in that: The first protection circuit includes: a resistor R20 and a diode D5, one end of the resistor R20 is electrically connected to the OUT pin of the power switch chip U4, and the other end is electrically connected to the cathode of the diode D5, the anode of the diode D5 is grounded, and the cathode is electrically connected to the communication circuit to provide the VBUS voltage; The first voltage stabilizing circuit includes: a linear voltage regulator U8, a VIN pin of the linear voltage regulator U8 is electrically connected to the OUT pin of the power switch chip U4, is also grounded through a capacitor C45, is also grounded through a capacitor C46, ​​an EN pin of the linear voltage regulator U8 is electrically connected to the control circuit, a GND pin is grounded, a BP pin is grounded through a capacitor C49, a VOUT pin of the linear voltage regulator U8 is electrically connected to the audio driving circuit, is also grounded through a capacitor C47, is also grounded through a capacitor C48, and is used to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driving circuit; The first switch circuit includes: a transistor Q3 and a field effect transistor M2, the base of the transistor Q3 is electrically connected to the control circuit, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through a resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through a capacitor C38, the source is also electrically connected to the collector of the transistor Q3 through a resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio driving circuit, is also grounded through a capacitor C39, and is also grounded through a capacitor C40, so as to provide a 3.3V voltage VCC1_3V3 for the audio driving circuit; The second switch circuit includes: a transistor Q1 and a field effect transistor M1, the base of the transistor Q1 is electrically connected to the control circuit, the emitter of the transistor Q1 is grounded, the source of the field effect transistor M1 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R6 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C18, the source is also electrically connected to the collector of the transistor Q1 through the resistor R7, the gate of the field effect transistor M1 is electrically connected to the collector of the transistor Q1, the drain of the field effect transistor M1 is electrically connected to the audio generation chip generation circuit, is also grounded through the capacitor C19, and is also grounded through the capacitor C20, so as to provide a 3.3V voltage VCC2_3V3 for the audio generation circuit; The third switch circuit includes: a transistor Q4 and a field effect transistor M3, the base of the transistor Q4 is electrically connected to the control circuit, the emitter of the transistor Q4 is grounded, the source of the field effect transistor M3 is electrically connected to the inductor L8 of the power management chip U1 through a resistor R29 to access the second power supply voltage VCC_3.3V, the source is also grounded through a capacitor C50, the source is also electrically connected to the collector of the transistor Q4 through a resistor R30, the gate of the field effect transistor M3 is electrically connected to the collector of the transistor Q4, the drain of the field effect transistor M3 is electrically connected to the storage circuit, is also grounded through a capacitor C95, and is also grounded through a capacitor C51, so as to provide a 3.3V voltage VCC3_3V3 for the storage circuit; The fourth switch circuit includes: a transistor Q5 and a field effect transistor M4, the base of the transistor Q5 is electrically connected to the control circuit, the emitter of the transistor Q5 is grounded, the source of the field effect transistor M4 is electrically connected to the inductor L8 of the power management chip U1 through a resistor R52 to access the second power supply voltage VCC_3.3V, the source is also grounded through a capacitor C71, the source is also electrically connected to the collector of the transistor Q5 through a resistor R53, the gate of the field effect transistor M4 is electrically connected to the collector of the transistor Q5, the drain of the field effect transistor M4 is respectively electrically connected to the filter circuit, the second DC-DC circuit and the third voltage stabilizing circuit, and is also grounded through a capacitor C72, so as to provide a 3.3V voltage VCC4_3V3; The filtering circuit includes: an inductor L2, a capacitor C73, a capacitor C74 and a capacitor C75, one end of the inductor L2 is electrically connected to the drain of the field effect transistor M4, and is also grounded through the capacitor C73 and the capacitor C74, and the other end of the inductor L2 is electrically connected to the signal acquisition circuit and is also grounded through the capacitor C75, and is used to provide a filtered voltage DVDD_33 for the signal acquisition circuit; The second DC-DC circuit includes: a switching regulator chip U11, an IN pin of the switching regulator chip U11 is electrically connected to the drain of the field effect transistor M4 through an inductor L5, is also grounded through the series-connected inductor L5 and capacitor C84, is also grounded through a capacitor C85, and is also grounded through a capacitor C86, a GND pin of the switching regulator chip U11 is grounded, a capacitor C83 is connected between the CFLY- pin and the CFLY+ pin, and an OUT pin of the switching regulator chip U11 is electrically connected to the second voltage stabilization circuit through an inductor L6, and is also grounded through capacitors C87 and C88 respectively; The second voltage stabilizing circuit comprises: a negative linear voltage stabilizing chip U12, the IN1 pin, IN2 pin, EP pin, PGFB pin and EN / UV pin of the negative linear voltage stabilizing chip U12 are all electrically connected to the inductor L6, and are also grounded through capacitors C89 and C90 respectively, the ILIM pin of the negative linear voltage stabilizing chip U12 is grounded through a resistor R57, the GND pin is grounded, and the SET pin is grounded through a resistor R56 and a capacitor C94 connected in parallel respectively, the OUTS pin, OUT1 pin and OUT2 pin of the negative linear voltage stabilizing chip U12 are all electrically connected to the signal acquisition circuit through the inductor L7, and are also grounded through the inductor L7 and the capacitor C93 in turn, and are also grounded through the capacitor C91 and the capacitor C92, for providing a -2.5V voltage AVSS in the bipolar power supply voltage for the signal acquisition circuit; The third voltage stabilizing circuit includes: a linear voltage stabilizing chip U10, wherein the IN pin, IN1 pin, PGFB pin and EN / UV pin of the linear voltage stabilizing chip U10 are electrically connected to the drain of the field effect transistor M4 through the inductor L3, and are grounded in turn through the inductor L3 and the capacitor C76, and are also grounded through the capacitors C77 and C78 respectively; the ILIM pin of the linear voltage stabilizing chip U10 is grounded through the resistor R54, the two GND pins are grounded, and the SET pin is grounded through the parallel resistor R55 and the capacitor C82 respectively; the OUTS pin and OUT pin of the linear voltage stabilizing chip U10 are electrically connected to the signal acquisition circuit through the inductor L4, and are also grounded in turn through the inductor L4 and the capacitor C81, and are also grounded through the capacitor C79 and the capacitor C80, so as to provide the signal acquisition circuit with a +2.5V voltage AVDD in the bipolar power supply voltage.

5. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 4, characterized in that: The control circuit includes: a main control chip U13, the main control chip U13 adopts STM32H743IIK6, and the PA0 pin, PA1 pin, PA2 pin, PA3 pin, PE11 pin, PE12 pin, PE13 pin, PE14 pin, PC10 pin and PC11 pin of the main control chip U13 are all electrically connected to the audio generation circuit; The PE4 pin, PE5 pin, PE3 pin, PE6 pin, PE2 pin, PB8 pin, PB9 pin and PE1 pin of the main control chip U13 are all electrically connected to the audio driving circuit; The PB3 pin, PA15 pin, PB5 pin, PG9 pin, PG13 pin, PC13 pin, PI8 pin, PI7 pin, PC9 pin and PI9 pin of the main control chip U13 are all electrically connected to the signal acquisition circuit; The PB14 pin, PB15 pin, PG11 pin, PB4 pin, PC1 pin, PD7 pin, PA7 pin and PD8 pin of the main control chip U13 are all electrically connected to the storage circuit; The PB11 pin, PB12 pin, PD6 pin and PD5 pin of the main control chip U13 are all electrically connected to the communication circuit; The PA9 pin, PA10 pin, PA13 pin and PA14 pin of the main control chip U13 are all electrically connected to the debug printing interface; The VDDA pin, VBAT pin, VREF+ pin and VDD1-VDD14 pins of the main control chip U13 are all connected to the second power supply voltage VCC_3.3V, the VSSA pin, VREF- pin and VSS1-VSS37 pins of the main control chip U13 are all grounded, the BOOT0 pin of the main control chip U13 is grounded through a resistor R67, the VCAP1 pin is grounded through a capacitor C14, the VCAP2 pin is grounded through a capacitor C17, and the PDR_ON pin is grounded through a resistor R68, the NRST pin of the main control chip U13 is electrically connected to pin 2 of the touch switch K1, and is also connected to the second power supply voltage VCC_3.3V through a resistor R2, and is also grounded through a capacitor C16, pins 1 and 4 of the touch switch K1 are both grounded, and a crystal oscillator circuit is connected between the PH0 pin and the PH1 pin of the main control chip U13.

6. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 5, characterized in that: The audio generation circuit includes: an audio generation chip U2, a 3V3 pin of the audio generation chip U2 is electrically connected to the drain of the field effect tube M1 to access a 3.3V voltage VCC2_3V3, an EN pin of the audio generation chip U2 is electrically connected to the drain of the field effect tube M1 through a resistor R74, is also electrically connected to pin 2 of a touch switch K4, is also grounded through a capacitor C106, pins 1 and 4 of the touch switch K4 are grounded, an IO6 pin of the audio generation chip U2 is electrically connected to a PE12 pin of a main control chip U13, an IO7 pin is electrically connected to a PE14 pin of the main control chip U13, an IO8 pin of the audio generation chip U2 is electrically connected to a PA0 pin of the main control chip U13, is also electrically connected to the drain of the field effect tube M1 through a resistor R75, an IO Pin 9 is electrically connected to pin PA1 of the main control chip U13, and is also electrically connected to pin 3 of the sound source interface J2. Pin IO10 of the audio generation chip U2 is electrically connected to pin PE11 of the main control chip U13. Pin RXD0 and pin TXD0 of the audio generation chip U2 are electrically connected to pin 1 and pin 2 of the sound source interface J2 respectively. The sound source interface J2 is a USB communication interface or a serial communication interface, and pin 4 is grounded. Pin IO3 of the audio generation chip U2 is electrically connected to pin PA2 of the main control chip U13, pin IO2 is electrically connected to pin PE13 of the main control chip U13, pin IO1 is electrically connected to pin PC11 of the main control chip U13, pin IO0 is electrically connected to pin PC10 of the main control chip U13, and all GND pins of the audio generation chip U2 are grounded.

7. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 6, characterized in that: The audio driving circuit includes: an audio driving chip U7, an LRC pin of the audio driving chip U7 is electrically connected to a PE4 pin of a main control chip U13, a BCLK pin is electrically connected to a PE5 pin of the main control chip U13, an ADCDAT pin is electrically connected to a PE3 pin of the main control chip U13, a DACDAT pin is electrically connected to a PE6 pin of the main control chip U13, an MCLK pin is electrically connected to a PE2 pin of the main control chip U13, an SCLK pin of the audio driving chip U7 is electrically connected to a PB8 pin of the main control chip U13, and a resistor R2 is also connected to the PE6 pin of the main control chip U13. 3 is connected to the 3.3V voltage VCC1_3V3, the SDIN pin of the audio driver chip U7 is electrically connected to the PB9 pin of the main control chip U13, and is also connected to the 3.3V voltage VCC1_3V3 through the resistor R24, the MODE pin of the audio driver chip U7 is grounded through the resistor R27, the EP pin, DGND pin, SPKGND pin and AGND pin of the audio driver chip U7 are all grounded, and the resistor R28 is connected between the DGND pin and the SPKGND pin, and the VMID pin of the audio driver chip U7 is grounded through the capacitor C103; The ROUT1 pin of the audio driver chip U7 is electrically connected to the headphone interface J6 through the capacitor C43, the LOUT1 pin is electrically connected to the headphone interface J6 through the capacitor C44, and the LOUT1 pin is also electrically connected to the signal acquisition circuit through the capacitor C44 and the resistor R25, for sending a synchronization signal; The SPKVDD pin and AVDD pin of the audio driver chip U7 are both electrically connected to the VOUT pin of the linear regulator U8. The SPKVDD pin of the audio driver chip U7 is grounded through capacitors C36 and C41 connected in parallel, and the AVDD pin is grounded through capacitors C37 and C42 connected in parallel, respectively, to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driver chip U7. The DBVDD pin and the DCVDD pin of the audio driver chip U7 are both electrically connected to the drain of the field effect transistor M2, so as to provide a 3.3V voltage VCC1_3V3 for the audio driver chip U7.

8. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 5, characterized in that: The EEG cap is provided with 8 EEG electrodes from front to back, an EEG acquisition protection circuit is integrated in the shell, and the 8 EEG electrodes are electrically connected to the signal acquisition circuit through a signal acquisition interface and the EEG acquisition protection circuit.

9. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 8, characterized in that: The EEG acquisition protection circuit includes an ESD protection circuit D6, an ESD protection circuit D7 and an ESD protection circuit D8; Pin 2 of the ESD protection circuit D6 is connected to a -2.5V voltage AVSS and is also grounded through a capacitor C99, pin 3 of the ESD protection circuit D6 receives a reference signal EEG_SRB1 through a signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R40 to output a reference signal SRB1, pin 4 of the ESD protection circuit D6 receives an EEG signal EEG_IN2_P sensed by a second EEG electrode through a signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R33 to output an EEG signal IN2_P, pin 5 of the ESD protection circuit D6 is connected to a +2.5V voltage AVDD and is also grounded through a capacitor C96, pin 6 of the ESD protection circuit D6 receives an EEG signal EEG_IN1_P sensed by a first EEG electrode through a signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R32 to output an EEG signal IN1_P; Pin 1 of the ESD protection circuit D7 receives the EEG signal EEG_IN3_P sensed by the third EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R34 to output the EEG signal IN3_P. Pin 2 of the ESD protection circuit D7 is connected to the -2.5V voltage AVSS and is also grounded through the capacitor C100. Pin 3 of the ESD protection circuit D7 receives the EEG signal EEG_IN4_P sensed by the fourth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R35 to output the EEG signal IN4_P. , pin 4 of the ESD protection circuit D7 receives the EEG signal EEG_IN5_P sensed by the fifth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R36 to output the EEG signal IN5_P, pin 5 of the ESD protection circuit D7 is connected to the +2.5V voltage AVDD, and is also grounded through the capacitor C97, and pin 6 of the ESD protection circuit D7 receives the EEG signal EEG_IN6_P sensed by the sixth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through the resistor R37 to output the EEG signal IN6_P; Pin 1 of the ESD protection circuit D8 receives the EEG signal EEG_IN7_P induced by the seventh EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R38 to output the EEG signal IN7_P. Pin 2 of the ESD protection circuit D8 is connected to a -2.5V voltage AVSS and is also grounded through a capacitor C101. Pin 3 of the ESD protection circuit D8 receives the EEG signal EEG_IN8_P induced by the eighth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R39 to output the EEG signal IN8_P. Pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through a resistor R41 to output the bias signal BIAS. Pin 5 of the ESD protection circuit D8 is connected to a +2.5V voltage AVDD and is also grounded through a capacitor C98.

10. The multi-channel EEG signal acquisition system based on auditory evoked potential according to claim 9, characterized in that: The signal acquisition circuit includes: a signal acquisition chip U9, the SRB1 pin of the signal acquisition chip U9 is connected to the reference signal SRB1, the IN1P pin is connected to the EEG signal IN1_P, the IN2P pin is connected to the EEG signal IN2_P, the IN3P pin is connected to the EEG signal IN3_P, the IN4P pin is connected to the EEG signal IN4_P, the IN5P pin is connected to the EEG signal IN5_P, the IN6P pin is connected to the EEG signal IN6_P, the IN7P pin is connected to the EEG signal IN7_P, and the IN8P pin is connected to the EEG signal IN8_P, and the capacitor C55 and the resistor R49 are connected in parallel between the BIASINV pin and the BIASOUT pin of the signal acquisition chip U9, and then connected to the bias signal through the resistor R50. BIAS, the VCAP1 pin of the signal acquisition chip U9 is connected to the -2.5V voltage AVSS through the capacitor C67, the VCAP2 pin is connected to the -2.5V voltage AVSS through the capacitor C59, the VCAP3 pin is connected to the -2.5V voltage AVSS through the capacitors C60 and C61 connected in parallel, the VCAP4 pin is connected to the -2.5V voltage AVSS through the capacitor C62, the RESV1 pin and the three DGND pins of the signal acquisition chip U9 are all grounded, the VREFP pin of the signal acquisition chip U9 is connected to the reference voltage VREFP, the VREFN pin is connected to the -2.5V voltage AVSS, and the capacitors C56 and C57 are connected in parallel between the VREFP pin and the VREFN pin; The CLK pin of the signal acquisition chip U9 is electrically connected to the PC9 pin of the main control chip U13. The pin is electrically connected to the PI7 pin of the main control chip U13. The pin is electrically connected to the PI8 pin of the main control chip U13, the START pin is electrically connected to the PC13 pin of the main control chip U13, The pin is electrically connected to the PG13 pin of the main control chip U13, the DOUT pin is electrically connected to the PG9 pin of the main control chip U13, the DIN pin is electrically connected to the PB5 pin of the main control chip U13, The pin is electrically connected to the PA15 pin of the main control chip U13, and the SCLK pin is electrically connected to the PB3 pin of the main control chip U13; The two DVDD pins of the signal acquisition chip U9 are connected to the filtered voltage DVDD_33 and are grounded through capacitors C52 and C53 respectively. All AVSS pins and AVSS1 pins of the signal acquisition chip U9 are connected to the -2.5V voltage AVSS, and all AVDD pins and AVSS1 pins are connected to the +2.5V voltage AVDD.

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