A method of reducing manufacturing cost of a pressure sensor and a pressure sensor

Abstract

The application provides a method for reducing the manufacturing cost of a pressure sensor and the pressure sensor, and the method comprises the following steps: providing a first substrate, which comprises a bottom silicon layer, a buried oxygen layer and a top silicon layer which are stacked in sequence; forming a first doped region and a second doped region in a preset region of the top silicon layer from the top surface side of the top silicon layer; after the first doped region and the second doped region are formed, forming a cavity groove which is exposed by the bottom surface of the bottom silicon layer in the bottom silicon layer from the bottom surface side of the bottom silicon layer, and the groove bottom of the cavity groove is exposed by the buried oxygen layer; and the ion implantation is carried out by taking the photoetching mask layer for forming the cavity groove as a mask to form a well region in the preset region of the top silicon layer, so that one photo mask is saved, and the manufacturing cost of the pressure sensor is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and more particularly to a method for reducing the manufacturing cost of pressure sensors and a pressure sensor thereof. Background Technology

[0002] The fabrication of MEMS (Micro-Electro-Mechanical Systems) pressure sensors typically involves multiple complex process steps, including photolithography, etching, thin film deposition, and packaging, which require the use of multiple photomasks.

[0003] However, the complex manufacturing process and high production costs of current MEMS pressure sensors severely restrict their market promotion and application. Summary of the Invention

[0004] This invention provides a method for manufacturing a pressure sensor that reduces the manufacturing cost by effectively utilizing the device's own structure and saving a photomask.

[0005] To address the aforementioned technical problems, the present invention provides a method for reducing the manufacturing cost of pressure sensors, comprising:

[0006] A first substrate is provided, comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially;

[0007] A first doped region and a second doped region are formed from one side of the top surface of the top silicon layer within a predetermined region of the top silicon layer;

[0008] A patterned mask layer is formed on the bottom surface of the bottom silicon layer. The mask layer includes a cavity recess window pattern and a blocking area. The cavity recess window pattern and the preset area are vertically corresponding, and the size of the cavity recess window pattern is larger than the size of the preset area.

[0009] Using the patterned mask layer as a mask, the underlying silicon within the cavity groove window pattern is etched, with the etching endpoint stopping at the surface of the buried oxide layer;

[0010] Using the patterned mask layer as a mask, ion implantation is performed on the predetermined well region position of the top silicon layer from one side of the bottom surface of the bottom silicon layer to form a well region. The predetermined well region position corresponds vertically to the cavity groove.

[0011] A second substrate is provided, and the bottom surface of the second substrate and the bottom silicon layer of the first substrate are bonded together to form a pressure sensor.

[0012] Optionally, the parameters for the N-type ion implantation include: the implanted material comprising at least phosphorus, and the implantation dose being at 4e. 15 ions / cm 2 ~6e15 ions / cm 2 The injection energy is between 110 keV and 130 keV, and the ion injection angle is between 6° and 8° off the vertical direction.

[0013] Optionally, before forming the first doped region and the second doped region, the method further includes:

[0014] An oxide layer is formed on the surface of the top silicon layer;

[0015] A first cutting mark is formed on the surface of the oxide layer, and the cutting area is located outside the main body of the pressure sensor.

[0016] Optionally, before forming the cavity groove on the bottom surface of the bottom silicon layer, the method further includes:

[0017] The bottom surface of the bottom silicon layer is thinned, and the thickness of the first substrate is reduced to a first preset thickness;

[0018] The bottom surface of the thinned silicon layer is subjected to chemical mechanical polishing.

[0019] Optionally, the first preset thickness is within 500 μm.

[0020] Optionally, the second substrate includes a first surface and a second surface that are vertically opposite each other, the first surface of the second substrate is bonded to the bottom surface of the bottom silicon layer, and further includes:

[0021] The second side of the second substrate is thinned, and the thickness of the bonded wafer is reduced to a second preset thickness;

[0022] The second surface of the thinned second substrate is subjected to chemical mechanical polishing.

[0023] Optionally, the second preset thickness is within 700 μm.

[0024] Optionally, a first doped region is formed in a predetermined region within the top silicon layer, specifically including:

[0025] P+ doped region on the surface of the oxide layer;

[0026] Photoresist is uniformly coated on the surface of the oxide layer;

[0027] The photoresist is exposed, developed, and baked using a first photomask, which includes a P+ doped region window pattern region and a blocking region.

[0028] The first ion implantation is performed to form a P+ doped region.

[0029] Optionally, a second doped region is formed in a predetermined region within the top silicon layer, specifically including:

[0030] The photoresist is exposed, developed, and baked using a second photomask, which includes a P-doped region window pattern area and a blocking region.

[0031] A second ion implantation is performed to form a P-doped region;

[0032] Remove the photoresist;

[0033] Thermal annealing is performed on the surface of the second oxide to activate impurity atoms and repair lattice damage.

[0034] The present invention also provides a pressure sensor, comprising a pressure sensor prepared by the method for reducing the manufacturing cost of the pressure sensor, the pressure sensor comprising:

[0035] A first substrate, comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially;

[0036] The first doped region and the second doped region are both located within the top silicon layer region;

[0037] A well region that encloses the first doped region and the second doped region and completely fills the preset region;

[0038] A cavity groove is located within the bottom silicon layer, with the cavity groove and the preset area being vertically opposite each other and exposing the buried oxide layer;

[0039] A second substrate is bonded to the bottom surface of the bottom silicon layer to form the cavity structure of the pressure sensor.

[0040] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0041] The method for reducing the manufacturing cost of pressure sensors provided by this invention involves reusing the mask layer that forms the cavity recess to perform N-type ion implantation on the top silicon layer. Therefore, one photomask is saved during the fabrication of the N-type well region, thereby reducing the manufacturing cost of the pressure sensor. Simultaneously, the buried oxide layer within the cavity recess acts as a barrier layer. During ion implantation, the implanted ions are hindered by the buried oxide layer, increasing the scattering of the implanted ions into the crystal lattice and preventing direct alignment of the implantation with interstitial lattice positions. This allows for control over the ion implantation depth. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the cross-sectional structure of a pressure sensor;

[0043] Figures 2 to 11This is a cross-sectional structural schematic diagram of each step of a method for reducing the manufacturing cost of a pressure sensor according to an embodiment of the present invention. Detailed Implementation

[0044] As described in the background section, the current manufacturing process of MEMS pressure sensors suffers from complex procedures and high production costs. This will be explained below with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of the cross-sectional structure of a pressure sensor.

[0046] Please refer to Figure 1 , Figure 1 The fabrication process of the pressure sensor shown generally includes the following:

[0047] Provide an SO1 substrate 210;

[0048] An oxide layer 220 is formed on the surface of the top silicon layer 213 in the SOI substrate 210, and a cutting mark 230 is formed at the edge of the oxide layer surface, penetrating the oxide layer 220 and the top silicon layer 213;

[0049] N-type ion implantation is performed on the surface of the oxide layer 220 using an N-type ion implantation photomask to form a well region 240 within the top silicon layer 213;

[0050] After forming the N-type well region 240, P+ ion implantation and P- ion implantation are performed on the surface of the oxide layer 220 using P+ ion implantation photomask and P- ion implantation photomask, respectively, to form P+ doped region 250 and P- doped region 260 in the top silicon layer 213, respectively.

[0051] A cavity groove 2111 is formed on the bottom surface of the bottom silicon layer 211 in the SOI substrate 210 to expose the buried oxide layer 212 in the SOI substrate 210.

[0052] A second substrate 270 is provided, and the second substrate 270 and the bottom surface of the bottom silicon layer 211 are bonded together to form a cavity structure for a MEMS pressure sensor.

[0053] The problem with the above-described pressure sensor fabrication process is that each process, such as cavity etching, trap ion implantation, and doping, requires exposure and development to form the corresponding patterned areas, which increases the fabrication cost of the pressure sensor.

[0054] To address the aforementioned technical problems, embodiments of the present invention provide a method for reducing the manufacturing cost of pressure sensors, the method comprising:

[0055] A first substrate is provided, comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially;

[0056] A first doped region and a second doped region are formed from one side of the top surface of the top silicon layer within a predetermined region of the top silicon layer;

[0057] A patterned mask layer is formed on the bottom surface of the bottom silicon layer. The patterned mask layer includes a cavity recess window pattern and a blocking area. The cavity recess window pattern and the preset area are vertically corresponding, and the size of the cavity recess window pattern is larger than the size of the preset area.

[0058] Using the patterned mask layer as a mask, the underlying silicon within the cavity groove window pattern is etched, with the etching endpoint stopping at the surface of the buried oxide layer;

[0059] Using the patterned mask layer as a mask, ion implantation is performed on the predetermined well region position of the top silicon layer from one side of the bottom surface of the bottom silicon layer to form a well region. The predetermined well region position corresponds vertically to the cavity groove.

[0060] A second substrate is provided, and the bottom surface of the second substrate and the bottom silicon layer of the first substrate are bonded together to form a pressure sensor.

[0061] Since the cavity recess window pattern in the mask layer is vertically aligned with the preset region, this embodiment of the application can reuse the mask layer as a mask after etching the cavity recess through the photolithography mask layer to perform ion implantation on the exposed buried oxide layer and the top silicon layer below the buried oxide layer, thereby forming a well region in the preset region of the top silicon layer. This saves one photomask in the process of forming the well region, thus reducing the fabrication cost of the pressure sensor. At the same time, the buried oxide layer in the cavity recess acts as a barrier layer. During ion implantation, the implanted ions are hindered by the buried oxide layer, increasing the scattering of the implanted ions into the lattice and preventing the implantation from directly aligning with the interstitial position of the lattice, thereby controlling the ion implantation depth.

[0062] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0063] Figures 2 to 10 This is a cross-sectional structural schematic diagram of each step of a method for reducing the manufacturing cost of a pressure sensor according to an embodiment of the present invention.

[0064] Please refer to Figure 2 Provides a first substrate.

[0065] The first substrate is specifically an SOI wafer, which includes a bottom silicon layer 100, a buried oxide layer 101 and a top silicon layer 102 stacked sequentially, with the surface a1 of the top silicon layer 102 and the bottom surface a2 of the bottom silicon layer 100 facing each other vertically.

[0066] Please refer to Figure 3 An oxide layer 103 is formed on the surface a1 of the top silicon layer 102.

[0067] A first cutting mark 104 is formed on the surface of the oxide layer 103, and the first cutting mark 104 penetrates the oxide layer 103 and the top silicon layer 102.

[0068] Specifically, the first dicing mark 104 is located at the dicing channel of the first substrate, that is, outside the main body of the pressure sensor. Since the pressure sensor, which is fabricated on the wafer, is diced through the dicing channel, the fabrication of the first dicing mark 104 will not damage the pressure sensor, and thus will not affect the performance of the pressure sensor.

[0069] The method for forming the first dicing mark 104 includes: spin-coating a photoresist layer on the first surface of the oxide layer 103; exposing and developing the photoresist layer using a photomask with a dicing mark pattern to form a patterned first mask layer, the first mask layer including an Nth dicing mark window pattern and a blocking area, the first dicing mark window pattern being located at the dicing path; using the first mask layer as a mask, sequentially etching the oxide layer 103 and the top silicon layer 102 until the first surface of the buried oxide layer 101 is exposed to form the first dicing mark 104; and removing the first mask layer after forming the first dicing mark 104.

[0070] It should be understood that the above example uses photoresist as the material of the first mask layer. In actual applications, the first mask layer can also be made of other materials and can be formed in other ways. This invention is not limited thereto.

[0071] Please refer to Figure 4 A first doped region 105 and a second doped region 106 are formed in a predetermined region i1 on the surface a1 of the top silicon layer 102.

[0072] The method for forming the first doped region 105 includes the following steps:

[0073] A photoresist layer is spin-coated on the first side of the oxide layer 103.

[0074] The photoresist layer is exposed and developed using a first photomask to pattern the photoresist layer, forming a patterned second mask layer. The patterned second mask layer includes a first doped window pattern and a blocking region. The first doped window pattern is located within a preset region i1, which is the device region of the pressure sensor.

[0075] Using the patterned second mask layer as a mask, P+ ion implantation is performed on the oxide layer 103 and the top silicon layer 102 within the first doped window pattern to form the first doped region 105 within the top silicon layer 102, as follows. Figure 4 As shown. The second doped region is a high-concentration P-type doped region, and the implanted ions for the P+ ions are trivalent impurity elements, specifically boron or gallium. The specific process for the second doped region is a common technique in the field and will not be elaborated here.

[0076] The method for forming the second doped region 106 includes the following steps:

[0077] After the first doped region 105 is prepared, the photoresist layer is exposed and developed using a second photomask to pattern the photoresist layer, forming a patterned third mask layer. The patterned third mask layer includes a second doped window pattern and a blocking region. The second doped window pattern is also located within the preset region i1.

[0078] Using the patterned third mask layer as a mask, P-ion implantation is performed on the oxide layer 103 and the top silicon layer 102 within the second doped window pattern to form the second doped region 106 within the top silicon layer 102, as follows. Figure 4 As shown. The second doped region is a low-concentration P-type doped region. The implanted ions for the P-ion implantation are trivalent impurity elements, specifically boron or gallium. The specific process for the second doped region is a common technique in the field and will not be elaborated here.

[0079] The surface of the oxide layer 103 is ashed to remove any remaining third mask layer after pickling.

[0080] The oxide layer 103 is subjected to thermal annealing to activate impurity atoms and repair lattice damage. The thermal annealing temperature is between 900℃ and 1000℃.

[0081] It should be noted that the surface of the oxide layer 103 can be thermally annealed uniformly after the formation of the first doped region 105 and the second doped region 106. Alternatively, thermal annealing can be performed separately during the formation of the first doped region 105 and the second doped region 106. Of course, the specific process can be selected according to requirements and is not limited here.

[0082] Please refer to Figure 5 The bottom silicon layer 100 is thinned from its bottom surface a2 to reduce the thickness of the first substrate.

[0083] Thinning the bottom silicon layer 100 includes the following steps:

[0084] Dry etching is performed on the bottom surface a2 of the bottom silicon layer 100 to reduce the thickness of the first substrate to a first preset thickness. The thinned bottom surface a2 of the bottom silicon layer 100 is then chemically and mechanically polished.

[0085] Specifically, the dry etching uses carbon tetrafluoride as the gas, the etching temperature is room temperature, and the pressure of the carbon tetrafluoride is 170-190 millitor. Of course, the specific dry etching conditions can be adjusted according to actual conditions, and are not considered factors limiting the scope of protection of this invention. Specifically, the first preset thickness is approximately 500 μm. Of course, those skilled in the art should recognize that there are many ways to thin the bottom silicon layer 100, and this invention is not limited to these methods.

[0086] Please continue to refer to this. Figure 6 After thinning the bottom silicon layer 100, a patterned mask layer 111 is formed on the bottom surface of the bottom silicon layer. The patterned mask layer 111 includes a cavity recess window pattern 112 and a blocking area. The cavity recess window pattern 112 corresponds vertically to the preset area i1, and the size of the cavity recess window pattern 112 is larger than the size of the preset area i1.

[0087] The preparation method for forming the mask layer 111 is the same as that for the first to third mask layers described above, and will not be repeated here.

[0088] Please refer to Figure 7 Using the patterned mask layer 111 as a mask, the underlying silicon 100 within the cavity recess window pattern 112 is etched to form the cavity recess 107, with the etching endpoint resting on the surface of the buried oxide layer 101.

[0089] Please refer to Figure 8 Using the patterned photolithography mask layer as a mask, ion implantation is performed on the preset well region position i2 of the top silicon layer from one side of the bottom silicon layer to form a well region 108. The preset well region position i2 corresponds vertically to the cavity groove 107.

[0090] Specifically, since the cavity groove 107 corresponds vertically to the preset region i1 and the size of the cavity groove window pattern 112 is larger than the size of the preset region i1, and since the preset well region position i2 corresponds vertically to the cavity groove 107 and the size of the preset well region position i2 is larger than the size of the preset position i1, the first doped region and the second doped region are located within the well region, thereby achieving the alignment of the device area of ​​the pressure sensor and ensuring the normal electrical performance of the pressure sensor.

[0091] Please refer to Figure 9 After forming the well region 108, the mask layer 111 is removed, and the well region 108 is thermally annealed. The removal of the photolithographic mask layer 111 and the thermal annealing of the well region 108 can be described with reference to the third mask layer, and will not be elaborated further here.

[0092] The ion implantation in the well region can be P-type ions or N-type ions; the first doped region and the second doped region 10 can be P-type doped regions or N-type doped regions.

[0093] As an example, the first doped region is a high-concentration P-type doped region, the second doped region is a low-concentration P-type doped region, and the well region ion implantation is N-type ion implantation.

[0094] Taking N-type ions as an example, the parameters for N-type ion implantation include: the implanted material must contain at least phosphorus ions, and the implantation dose must be at least 4e. 15 ions / cm 2 ~6e 15 ions / cm 2 The implantation energy is between 110 keV and 130 keV, and the ion implantation angle is between 6° and 8° off-vertical. Of course, the material, concentration, energy, and implantation angle of the N-type ion implantation can be adjusted according to actual needs and are not limited here.

[0095] Since the mask layer 111 used in forming the cavity recess 107 is used as a mask for N-type ion implantation, one photomask is saved during the formation of the well region 108, thereby reducing the device fabrication cost. Simultaneously, the buried oxide layer 101 within the cavity recess 107 acts as a barrier layer. During ion implantation, the implanted ions are hindered by the buried oxide layer, increasing the scattering of the implanted ions into the crystal lattice and preventing direct alignment of the implantation with interstitial lattice positions. This allows for control over the ion implantation depth.

[0096] Please refer to Figure 10 A second substrate 109 is provided, the second substrate 109 includes a first surface b1 and a second surface b2 that are opposite each other, and the first surface b1 of the second substrate 109 is bonded to the bottom surface a2 of the bottom silicon layer 100 to form a cavity structure 110.

[0097] Please refer to Figure 11 After forming the cavity structure 110, the second surface b2 of the second substrate 109 is thinned, and the thickness of the bonded wafer is thinned to a second preset thickness to form a pressure sensor.

[0098] Thinning the second surface b2 of the second substrate 109 includes the following steps:

[0099] Dry etching is performed on the second surface b2 of the second substrate 109 to reduce the thickness of the bonded wafer to a second preset thickness. For details regarding the specific etching gas and pressure used in the dry etching of the second surface b2 of the second substrate 109, please refer to the above description of dry etching of the second surface of the bottom silicon layer; these details will not be repeated here. Specifically, the second preset thickness is approximately 700 μm.

[0100] Of course, those skilled in the art should realize that there are many ways to thin the second substrate, and the present invention is not limited thereto.

[0101] In summary, the method for reducing the manufacturing cost of pressure sensors provided by this invention reuses the photolithographic mask layer forming the cavity groove to perform ion implantation on the top silicon layer. Therefore, one photomask is saved during the fabrication of the N-well region, thereby reducing the manufacturing cost of the pressure sensor. Simultaneously, the buried oxide layer within the cavity groove acts as a barrier layer. During ion implantation, the implanted ions are hindered by the buried oxide layer, increasing the scattering of the implanted ions into the crystal lattice and preventing direct alignment of the implantation with interstitial lattice positions. This allows for control over the ion implantation depth.

[0102] Please continue to refer to this. Figure 8 The present invention also provides a pressure sensor, the pressure sensor comprising a pressure sensor prepared by the above-described method for reducing the manufacturing cost of pressure sensors, the pressure sensor comprising:

[0103] A first substrate, comprising a bottom silicon layer 100, a buried oxide layer 101, and a top silicon layer 102 stacked sequentially.

[0104] The first doped region 105 and the second doped region 106 are both located within the preset region i1 of the top silicon layer 102.

[0105] Well region 108, which encloses the first doped region 105 and the second doped region 106 and fills the preset region i1;

[0106] A cavity structure 110 is located within the bottom silicon layer 100. The cavity structure 110 and the preset region i1 are vertically opposite each other, and the buried oxide layer 101 is exposed.

[0107] The second substrate 109 is bonded to the bottom surface b2 of the bottom silicon layer 100 to form the cavity structure of the pressure sensor.

[0108] The pressure sensor structure provided by this invention does not require an additional photomask to form the well region. The well region and the cavity are vertically aligned and aligned with the first doped region and the second doped region, which improves the alignment accuracy between the cavity and the device region. In the process of forming the well region, a photomask is saved, thereby reducing the manufacturing cost of the pressure sensor.

[0109] The materials, forming process, working principle, specific implementation method and beneficial effects of the pressure sensor structure in the embodiments of the present invention can be found in the preparation method of the pressure sensor in the embodiments of the present invention, and will not be repeated here.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for reducing the manufacturing cost of a pressure sensor, characterized in that, include: A first substrate is provided, comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; A first doped region and a second doped region are formed from one side of the top surface of the top silicon layer within a predetermined region of the top silicon layer; A patterned mask layer is formed on the bottom surface of the bottom silicon layer. The patterned mask layer includes a cavity recess window pattern and a blocking area. The cavity recess window pattern and the preset area are vertically corresponding, and the size of the cavity recess window pattern is larger than the size of the preset area. Using the patterned mask layer as a mask, the bottom silicon layer within the cavity groove window pattern is etched, and the etching endpoint stops at the surface of the buried oxide layer. Using the patterned mask layer as a mask, ion implantation is performed on the predetermined well region position of the top silicon layer from one side of the bottom surface of the bottom silicon layer to form a well region. The predetermined well region position corresponds vertically to the cavity groove. A second substrate is provided, and the bottom surface of the second substrate and the bottom silicon layer of the first substrate are bonded together to form a pressure sensor.

2. The method for reducing the manufacturing cost of pressure sensors according to claim 1, characterized in that, The ion implantation is N-type ion implantation, with parameters including: the implantation material is phosphorus, and the implantation dose is 4e. 15 ioNs / cm 2 ~6e 15 ioNs / cm 2 The injection energy is between 110 keV and 130 keV, and the ion injection angle is between 6° and 8° off the vertical direction.

3. The method for reducing the manufacturing cost of pressure sensors according to claim 1, characterized in that... Before forming the first doped region and the second doped region, the method further includes: An oxide layer is formed on the surface of the top silicon layer; A first cutting mark is formed at the surface edge of the oxide layer, and the cutting mark is located outside the body of the pressure sensor.

4. The method for reducing the manufacturing cost of pressure sensors according to claim 3, characterized in that, Before forming the cavity groove on the bottom surface of the bottom silicon layer, the method further includes: The bottom surface of the bottom silicon layer is thinned, and the thickness of the first substrate is reduced to a first preset thickness; The bottom surface of the thinned silicon layer is subjected to chemical mechanical polishing.

5. The method for reducing the manufacturing cost of a pressure sensor according to claim 4, characterized in that, The first preset thickness is within 500 μm.

6. The method for reducing the manufacturing cost of a pressure sensor according to claim 4, characterized in that, The second substrate includes a first surface and a second surface that are positioned vertically opposite each other. The first surface of the second substrate is bonded to the bottom surface of the bottom silicon layer of the first substrate. The substrate also includes: The second side of the second substrate is thinned, and the thickness of the bonded wafer is reduced to a second preset thickness; The second surface of the thinned second substrate is subjected to chemical mechanical polishing.

7. The method for reducing the manufacturing cost of a pressure sensor according to claim 6, characterized in that, The second preset thickness is within 700 μm.

8. The method for reducing the manufacturing cost of a pressure sensor according to claim 3, characterized in that, A first doped region is formed within the top silicon layer, specifically including: Photoresist is uniformly coated on the surface of the oxide layer; The photoresist is exposed, developed, and baked using a first photomask, which includes a P+ doped region window pattern region and a blocking region. P+ ion implantation is performed to form P+ doped regions.

9. The method for reducing the manufacturing cost of a pressure sensor according to claim 8, characterized in that, A second doped region is formed in a predetermined region within the top silicon layer, specifically including: The photoresist is exposed, developed, and baked using a second photomask, which includes a P-doped region window pattern area and a blocking region. P-ion implantation is performed to form a P-doped region; Remove the photoresist; Thermal annealing is performed to activate impurity atoms and repair lattice damage.

10. A pressure sensor, characterized in that, The pressure sensor includes one manufactured by the method for reducing the manufacturing cost of a pressure sensor as described in any one of claims 1 to 9, the pressure sensor comprising: A first substrate, comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; The first doped region and the second doped region are both located within the top silicon layer region; A well region that encloses the first doped region and the second doped region and completely fills the preset region; A cavity groove is located within the bottom silicon layer, with the cavity groove and the preset area being vertically opposite each other and exposing the buried oxide layer; A second substrate is bonded to the bottom surface of the bottom silicon layer to form the cavity structure of the pressure sensor.

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