Inductance type encoder and demodulation circuit and demodulation method applied to inductance type encoder

Abstract

The invention provides an inductive encoder, and a demodulation circuit and a demodulation method applied to the inductive encoder. The demodulation circuit comprises a clock signal generation circuit, a sampling hold circuit and a low-pass filter circuit. The clock signal generation circuit performs 90-degree phase shift on a signal to be demodulated, and generates a sample hold clock comprising a clock edge and a level hold state. The sampling and holding circuit samples a peak signal of the signal to be demodulated according to the clock edge and holds the peak signal in a level holding state; the amplitude of an envelope signal of a signal to be demodulated is reserved to the maximum extent, amplitude information of a modulation signal is removed to the maximum extent, and then a low-pass filtering circuit is used for carrying out low-pass filtering on a maintained peak signal to form an envelope demodulation signal and outputting the envelope demodulation signal. Compared with the prior art, the envelope demodulation signal obtained after demodulation has the advantages of being large in signal amplitude, small in signal distortion, small in signal delay and the like, and the application requirements of high precision, low delay and low noise of the inductive encoder can be met.

Description

Technical Field

[0001] The present application relates to the technical field of signal demodulation, and in particular to an inductive encoder and a demodulation circuit and a demodulation method applied thereto. Background Art

[0002] Encoders can be divided into photoelectric encoders, magnetic encoders, capacitive encoders and inductive encoders, etc. Among them, inductive encoders have the advantages of high precision, strong environmental adaptability, outstanding anti-magnetic field interference ability, compact structure and low electromagnetic interference.

[0003] The working principle of the inductive encoder is based on the inductive coupling between the transmitting coil, the target and the receiving coil. Through the sensor chip integrated in the encoder, its built-in LC oscillator works together with the transmitting coil to generate an electromagnetic field. In the receiving coil, this electromagnetic field induces a voltage signal related to the target rotor angle. The signal is in the form of an amplitude modulated wave, the carrier frequency is consistent with the LC oscillator frequency, and the amplitude variation of the amplitude modulation envelope is closely related to the target rotor angle.

[0004] At present, the amplitude modulated wave signal in the receiving coil of the inductive encoder mainly adopts envelope detection and synchronous demodulation and other demodulation methods. However, these demodulation methods all have different defects. For example, although the circuit structure of envelope detection is simple, the envelope signal obtained by its demodulation will show obvious attenuation due to the forward voltage drop of the diode, and even lead to disadvantages such as serious signal distortion and increased delay. Similarly, the envelope signal obtained by synchronous demodulation also has problems such as large voltage drop attenuation, low signal-to-noise ratio and large signal delay. These defects limit the use of inductive encoders in applications that require high precision, low delay and low noise. Summary of the invention

[0005] The present application proposes an inductive encoder and a demodulation circuit and a demodulation method applied thereto, which utilize 90° phase shift, peak sampling and holding, and low-pass filtering technology to ensure that the demodulated signal has the characteristics of high signal amplitude, low distortion, and low delay, thereby meeting the requirements of the inductive encoder in high-precision, low-delay, and low-noise applications.

[0006] This application provides the following technical solutions:

[0007] A demodulation circuit applied to an inductive encoder, comprising:

[0008] A clock signal generating circuit, used for performing a 90° phase shift on the input signal to be demodulated to generate a sampling and holding clock, wherein the sampling and holding clock includes a clock edge and a level holding state;

[0009] A sampling and holding circuit, used for sampling the peak signal of the signal to be demodulated according to the clock edge, and holding the peak signal in the level holding state;

[0010] The low-pass filter circuit is used for performing low-pass filtering on the retained peak signal to form an envelope demodulation signal and output it.

[0011] Optionally, the clock edge includes a rising edge and a falling edge; the level holding state includes a high level holding state and a low level holding state;

[0012] The sampling and holding circuit includes a sampling circuit and a holding circuit; the sampling circuit is used to sample the first peak signal of the signal to be demodulated according to the rising edge, and to sample the second peak signal of the signal to be demodulated according to the falling edge; the holding circuit includes a positive envelope holding circuit and a negative envelope holding circuit; wherein the positive envelope holding circuit is used to hold the first peak signal in the high level holding state; the negative envelope holding circuit is used to hold the second peak signal in the low level holding state; the first peak signal is any one of the positive peak signal and the negative peak signal, and the second peak signal is the other of the positive peak signal and the negative peak signal;

[0013] The low-pass filter circuit includes a first low-pass filter circuit and a second low-pass filter circuit; the first low-pass filter circuit is used to perform low-pass filtering on the maintained first peak signal to form a positive envelope demodulation signal and output it; the second low-pass filter circuit is used to perform low-pass filtering on the maintained second peak signal to form a negative envelope demodulation signal and output it.

[0014] Optionally, the sampling circuit includes a first switch, a second switch, a third switch, a fourth switch and a first capacitor;

[0015] Among them, one end of the first switch is connected to the output end of the clock signal generating circuit and connected to the signal to be demodulated, the other end of the first switch is connected to one end of the second switch and one end of the first capacitor; the other end of the second switch is connected to a reference voltage; the other end of the first capacitor is connected to one end of the third switch and one end of the fourth switch; the other end of the third switch is connected to a reference voltage; the other end of the fourth switch is connected to the input end of the holding circuit;

[0016] When the first switch and the third switch are turned on, and the second switch and the fourth switch are turned off, the peak signal of the signal to be demodulated is sampled through the first capacitor.

[0017] Optionally, the positive envelope holding circuit includes a fifth switch and a second capacitor; wherein one end of the fifth switch is connected to the output end of the sampling circuit, the other end of the fifth switch is connected to one end of the second capacitor and the input end of the first low-pass filter circuit, and the other end of the second capacitor is grounded; the fifth switch is used to be turned on when the clock edge is the rising edge, so that the second capacitor maintains the first peak signal of the signal to be demodulated;

[0018] The negative envelope holding circuit includes a sixth switch and a third capacitor; wherein one end of the sixth switch is connected to the output end of the sampling circuit, the other end of the sixth switch is connected to one end of the third capacitor and the input end of the second low-pass filter circuit, and the other end of the third capacitor is grounded; the sixth switch is used to be turned on when the clock edge is the falling edge, so that the third capacitor holds the second peak signal of the signal to be demodulated.

[0019] Optionally, the demodulation circuit further includes a sampling and holding amplifier circuit connected between the sampling circuit and the holding circuit;

[0020] The sampling and holding amplifier circuit includes an operational amplifier and a fourth capacitor, wherein the non-inverting input terminal of the operational amplifier is connected to the other end of the fourth switch, the inverting input terminal of the operational amplifier is connected to a reference voltage, and the output terminal of the operational amplifier is connected to the input terminal of the holding circuit; the fourth capacitor is connected between the non-inverting input terminal of the operational amplifier and the output terminal of the operational amplifier;

[0021] When the first switch and the third switch are disconnected and the second switch and the fourth switch are turned on, the peak signal sampled by the first capacitor is amplified by the operational amplifier, and the amplification factor of the operational amplifier is adjusted by the fourth capacitor.

[0022] Optionally, the clock signal generating circuit includes a phase shift circuit and a comparator connected to each other, wherein the phase shift circuit is used to perform a 90° phase shift on the signal to be demodulated, and the comparator is used to perform a zero-crossing comparison on the signal after the phase shift circuit is phase-shifted to generate the sampling and holding clock.

[0023] Optionally, the phase shift circuit includes an RC phase shift network, wherein the RC phase shift network is an advanced phase shift network, and the RC phase shift network includes a first phase shift resistor and a first phase shift capacitor, one end of the first phase shift capacitor is used to access the signal to be demodulated, the other end of the first phase shift capacitor is connected to one end of the first phase shift resistor and the in-phase input end of the comparator, and the other end of the first phase shift resistor is connected to the power supply end; wherein, when the frequency of the signal to be demodulated is between 2MHz and 5MHz, the RC constant formed by the first phase shift resistor and the first phase shift capacitor is not greater than 1.03×10 -8, so that the phase shift deviation of the RC phase shift network to the signal to be demodulated is no more than 5% of the period of the signal to be demodulated;

[0024] Alternatively, the RC phase shift network is a hysteresis phase shift network, the RC phase shift network includes a second phase shift resistor and a second phase shift capacitor, one end of the second phase shift resistor is used to access the signal to be demodulated, the other end of the second phase shift resistor is connected to one end of the second phase shift capacitor and the in-phase input end of the comparator, and the other end of the second phase shift capacitor is grounded; wherein, when the frequency of the signal to be demodulated is between 2MHz and 5MHz, the RC constant formed by the second phase shift resistor and the second phase shift capacitor is not less than 2.45×10 -7 , so that the phase shift deviation of the RC phase shift network to the signal to be demodulated is no more than 5% of the period of the signal to be demodulated.

[0025] Optionally, the phase shift circuit includes a phase-locked loop circuit, wherein the phase-locked loop circuit includes a phase detector, a low-pass filter loop, a voltage-controlled oscillator and a frequency divider; the phase detector is used to form a 90° phase difference signal according to the input signal to be demodulated, and the low-pass filter loop is used to low-pass filter the phase difference signal; the voltage-controlled oscillator is used to generate an oscillation signal, wherein the frequency of the oscillation signal is the same as the frequency of the signal to be demodulated, and the phase of the oscillation signal differs from the phase of the signal to be demodulated by 90°; or

[0026] The phase shift circuit includes a delay phase-locked loop circuit, wherein the delay phase-locked loop circuit includes a phase comparison circuit and a delay circuit; wherein the phase comparison circuit is used to perform phase comparison between the signal to be demodulated and the phase-shifted signal output by the delay circuit, and control the delay circuit according to the comparison result so that the delay circuit converts the input signal to be demodulated into a 90° phase-shifted signal.

[0027] The present application also provides a demodulation method applied to an inductive encoder, comprising:

[0028] Generate a sampling and holding clock with a 90° phase shift according to the input signal to be demodulated, wherein the sampling and holding clock includes a clock edge and a level holding state;

[0029] According to the clock edge, sampling the peak signal of the signal to be demodulated;

[0030] Maintaining the peak signal in the level holding state;

[0031] The retained peak signal is low-pass filtered to form an envelope demodulation signal and output.

[0032] The present application also provides an inductive encoder, comprising:

[0033] A sensor chip, wherein the sensor chip includes an oscillator;

[0034] A transmitting device and a receiving device, wherein a target rotor to be detected is arranged between the transmitting device and the receiving device; the transmitting device and the oscillator jointly generate an electromagnetic field, and the receiving device generates an amplitude modulated wave signal related to the angle of the target rotor according to the electromagnetic field induction; and based on any one of the demodulation circuits applied to the inductive encoder as described above, the demodulation circuit applied to the inductive encoder demodulates the amplitude modulated envelope signal to obtain an envelope demodulation signal.

[0035] Compared with the prior art, the present invention has at least one of the following advantages:

[0036] The present application generates a sampling and holding clock by performing a 90° phase shift on the demodulated signal through a clock signal generating circuit, so that the signal sampling can be accurately triggered at the edge of the sampling and holding clock, thereby performing synchronous sampling and holding at the peak point of the signal. For example, in the case of a 90° phase shift ahead, the positive peak value of the envelope (i.e., the positive peak value of the amplitude modulation signal) can be synchronously sampled at the falling edge of the clock, and the negative peak value of the envelope (i.e., the negative peak value of the amplitude modulation signal) can be synchronously sampled at the rising edge of the clock. This method can maximize the retention of the amplitude of the envelope signal in the demodulated signal, significantly reduce the amplitude attenuation during the demodulation process, thereby meeting the requirements of high-precision applications. At the same time, the method can also effectively remove the modulation signal component, so that the modulation signal energy in the sampled signal is extremely small, so that efficient filtering can be completed without relying on a filter with extremely low bandwidth, and therefore the signal delay can be extremely low, so as to be controlled within 1us. The present application not only avoids the large delay problem that occurs during the filtering process of the envelope signal, but also significantly improves the delay characteristics of the envelope signal, thereby meeting the requirements of high-precision and high-real-time application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is the principle diagram of the diode half-wave detection circuit in the prior art;

[0039] Figure 2 It is a schematic diagram of synchronous demodulation steps in the prior art;

[0040] Figure 3 It is a schematic diagram of an amplitude modulated wave envelope demodulation method applied to an inductive encoder in an embodiment of the present application;

[0041] Figure 4 is a schematic diagram of the steps of generating a sampling and holding clock in an embodiment of the present application;

[0042] Figure 5 is a schematic diagram of a demodulation circuit in an embodiment of the present application;

[0043] Figure 6 It is a schematic diagram of a positive peak signal and a negative peak signal separation and demodulation circuit in an embodiment of the present application;

[0044] Figure 7 It is a connection diagram of a sampling circuit, a sampling and holding amplifier circuit, and a holding circuit in an embodiment of the present application;

[0045] Figure 8 is a schematic diagram of a clock signal generating circuit including an advanced phase shift network in an embodiment of the present application;

[0046] Fig. 9 is a schematic diagram of a clock signal generating circuit including a lagging phase shift network in an embodiment of the present application;

[0047] Fig.10 is a schematic diagram of a phase-locked loop circuit in an embodiment of the present application;

[0048] Fig.11 is a schematic diagram of a delay-locked loop circuit in an embodiment of the present application;

[0049] Fig.12 It is a step diagram of a demodulation method applied to an inductive encoder in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0052] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0053] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0055] The receiving coil of the inductive encoder receives an amplitude modulated wave signal, that is, the transmitting coil of the inductive encoder transmits a high-frequency carrier signal. After passing through the target rotor, the receiving coil receives an amplitude modulated signal. It is necessary to demodulate the envelope from the amplitude modulated signal to obtain the angle corresponding to the target rotor from the envelope signal. The existing demodulation schemes mainly include envelope detection and synchronous demodulation.

[0056] The envelope detection method consists of half-wave / full-wave rectification and LPF. Figure 1 The schematic diagram of the diode half-wave detection circuit is shown, which consists of a diode D, a resistor R and a capacitor C. Although the envelope detection circuit is simple, the signal detected by the envelope detection circuit has a significant attenuation in amplitude due to the forward voltage drop of the diode, and the signal distortion is also large. In addition, a large signal delay is generated after low-pass filtering by a low-pass filter (LPF).

[0057] refer to Figure 2As shown in the figure, the synchronous demodulation method is to first perform synchronous clock recovery based on the carrier signal of the amplitude modulated wave, and then decompose the amplitude modulated signal into a differential amplitude modulated signal diagram through the synchronous clock, and then filter the carrier signal through a low-pass filter to obtain a complete signal envelope. Although the carrier envelope signal obtained by synchronous demodulation is of high quality and has low signal distortion, the detected envelope signal is also greatly attenuated due to low-pass filtering, resulting in a decrease in the signal-to-noise ratio. In addition, in order to filter out the carrier signal, the 3dB bandwidth of the low-pass filter is set low, resulting in a large signal delay (usually more than 10us), which affects the high-speed application of the encoder. In addition, due to the large amplitude of the carrier signal, after passing through the low-pass filter, the envelope signal output has a ripple signal generated by the residual carrier, which is also manifested as a decrease in the signal-to-noise ratio.

[0058] In summary, the envelope signal obtained by the existing envelope detection and synchronous demodulation cannot meet the application requirements of the inductive encoder in high-precision, low-latency, low-noise and other high-application scenarios.

[0059] To this end, this application provides a new idea for amplitude modulation wave envelope demodulation: Figure 3 As shown in the figure, compared with the original envelope detection and synchronous demodulation scheme, this scheme directly samples the peak amplitude signal of the amplitude modulated wave to achieve demodulation, wherein the carrier signal is first phase-shifted by 90° to form a sampling and holding clock, and then the sampling and holding clock is used to perform peak sampling and holding on the carrier signal. Since the sampling and holding clock is a clock signal obtained after the original carrier signal is phase-shifted by 90°, the peak position of the carrier signal is exactly aligned with the edge position of the clock. For example, when the phase shift is advanced by 90°, the rising edge of the clock is exactly aligned with the negative peak position, and the falling edge of the clock is exactly aligned with the positive peak position, while the situation is just the opposite when the phase shift is lagged by 90°. In this way, using the edge trigger of the clock for peak sampling will inevitably accurately use the 90° phase shift position of the carrier frequency to collect the carrier signal, thereby achieving accurate sampling of the peak value of the carrier signal. After peak sampling, the positive peak signal and the negative peak signal are respectively maintained in the level holding state of the sampling and holding clock. The waveforms of the maintained positive peak signal and negative peak signal are as shown in the figure. Figure 3 As shown in the waveform ② in the figure. Finally, the positive peak signal and the negative peak signal are kept and then low-pass filtered to obtain the ideal envelope demodulation signal. The ideal envelope waveform obtained after filtering is as follows: Figure 3 As shown in the waveform ③.

[0060] Therefore, compared with the previous two methods, the demodulation scheme of the present application has the following advantages:

[0061] 1. After the AM wave signal is demodulated, the amplitude of the obtained envelope demodulation signal is basically lossless, with the advantages of large signal amplitude, small signal distortion and low noise;

[0062] 2. After peak sampling and holding, the amplitude energy of the carrier signal within the bandwidth is very small, and there is no need to design a low-pass filter with very low bandwidth. Therefore, the signal delay can be very small and the delay can be controlled within 1us;

[0063] 3. In the application of inductive encoders, it can also be combined with back-end high-precision analog-to-digital conversion (AD) sampling and angle digital algorithms to meet high-precision and high-speed encoder applications.

[0064] In implementation, the new plan mainly involves the following three aspects:

[0065] 1. Generate the sampling and holding clock required for sampling and holding according to the peak position of the amplitude modulated wave signal.

[0066] refer to Figure 4 It is shown that although the clock in the new scheme is also recovered from the carrier signal (referred to as the AM wave signal to be demodulated, the signal to be demodulated, etc. in this article, without distinction), it is different from the clock generated by the original synchronous demodulation scheme. The clock in the new scheme is 90° phase-shifted with the carrier signal, so that the edge of the clock is exactly aligned with the peak value of the carrier signal, so that the edge of the clock can be used for sampling and the level holding state of the clock can be used for holding operations, thereby accurately retaining the peak value of the carrier signal.

[0067] It should be noted that the phase shift operation can be a 90° leading phase shift or a 90° lagging phase shift. As long as the phase shift mode is determined, the corresponding clock edge can be used for sample-and-hold operation. Figure 3 Schematic diagram), the rising edge of the clock is exactly aligned with the negative peak position of the carrier, and the falling edge of the clock is exactly aligned with the positive peak position of the carrier, so the rising edge can be used to sample the negative peak, and the falling edge can be used to sample the positive peak. The high level hold state maintains the negative peak signal, and the low level hold state maintains the positive peak signal. The lagging phase shift situation can be operated in the opposite way to the leading phase shift.

[0068] 2. Sample and hold the peak value of the AM wave signal.

[0069] Since there are many sampling and holding methods in the prior art, the existing sampling and holding circuit or the sampling and holding circuit described in the example below can be used, and the sampling and holding clock generated as above can be used to perform high-precision and low-delay sampling and holding on the peak value of the amplitude modulated wave signal.

[0070] 3. Perform low-pass filtering on the peak waveform after sampling and holding to obtain the envelope.

[0071] Similarly, there are many low-pass filtering methods in the prior art, such as active filtering, passive filtering, digital filtering, etc., so the existing low-pass filtering method can be used to filter the peak signal of the sampled and held signal, so as to obtain a demodulated envelope with small distortion and small delay. It should be noted that in this application, since the amplitude capacity of the carrier signal within the bandwidth is very small after being sampled and held, a low-pass filter with very low bandwidth is not required.

[0072] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0073] like Figure 5 As shown, a demodulation circuit applied to an inductive encoder may include a clock signal generating circuit 10 , a sampling and holding circuit 20 , and a low-pass filtering circuit 30 .

[0074] The clock signal generating circuit 10 has an input end and an output end, wherein the input end of the clock signal generating circuit 10 receives the signal to be demodulated, the clock signal generating circuit 10 performs a 90° phase shift on the signal to be demodulated received at the input end, and then performs a zero crossing comparison on the signal to be demodulated that has undergone a 90° phase shift, generates a sampling and holding clock, and outputs the sampling and holding clock at the output end of the clock signal generating circuit 10.

[0075] As analyzed above, because there is a 90° phase shift relationship between the clock signal and the carrier signal, the edge of the clock signal can be synchronously aligned with the peak position of the carrier signal, making it convenient to use the clock signal to perform sampling and holding operations on the peak amplitude of the carrier signal.

[0076] The sampling and holding circuit 20 has an input terminal, an output terminal and a control terminal, wherein the input terminal of the sampling and holding circuit 20 receives the signal to be demodulated and enters the sampling and holding circuit 20, the control terminal is coupled to the output terminal of the clock signal generating circuit 10, receives the sampling and holding clock, and the sampling and holding circuit 20 includes two stages of sampling and holding, wherein in the sampling stage, under the edge of the sampling and holding clock, such as the 90° phase shift in advance in the above example, the negative peak value and the positive peak value of the signal to be demodulated can be sampled at the rising edge and the falling edge of the sampling and holding clock respectively, and then in the holding stage, the sampling result of the peak value is correspondingly held in the level holding state of the sampling and holding clock. Therefore, after the sampling and holding operation is performed using the sampling and holding clock, the sampling results of the positive peak value and the negative peak value of the signal to be demodulated can be output at the output terminal of the sampling and holding circuit 20.

[0077] The low-pass filter circuit 30 has an input end and an output end, wherein the input end of the low-pass filter circuit 30 is coupled to the output end of the sampling and holding circuit 20, and receives the sampling result of the positive peak value and the negative peak value of the demodulated signal output by the sampling and holding circuit 20. The low-pass filter circuit 30 is used to perform low-pass filtering on the signal output by the sampling and holding circuit 20, and output the envelope demodulation signal at the output end of the low-pass filter circuit 30. Therefore, the low-pass filter only needs to filter the peak sampling result, and there is basically no other relevant information of the carrier in the sampling result, and the carrier energy can be basically ignored, so the design of the low-pass filter is no longer subject to too many constraints, and a common low-pass filter can be used, which simplifies the filter circuit, and can also obtain an ideal demodulation envelope waveform, ensuring the overall performance. At the same time, the signal delay can be made very small, and the delay can be controlled within 1us.

[0078] The present application generates a sampling and holding clock by performing a 90° phase shift on the signal to be demodulated through a clock signal generating circuit. The sampling and holding circuit responds to the sampling and holding clock. Under the edge of the sampling and holding clock, the signal to be demodulated is sampled. Peak sampling can be accurately performed at the peak point of the signal to be demodulated, thereby retaining the amplitude of the envelope signal of the signal to be demodulated to the maximum extent and removing the amplitude information of the modulation signal to the maximum extent. Moreover, the amplitude energy of the signal obtained after peak sampling and holding is very small within the band, and a filter with very low bandwidth is not required for filtering processing, so that the delay of the envelope demodulated signal obtained after processing by the filtering circuit is very small.

[0079] In one embodiment, if Figure 6 As shown, the holding circuit 22 includes a positive envelope holding circuit 221 and a negative envelope holding circuit 222, which can separate and hold the positive and negative envelopes, making it convenient for subsequent circuits to process the positive and negative envelope signals.

[0080] For the sampling result output by the sampling circuit 21 , the peak sampling result is separated and held by the positive envelope holding circuit 221 and the negative envelope holding circuit 222 .

[0081] Specifically, the holding circuit 22 includes a positive envelope holding circuit 221 and a negative envelope holding circuit 222; wherein the input end of the positive envelope sampling circuit 221 receives the sampling result outputted from the output end of the sampling circuit 21; the control end of the positive envelope sampling circuit 221 is coupled to the output end of the clock signal generating circuit 10, and receives the sampling holding clock; the positive envelope holding circuit 221 is used to hold the signal outputted from the sampling circuit 21 under the action of the rising edge of the sampling holding clock, obtain the positive envelope sampling result, and output the positive envelope sampling result from the output end of the positive envelope holding circuit 21 after holding the positive envelope sampling result. The input end of the negative envelope holding circuit 222 receives the sampling result outputted from the output end of the sampling circuit 21; the control end of the negative envelope holding circuit 222 is coupled to the output end of the clock signal generating circuit 10, and receives the sampling holding clock; the negative envelope holding circuit 222 is used to hold the signal outputted from the sampling circuit 21 under the action of the falling edge of the sampling holding clock, obtain the negative envelope sampling result, and output the negative envelope sampling result from the output end of the negative envelope holding circuit 222 after holding the negative envelope sampling result.

[0082] The positive envelope holding circuit 221 and the negative envelope holding circuit 222 can separate the positive and negative peak values ​​of the previous stage sampling result, so as to facilitate the circuit processing of the positive peak value and the negative peak value in the later stage.

[0083] It should be noted that the positive envelope holding circuit 221 is limited to using rising edge trigger sampling and holding, and the negative envelope holding circuit 222 is limited to using falling edge trigger sampling and holding. It should be understood by those skilled in the art that, in combination with the above exemplary explanation of the leading phase shift and lagging phase shift, it can be known that: under the leading phase shift, the positive envelope holding circuit 221 may use the rising edge sampling and holding to obtain a negative peak value, and the negative envelope holding circuit 222 may use the falling edge trigger sampling and holding to obtain a positive peak value, while the lagging phase shift situation is just the opposite. Therefore, whether the separation is a positive peak sampling result or a negative peak sampling result can be determined in combination with the specific phase shift of the clock. The positive and negative examples are used here for convenience of understanding and should not constitute a restrictive understanding.

[0084] The low-pass filter circuit 30 includes a first low-pass filter circuit 31 and a second low-pass filter circuit 32, wherein the input end of the first low-pass filter circuit 31 receives a positive envelope sampling result, and the first low-pass filter circuit 31 is used to perform low-pass filtering on the positive envelope sampling result output by the positive envelope holding circuit 221 to form a positive envelope output; the input end of the first low-pass filter circuit 32 receives a negative envelope sampling result, and the second low-pass filter circuit 32 is used to perform low-pass filtering on the negative envelope sampling result output by the negative envelope holding circuit 222 to form a negative envelope output.

[0085] like Figure 7As shown, in one embodiment, the sampling circuit 21 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a first capacitor C1 (sampling capacitor); one end of the first switch S1 is connected to the output end of the clock signal generating circuit 10 and is connected to the signal to be demodulated, the other end of the first switch S1 is connected to one end of the second switch S2 and one end of the first capacitor C1, and the other end of the second switch S2 is connected to a reference voltage (such as a high-precision reference reference Vref); the other end of the first capacitor C1 is connected to one end of the third switch S3 and one end of the fourth switch S4; the other end of the third switch S3 is connected to a reference voltage (such as a high-precision reference reference Vref); the other end of the fourth switch S4 is connected to the input end of the holding circuit 42.

[0086] The specific situation of the sampling circuit 21 sampling the peak value of the demodulated signal is that the first switch S1 and the third switch S3 are used to be turned on under the triggering of the rising edge of the sampling and holding clock, and the second switch S2 and the fourth switch S4 are disconnected, so that the first capacitor C1 is used to sample the first peak signal of the demodulated signal; the first switch S1 and the third switch S3 are used to be turned on under the triggering of the falling edge of the sampling and holding clock, and the second switch S2 and the fourth switch S4 are disconnected, so that the first capacitor C1 is used to sample the second peak signal of the demodulated signal. The peak signal of the demodulated signal is sampled by the first capacitor C1, and then the first peak signal and the second peak signal, that is, the positive peak signal and the negative peak signal, are output from the output port of the sampling circuit 21. Specifically, the first peak signal is any one of the positive peak signal and the negative peak signal, and the second peak signal is the other of the positive peak signal and the negative peak signal.

[0087] In one embodiment, considering that the peak sampling amplitude of the amplitude modulation signal varies, a sampling and amplification circuit may be used to perform the sampling and holding process.

[0088] In one embodiment, the holding circuit 22 may be in the form of a simple “switch+capacitor” circuit.

[0089] like Figure 7 As shown, the positive envelope holding circuit 221 includes a fifth switch S5 and a second capacitor C2; wherein one end of the fifth switch S5 is connected to the output end of the sampling circuit 21, the other end of the fifth switch S5 is connected to one end of the second capacitor C2 and the input end of the first low-pass filter circuit 31, and the other end of the second capacitor C2 is grounded, and the fifth switch S5 is used to be turned on when the clock edge is a rising edge, and in a high level holding state, so that the second capacitor C2 holds the first peak signal of the demodulated signal;

[0090] The negative envelope holding circuit 222 includes a sixth switch S6 and a third capacitor C3; wherein, the input end of the sixth switch S6 is connected to the output end of the sampling circuit 21, the other end of the sixth switch S6 is connected to one end of the third capacitor C3 and the input end of the second low-pass filter circuit 32, and the other end of the third capacitor C3 is grounded. The sixth switch S6 is used to be turned on when the clock edge is a falling edge, and in a low-level holding state, the third capacitor C3 maintains the second peak signal of the demodulated signal.

[0091] The holding function can be realized by a holding circuit in the form of a switched capacitor, and the circuit form is simple.

[0092] like Figure 7 As shown, the demodulation circuit also includes a sampling and holding amplifier circuit 40 connected between the sampling circuit 21 and the holding circuit 22, wherein the sampling and holding amplifier circuit 40 includes an operational amplifier 41 and a fourth capacitor C4, the non-inverting input terminal of the operational amplifier 41 is connected to the other end of the fourth switch S4, the reverse input terminal of the operational amplifier 41 is connected to the reference voltage, and the output terminal of the operational amplifier 41 is connected to the input terminal of the holding circuit 22; the fourth capacitor C4 is connected between the non-inverting input terminal of the operational amplifier 41 and the output terminal of the operational amplifier 41;

[0093] When the first switch S1 and the third switch S3 are disconnected, and the second switch S2 and the fourth switch S4 are turned on, the peak signal sampled by the first capacitor C1 is amplified by the operational amplifier 41, and the amplification factor of the operational amplifier is adjusted by the fourth capacitor C4. In addition, the amplification factor of the operational amplifier 41 can be flexibly adjusted by setting the first capacitor C1 of the sampling circuit 21. The sampling and holding amplifier circuit 40 amplifies and holds the sampling result at the same time, and the DC offset of the sampling and holding amplifier circuit 40 can be offset by the system, and the DC offset of the operational amplifier 41 has no effect on the subsequent signal output.

[0094] In one embodiment, the amplification factor of the operational amplifier 41 can preferably range from 1 to 5 times. By selecting a suitable amplification factor, it can be ensured that the sampling result is properly amplified, and large signals will not be saturated and distorted, thereby ensuring signal distortion. Small signals can also be reasonably amplified, thereby improving the signal-to-noise ratio.

[0095] In one embodiment, the reference voltage preset in the circuit is preferably a high-precision, high-stability reference voltage, such as a reference voltage Vref obtained by a reference power supply. By adopting a high-precision, high-stability reference potential, the stability and accuracy of the sampling and holding can be guaranteed, and the signal-to-noise ratio can be improved.

[0096] In one embodiment, when generating a clock, a phase shift-related circuit may be used to implement a 90° phase shift operation.

[0097] In practice, the clock signal generating circuit 10 adopts a circuit form of a phase shift circuit + a comparator.

[0098] like Figure 8 and Fig. 9 As shown (the phase shift circuit 11 is shown as an RC phase shift network), the clock signal generating circuit 10 includes a phase shift circuit 11 and a comparator 12, wherein the phase shift circuit 11 is used to perform a 90° phase shift (such as overtime or lag) on ​​the signal to be demodulated, and the comparator 12 is used to perform a zero-crossing comparison on the signal after the phase shift circuit 11 is phase-shifted to generate a sampling and holding clock. It should be noted that the phase shift can be completed on the analog signal first, and then the comparator is used to form the clock.

[0099] In one embodiment, the phase shift circuit 11 includes an RC phase shift network, wherein the RC phase shift network may be a leading phase shift network (eg, Fig. 9 as shown) or a delayed phase shift network (as Fig.10 shown).

[0100] like Figure 8 As shown, when the RC phase shift network is an advanced phase shift network, the advanced phase shift network includes a first phase shift resistor R5 and a first phase shift capacitor C5, one end of the first phase shift capacitor C5 is used to access the signal to be demodulated, the other end of the first phase shift capacitor C5 is connected to one end of the first phase shift resistor R5 and the in-phase input end of the comparator 12, and the other end of the first phase shift resistor R5 is connected to the power supply end.

[0101] When the frequency of the demodulated signal is between 2 MHz and 5 MHz, the RC constant formed by the first phase-shift resistor R5 and the first phase-shift capacitor C5 is not greater than 1.03×10 -8 , so that the phase shift deviation of the demodulated signal by the leading phase shift network is no more than 5% of the period of the demodulated signal.

[0102] Specifically, when the phase shift circuit 11 is an advanced phase shift network, the transfer function of the RC advanced phase shift circuit can be expressed as:

[0103]

[0104] Where H(s) is the transfer function, R and C are the phase shift network parameters, ω is the angular frequency, ω = 2πf (f is the carrier frequency);

[0105] Therefore, the phase advance radian α can be expressed as:

[0106]

[0107] And, the amplitude gain is expressed as:

[0108]

[0109] In summary, when the lead phase shift network is used for lead shifting, when the input signal frequency is between 2 and 5MHz, the required sampling deviation is controlled to be 5% of the period (that is, 0.05T; for a sampling frequency of 5MHz, the phase shift deviation is controlled to be 10ns). In order to ensure that the time difference between the real waveform after RC phase shift and the ideal waveform after 90° phase shift is less than 0.05T, the phase shift amount θ after the RC phase shifter must not be less than:

[0110]

[0111] That is:

[0112]

[0113] Therefore, when ω=2πf=2π·5MHz, RC≤1.03×10 －8 At this time, it can be ensured that the carrier frequency can meet the demand when it changes between 2 and 5 MHz.

[0114] like Fig. 9 As shown, when the RC phase shift network is a hysteresis phase shift network, the hysteresis phase shift network includes a second phase shift resistor R6 and a second phase shift capacitor C6, one end of the second phase shift resistor R6 is used to access the signal to be demodulated, the other end of the second phase shift resistor R6 is connected to one end of the second phase shift capacitor C6 and the in-phase input end of the comparator 12, and the other end of the second phase shift capacitor C6 is grounded.

[0115] When the frequency of the demodulated signal is between 2MHz and 5MHz, the RC constant formed by the second phase-shift resistor R6 and the second phase-shift capacitor C6 is not less than 2.45×10 -7 , so that the phase shift deviation of the signal to be demodulated by the lagging phase shift network is no more than 5% of the period of the signal to be demodulated;

[0116] Specifically, when the phase shift circuit 11 is a lagging phase shift network, the transfer function of the lagging phase shift network can be expressed as:

[0117]

[0118] The phase lag radian β can be expressed as:

[0119] β=-tan -1 (ωRC)

[0120] The amplitude gain is expressed as:

[0121]

[0122] Therefore, when using a lagging phase shift network for lagging shifting, in order to ensure that the time difference between the real waveform after phase shift and the ideal waveform after 90° phase shift is less than 0.05T, the phase shift θ after the RC phase shifter shall not be greater than:

[0123]

[0124] That is:

[0125]

[0126] In summary, when ω=2πf=2π·2M, RC≥2.45×10 －7 At this time, it can be ensured that the carrier frequency can meet the requirements when it changes between 2 and 5 MHz.

[0127] In one embodiment, the phase shift circuit 11 may be in the form of a phase-locked loop circuit.

[0128] like Fig.10 As shown, the phase shift circuit 11 adopts a frequency division phase-locked phase-locked loop circuit, wherein the phase-locked loop circuit includes a frequency divider 1121, a phase detector 1122, a low-pass filter 1123, a voltage-controlled oscillator 1124, a fractional frequency divider 1125, and two counters 1126; the frequency divider 1121 is used to divide the input signal to be demodulated to obtain F1, the phase detector 1122 is used to form a 90° phase difference signal according to the input signal to be demodulated after the frequency division, and the low-pass filter 1123 is used to low-pass filter the phase difference signal; the voltage-controlled oscillator 1124 is used to generate an oscillation signal, wherein the frequency of the oscillation signal is the same as the frequency of the signal to be demodulated, and the phase of the oscillation signal differs from the phase of the signal to be demodulated by 90°. The fractional frequency divider 1125 and the two counters 1126 are arranged in the feedback circuit to maintain the resolution of the input signal to be demodulated F1 after the frequency division.

[0129] like Fig.11 As shown, the phase shift circuit 11 adopts a delay phase-locked loop circuit, wherein the delay phase-locked loop circuit includes a phase comparison circuit 1111 and a variable delay circuit 1112; wherein the phase comparison circuit 1111 is used to compare the phases of the signal to be demodulated and the phase-shifted signal output by the variable delay circuit 1112, and control the variable delay circuit 1112 according to the comparison result, so that the variable delay circuit 1112 converts the input signal to be demodulated into a 90° phase-shifted signal.

[0130] Based on the same inventive concept, the present application also provides a demodulation method for an inductive encoder corresponding to the aforementioned circuit embodiment, such as Fig.12 As shown, the following steps are included:

[0131] S1, generating a 90° phase-shifted sampling and holding clock according to the input signal to be demodulated, the sampling and holding clock including a clock edge and a level holding state;

[0132] S2. sampling the peak signal of the signal to be demodulated according to the clock edge;

[0133] S3, maintaining the peak signal in the level maintaining state;

[0134] S4. Perform low-pass filtering on the retained peak signal to form an envelope demodulation signal and output it.

[0135] This method generates a sampling and holding clock by performing a 90° phase shift on the demodulated signal through a clock signal generation circuit, so that the signal sampling can be accurately triggered at the edge of the sampling and holding clock, thereby performing synchronous sampling and holding at the peak point of the signal. This method can retain the amplitude of the envelope signal in the demodulated signal to the maximum extent, significantly reduce the amplitude attenuation during the demodulation process, and thus meet the requirements of high-precision applications. At the same time, this method can also effectively remove the modulation signal component, so that the modulation signal energy in the sampled signal is extremely small, so that efficient filtering can be completed without relying on a filter with extremely low bandwidth, and therefore the signal delay can be extremely low, so as to be controlled within 1us. It not only avoids the large delay problem that occurs in the envelope signal filtering process, but also significantly improves the delay characteristics of the envelope signal, thereby meeting the requirements of high-precision and high-real-time application scenarios.

[0136] It should be noted that the steps in the demodulation method can be set accordingly according to the corresponding demodulation circuit mentioned above, which will not be further described here.

[0137] Based on the same inventive concept, the present application also provides an inductive encoder corresponding to the aforementioned circuit embodiment, comprising a sensor chip, a transmitting device and a receiving device, wherein the sensor chip comprises an oscillator, and a target rotor to be detected is arranged between the transmitting device and the receiving device;

[0138] The transmitting device and the oscillator jointly generate an electromagnetic field, and the receiving device generates an amplitude modulated wave signal related to the angle of the target rotor according to the electromagnetic field induction; and based on the amplitude modulated wave envelope demodulation circuit described in any one of the aforementioned circuit embodiments, the amplitude modulated envelope signal is demodulated to obtain a demodulated envelope.

[0139] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0140] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A demodulation circuit for an inductive encoder, characterized in that: include: A clock signal generating circuit, used for performing a 90° phase shift on the input signal to be demodulated to generate a sampling and holding clock, wherein the sampling and holding clock includes a clock edge and a level holding state; A sampling and holding circuit, used for sampling the peak signal of the signal to be demodulated according to the clock edge, and holding the peak signal in the level holding state; The low-pass filter circuit is used for performing low-pass filtering on the retained peak signal to form an envelope demodulation signal and output it.

2. The demodulation circuit according to claim 1, characterized in that: The clock edge includes a rising edge and a falling edge; the level holding state includes a high level holding state and a low level holding state; The sampling and holding circuit includes a sampling circuit and a holding circuit; the sampling circuit is used to sample the first peak signal of the signal to be demodulated according to the rising edge, and to sample the second peak signal of the signal to be demodulated according to the falling edge; the holding circuit includes a positive envelope holding circuit and a negative envelope holding circuit; wherein the positive envelope holding circuit is used to hold the first peak signal in the high level holding state; the negative envelope holding circuit is used to hold the second peak signal in the low level holding state; the first peak signal is any one of the positive peak signal and the negative peak signal, and the second peak signal is the other of the positive peak signal and the negative peak signal; The low-pass filter circuit includes a first low-pass filter circuit and a second low-pass filter circuit; the first low-pass filter circuit is used to perform low-pass filtering on the maintained first peak signal to form a positive envelope demodulation signal and output it; the second low-pass filter circuit is used to perform low-pass filtering on the maintained second peak signal to form a negative envelope demodulation signal and output it.

3. The demodulation circuit according to claim 2, characterized in that: The sampling circuit includes a first switch, a second switch, a third switch, a fourth switch and a first capacitor; Among them, one end of the first switch is connected to the output end of the clock signal generating circuit and connected to the signal to be demodulated, the other end of the first switch is connected to one end of the second switch and one end of the first capacitor; the other end of the second switch is connected to a reference voltage; the other end of the first capacitor is connected to one end of the third switch and one end of the fourth switch; the other end of the third switch is connected to a reference voltage; the other end of the fourth switch is connected to the input end of the holding circuit; When the first switch and the third switch are turned on, and the second switch and the fourth switch are turned off, the peak signal of the signal to be demodulated is sampled through the first capacitor.

4. The demodulation circuit according to claim 2, characterized in that: The positive envelope holding circuit comprises a fifth switch and a second capacitor; wherein one end of the fifth switch is connected to the output end of the sampling circuit, the other end of the fifth switch is connected to one end of the second capacitor and the input end of the first low-pass filter circuit, and the other end of the second capacitor is grounded; the fifth switch is used to be turned on when the clock edge is the rising edge, so that the second capacitor holds the first peak signal of the signal to be demodulated; The negative envelope holding circuit includes a sixth switch and a third capacitor; wherein one end of the sixth switch is connected to the output end of the sampling circuit, the other end of the sixth switch is connected to one end of the third capacitor and the input end of the second low-pass filter circuit, and the other end of the third capacitor is grounded; the sixth switch is used to be turned on when the clock edge is the falling edge, so that the third capacitor holds the second peak signal of the signal to be demodulated.

5. The demodulation circuit according to claim 3, characterized in that: The demodulation circuit also includes a sampling and holding amplifier circuit connected between the sampling circuit and the holding circuit; The sampling and holding amplifier circuit includes an operational amplifier and a fourth capacitor, wherein the non-inverting input terminal of the operational amplifier is connected to the other end of the fourth switch, the inverting input terminal of the operational amplifier is connected to a reference voltage, and the output terminal of the operational amplifier is connected to the input terminal of the holding circuit; the fourth capacitor is connected between the non-inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; When the first switch and the third switch are disconnected and the second switch and the fourth switch are turned on, the peak signal sampled by the first capacitor is amplified by the operational amplifier, and the amplification factor of the operational amplifier is adjusted by the fourth capacitor.

6. The demodulation circuit according to claim 1, characterized in that: The clock signal generating circuit comprises a phase shift circuit and a comparator connected to each other, wherein the phase shift circuit is used to perform a 90° phase shift on the signal to be demodulated, and the comparator is used to perform a zero-crossing comparison on the signal after the phase shift circuit is phase-shifted to generate the sampling and holding clock.

7. The demodulation circuit according to claim 6, characterized in that: The phase shift circuit includes an RC phase shift network, wherein the RC phase shift network is an advanced phase shift network, and the RC phase shift network includes a first phase shift resistor and a first phase shift capacitor, one end of the first phase shift capacitor is used to access the signal to be demodulated, the other end of the first phase shift capacitor is connected to one end of the first phase shift resistor and the in-phase input end of the comparator, and the other end of the first phase shift resistor is connected to the power supply end; wherein, when the frequency of the signal to be demodulated is between 2MHz and 5MHz, the RC constant formed by the first phase shift resistor and the first phase shift capacitor is not greater than 1.03×10 -8 , so that the phase shift deviation of the RC phase shift network to the signal to be demodulated is no more than 5% of the period of the signal to be demodulated; Alternatively, the RC phase shift network is a hysteresis phase shift network, the RC phase shift network includes a second phase shift resistor and a second phase shift capacitor, one end of the second phase shift resistor is used to access the signal to be demodulated, the other end of the second phase shift resistor is connected to one end of the second phase shift capacitor and the in-phase input end of the comparator, and the other end of the second phase shift capacitor is grounded; wherein, when the frequency of the signal to be demodulated is between 2MHz and 5MHz, the RC constant formed by the second phase shift resistor and the second phase shift capacitor is not less than 2.45×10 -7 , so that the phase shift deviation of the RC phase shift network to the signal to be demodulated is no more than 5% of the period of the signal to be demodulated.

8. The demodulation circuit according to claim 6, characterized in that: The phase shift circuit comprises a phase-locked loop circuit, wherein the phase-locked loop circuit comprises a phase detector, a low-pass filter loop, a voltage-controlled oscillator and a frequency divider; the phase detector is used to form a 90° phase difference signal according to the input signal to be demodulated, and the low-pass filter loop is used to low-pass filter the phase difference signal; the voltage-controlled oscillator is used to generate an oscillation signal, wherein the frequency of the oscillation signal is the same as the frequency of the signal to be demodulated, and the phase of the oscillation signal differs from the phase of the signal to be demodulated by 90°; or The phase shift circuit includes a delay phase-locked loop circuit, wherein the delay phase-locked loop circuit includes a phase comparison circuit and a delay circuit; wherein the phase comparison circuit is used to perform phase comparison between the signal to be demodulated and the phase-shifted signal output by the delay circuit, and control the delay circuit according to the comparison result so that the delay circuit converts the input signal to be demodulated into a 90° phase-shifted signal.

9. A demodulation method applied to an inductive encoder, characterized in that: The demodulation method comprises: Generate a sampling and holding clock with a 90° phase shift according to the input signal to be demodulated, wherein the sampling and holding clock includes a clock edge and a level holding state; According to the clock edge, sampling the peak signal of the signal to be demodulated; Maintaining the peak signal in the level holding state; The retained peak signal is low-pass filtered to form an envelope demodulation signal and output.

10. An inductive encoder, characterized in that: include: A sensor chip, wherein the sensor chip includes an oscillator; A transmitting device and a receiving device, wherein a target rotor to be detected is arranged between the transmitting device and the receiving device; the transmitting device and the oscillator jointly generate an electromagnetic field, and the receiving device generates an amplitude modulated wave signal related to the angle of the target rotor according to the electromagnetic field induction; and The demodulation circuit according to any one of claims 1 to 8, wherein the demodulation circuit is used to demodulate the amplitude modulated wave signal to obtain an envelope demodulation signal.

Images