High pressure sensor chip with one-word beam double island structure with stress hole and preparation method

Abstract

A one-bar double-island structure high-pressure pressure sensor chip with stress holes and a preparation method thereof, comprising a support layer, an insulating layer and a device layer arranged from bottom to top; a cavity is etched on the back of the support layer, and a sensitive film is arranged directly above the cavity; a one-bar double-island structure is arranged on the sensitive film; four piezoresistive strips are arranged at the edges and the center of the one-bar double-island structure respectively; the four piezoresistive strips are connected into a half-open loop Wheatstone bridge through five P-type heavily doped silicon leads; five metal point electrodes are arranged at the center of the five P-type heavily doped silicon lead regions; a sealing ring is arranged outside the periphery; the adjacent P-type heavily doped silicon leads are separated by a fine gap from the sealing ring; the present application effectively improves the pressure bearing limit, ensures a high range, realizes excellent sensitivity and linearity performance, has a high-pressure measurement capability of tens to hundreds of megapascals, and can withstand a temperature as high as 400 DEG C, and is widely applicable to the fields of petroleum, natural gas, chemical industry and high-pressure equipment monitoring.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon-based piezoresistive high-pressure pressure sensor, in particular to a one-beam double-island structure high-pressure pressure sensor chip with stress holes and a preparation method. BACKGROUND

[0002] The silicon-based piezoresistive pressure sensor utilizes the piezoresistive effect of silicon material to directly convert mechanical strain caused by pressure into electrical signal output. When pressure acts on the sensor diaphragm, the deformation of the diaphragm causes the resistance of the piezoresistive element to change, and then the resistance change is converted into a voltage signal through a Wheatstone bridge. The sensor has low cost and wide application range, and with the superior performance and mature manufacturing process of silicon material, it shows high sensitivity, high precision, fast response and other characteristics, and has been widely used in the fields of automobile, aerospace, medical devices and industrial automation.

[0003] The high-pressure pressure sensor is designed for extreme pressure conditions. The patent application with the title "MEMS pressure sensor oil-filled core body suitable for high-pressure small-molecule medium" (publication number: CN116989933A) adopts an oil-filled packaged pressure sensor. Through the synergistic effect of the corrugated metal diaphragm and the silicone oil, the input high pressure is effectively reduced to the bearing range of the sensor chip. However, in a high-temperature environment exceeding 200°C, the volume of silicone oil will increase due to thermal expansion, which may cause liquid leakage and lead to sensor failure. In addition, the filling process of silicone oil requires high technical precision and the packaging process is complex, increasing the manufacturing difficulty and cost. The patent application with the title "Pressure sensor chip, high-pressure resistant pressure sensor and manufacturing method thereof" (publication number: CN113551815A) adheres the pressure sensor chip to the surface of the diaphragm through silicone gel. The bottom of the diaphragm is connected to the external environment. When pressure is applied, the glass substrate and silicon-based pressure strain on the surface of the diaphragm are subjected to force, causing the resistance value of the pressure-sensitive resistor on the chip to change, thereby outputting the corresponding signal. This packaging structure effectively avoids the contact between the connecting wire and the external environment, significantly improving the anti-interference ability and temperature resistance of the sensor. However, since the back of the sensor chip bears the pressure, the additional stress on the connecting wire and pad caused by the upward protrusion of the chip during long-term use increases the risk of connecting wire falling off, which may lead to sensor failure. The literature "Zhang G D, Zhao Y L, Zhao Y, et al. Research of a Novel Ultra-High Pressure Sensor with High-Temperature Resistance [J]. Micromachines, 2018, 9(1): 5." compared to the traditional front or back pressure bearing method, by attaching the sensor chip to the side of the cylinder and using a side pressure bearing design, the sensor's range is successfully increased to the gigapascal (GPa) level. However, since the pressure is applied to the cylinder, its deformation behavior is affected by the mass distribution and shape factors, resulting in uneven deformation, which produces a smaller output signal and is accompanied by significant non-linear characteristics, limiting the widespread application of this design in engineering practice.

[0004] In summary, the existing high-pressure pressure sensors have the following shortcomings: liquid leakage in high-temperature environments, complex packaging process, lead falling off during long-term use, low sensitivity, and poor linearity. SUMMARY

[0005] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a one-beam double-island structure high-pressure pressure sensor chip with stress holes and a preparation method, by introducing a rectangular thick film structure in the sensor chip, effectively improving the pressure bearing limit, and etching a one-beam double-island structure with stress holes on the surface of the chip, greatly enhancing the stress distribution and partial structural stiffness of the stress concentration area, thereby ensuring high range while achieving excellent sensitivity and linearity performance; in addition, in order to meet the reliability requirements in high temperature environment, the connection between the chip and the external circuit is realized through the process design of through silicon via (TSV) technology and electron beam evaporation conductive metal filling hole, avoiding the problem of lead falling off during long-term use, and at the same time solving the risk of silicone oil leakage of oil-filled packaged sensors under the condition of exceeding 200℃; the sensor has high pressure measurement capability of tens to hundreds of megapascals, and can withstand a temperature as high as 400℃, and is widely used in the fields of petroleum, natural gas, chemical industry and high pressure equipment monitoring.

[0006] In order to achieve the above-mentioned purpose, the present application realizes the following technical solutions:

[0007] A one-beam double-island structure high-pressure pressure sensor chip with stress holes comprises a support layer 1, an insulating layer 2 and a device layer 3 arranged from bottom to top; a cavity 1-1 is etched on the back of the support layer 1, a sensitive film 1-2 is directly above the cavity 1-1, and a one-beam double-island structure 4 is arranged on the sensitive film 1-2; four piezoresistive strips 5-1, 5-2, 5-3 and 5-4 are arranged at the edge and center of the one-beam double-island structure 4, respectively, the four piezoresistive strips 5-1, 5-2, 5-3 and 5-4 are connected into a half-open loop Wheatstone bridge through five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5, five metal point electrodes 7-1, 7-2, 7-3, 7-4 and 7-5 are arranged at the center of the five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5, a sealing ring 8 is arranged around the outside, and the adjacent P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5 are separated from the sealing ring 8 by a fine gap 9.

[0008] The sensitive film 1-2 adopts a rectangular thick film, the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity 1-1 and the sensitive film 1-2 have the same size and shape; the four piezoresistive strips 5-1, 5-2, 5-3 and 5-4 are arranged in a "middle edge" design, and the effective length direction of the four piezoresistive strips 5-1, 5-2, 5-3 and 5-4 is along the crystal direction with the maximum piezoresistive coefficient of the (100) crystal surface.

[0009] The linear beam double island structure 4 includes two square islands 4-1, 4-2, and each of the two square islands 4-1, 4-2 is connected with a beam 4-3, the beam 4-3 is provided with a stress hole 4-4 at the center, the depth of the stress hole 4-4 is consistent with the height of the two square islands 4-1, 4-2 and the beam 4-3, and the distance between the two square islands 4-1, 4-2, the side length, the width of the beam 4-3 and the length and width of the stress hole 4-4 are determined by simulation optimization.

[0010] The thickness of the beam 4-3 is 10-40 μm, and the beam thickness is adjusted according to different sensitivity ranges.

[0011] The transverse and longitudinal stress difference directions of the two piezoresistive strips 5-1, 5-4 at the upper edge of the linear beam double island structure 4 and the two piezoresistive strips 5-2, 5-3 at the center are opposite, and the corresponding Wheatstone bridge pair bridge resistance changes are opposite.

[0012] The piezoresistive strips 5-1, 5-2, 5-3, 5-4 are P-type heavily doped, the doping concentration is the same as that of the P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5, and the upper surfaces of the piezoresistive strips 5-1, 5-2, 5-3, 5-4 are flush with the upper surfaces of the P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5.

[0013] The depth of the fine slit 9 is 1.5 μm, and the depth is equal to the depth of the device layer 3.

[0014] The front surface of the device layer 3 is vacuum-bonded with the silicon wafer 10, and the sensitive circuit is protected in the vacuum cavity composed of the device layer 3 and the silicon wafer 10.

[0015] The silicon wafer 10 is provided with five through silicon vias 11-1, 11-2, 11-3, 11-4, 11-5, which correspond to the shapes of the five metal point electrodes 7-1, 7-2, 7-3, 7-4, 7-5, respectively; the five through silicon vias 11-1, 11-2, 11-3, 11-4, 11-5 are filled with conductive metal 12; the silicon wafer 10 is provided with a recess 13 at the center, the recess 13 is rectangular in shape, the width of the recess 13 corresponds to the sensitive film 1-2, the length of the recess 13 corresponds to the farthest distance between the two piezoresistive strips 5-1, 5-4 at the edge, and the depth of the recess 13 ensures that the bottom surface of the recess 13 does not contact the linear beam double island structure 4 when high voltage is input.

[0016] The preparation method of the one linear beam double island structure high pressure pressure sensor chip with a stress hole includes the following steps:

[0017] 1) The chip adopts an SOI silicon wafer, and the SOI silicon wafer is composed of a device layer 3, an insulating layer 2 and a support layer 1 from top to bottom, wherein the device layer 3 and the support layer 1 are N-type single crystal silicon, the upper surface of the device layer 3 is a (100) crystal surface, and the insulating layer 2 is a SiO2 layer.

[0018] 2) The chip is subjected to thermal oxidation, boron ion re-doping ion implantation is carried out on the surface of the device layer 3, and annealing is carried out to make the implanted ions uniformly distributed in the device layer 3, so that electrical activation is realized;

[0019] 3) The silicon with the thickness of the device layer 3 is etched away by using the ICP technology to form four piezoresistive resistor strips 5-1, 5-2, 5-3 and 5-4, five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5, and a sealing ring 8;

[0020] 4) The PECVD technology is adopted to deposit silicon dioxide and silicon nitride 2-1 on the entire chip surface;

[0021] 5) The silicon dioxide and silicon nitride 2-1 on the back of the support layer 1 are etched away by using the ICP technology, the etching area is limited to the positive surface area of the cavity 1-1, and then wet etching is adopted, and the etching depth is limited to the bottom of the sensitive film 1-2 (0.5-0.7 times the thickness of the chip);

[0022] 6) The silicon dioxide and silicon nitride 2-1 on the chip surface are etched away by using the ICP technology to expose the point electrode area, and then the five metal point electrodes 7-1, 7-2, 7-3, 7-4 and 7-5 are formed through the metal sputtering and stripping processes;

[0023] 7) The device layer 3, the insulating layer 2 and the support layer 1 are etched by using the ICP technology, and the etching depth is 10-40 mu m, so as to form a complete one-beam double-island structure 4 three-dimensional structure with stress holes;

[0024] 8) The surface of the device layer 3 is vacuum-bonded with a silicon wafer 10, and the five silicon vias 11-1, 11-2, 11-3, 11-4 and 11-5 are aligned with the positions of the five metal point electrodes 7-1, 7-2, 7-3, 7-4 and 7-5 on the device layer 3 during the vacuum bonding;

[0025] 9) The five silicon vias 11-1, 11-2, 11-3, 11-4 and 11-5 are filled with conductive metal 12 by using the electron beam evaporation technology.

[0026] Compared with the prior art, the application has the beneficial effects that:

[0027] The sensitive film of the application adopts a rectangular shape, compared with a square or circular diaphragm, the rectangular diaphragm can maintain a higher inherent frequency and overload capacity, the advantage of this design is that the output stability of the sensor under high-frequency dynamic response working conditions is improved, and it is ensured that the sensor can quickly and accurately respond in a rapidly changing high-pressure environment, so as to meet the demand of modern industry for high-performance sensors.

[0028] The application is a stress concentration structure composed of a unidirectional beam double island structure with a stress hole on the front, a sensitive film and a back cavity as a chip structure of a piezoresistive pressure sensor. Compared with a traditional beam structure, the design of the unidirectional beam double island structure allows the distance between the islands and the side length of the island to be precisely adjusted, thereby significantly enhancing the transverse and longitudinal stress difference of the stress concentration area. In order to make the stress concentration effect more significant, a stress hole is etched in the center of the unidirectional beam double island structure to further improve the sensitivity of the sensor. The sensitive film adopts a flat film structure, which successfully solves the acceleration interference caused by the mass block that may be introduced during the back etching process of the traditional beam film-mass block structure. This improvement effectively reduces the noise output, thereby improving the clarity and accuracy of the signal.

[0029] The application adopts P-type heavily doped silicon leads and P-type heavily doped piezoresistive strips to form a sensitive circuit of a sensor chip. This selection exhibits excellent stability in a high-temperature environment. Compared with the P-type lightly doped piezoresistive strips and metal leads used in traditional sensors, the heavily doped material not only has small sensitivity temperature drift, but also effectively simplifies the production process, reduces the use of materials and process steps, thereby improving the overall production efficiency, reducing the production cost, and ensuring higher yield.

[0030] The application adopts a semi-open loop Wheatstone bridge with five P-type heavily doped silicon leads and five metal point electrodes, allowing for the convenient addition of a temperature compensation circuit in the later stage, thereby further enhancing the temperature resistance of the sensor and improving its measurement accuracy in different temperature environments, ensuring that it still maintains good performance and stability under complex operating conditions.

[0031] The pressure sensor of the application is designed with a sealing ring around the pad, which is beneficial to improve the sealing performance of the pressure sensor chip after vacuum bonding, further reducing the influence of corrosive gases and vapors in the test environment on the sensor chip. The sensor structure is flexible and diverse, suitable for full solid-state packaging and leadless packaging, and can meet the needs of different application scenarios.

[0032] The application adopts an SOI silicon wafer, which has low process preparation cost and high yield, can meet the demand of large-scale production, and its theoretical working temperature can reach 600 DEG C. Under high-temperature conditions, the existence of the insulating layer effectively prevents the occurrence of PN junction breakdown and leakage phenomenon, ensuring the long-term stability and reliability of the sensor, so that it still performs excellently in high-temperature applications.

[0033] The application adopts silicon wafers instead of glass for vacuum bonding. In thermal cycle conditions, the thermal stress generated by silicon-silicon bonding is smaller than that generated by silicon-glass bonding, which can greatly improve the service life of the sensor in a wide temperature range.

[0034] In summary, compared with the prior art, the sensor chip of the present invention provides sensors with stronger adaptability and accuracy in practical applications and has broad market prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a front isometric diagram of a high-pressure pressure sensor chip according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic backside isometric view of a high-pressure pressure sensor chip according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of a double-island structure of a straight beam with stress holes according to an embodiment of the present invention.

[0038] Figure 4 This is an axonometric diagram of a high-pressure pressure sensor chip bonded to a silicon wafer according to an embodiment of the present invention.

[0039] Figure 5 This is a schematic front axonometric view of a silicon wafer according to an embodiment of the present invention.

[0040] Figure 6 Schematic diagram of the back side isometric view of a silicon wafer according to an embodiment of the present invention.

[0041] Figure 7 This is a half-section isometric diagram of a high-pressure pressure sensor chip bonded to a silicon wafer filled with conductive metal according to an embodiment of the present invention.

[0042] Figure 8 Schematic diagram of the sensor chip preparation method according to an embodiment of the present invention: Figure (a) is a schematic diagram of the SOI substrate structure; Figure (b) is a schematic diagram of heavy doping; Figure (c) is a schematic diagram of dry etching of varistor strips, P-type heavily doped silicon leads, a double-island structure of a beam with stress holes and a sealing ring; Figure (d) is a schematic diagram of depositing silicon nitride and silicon dioxide; Figure (e) is a schematic diagram of wet etching of the cavity after etching back silicon dioxide and silicon nitride; Figure (f) is a schematic diagram of metal sputtering point electrodes after etching front silicon dioxide and silicon nitride; Figure (g) is a schematic diagram of dry etching the front to form a complete double-island structure of a beam with stress holes; Figure (h) is a schematic diagram of bonding; Figure (i) is a schematic diagram of electron beam evaporation of conductive metal.

[0043] Figure 9 This is a comparison diagram of stress distribution under the same pressure load for rectangular membrane, square membrane and circular membrane in an embodiment of the present invention.

[0044] Figure 10 This is a comparison chart of the simulation performance of rectangular membranes, square membranes and circular membranes according to an embodiment of the present invention.

[0045] Figure 11This is a comparison diagram of stress distribution under the same pressure load between the one-beam double-island structure with stress holes in an embodiment of the present invention and other beam-island (mass block) structures.

[0046] Figure 12 This is a comparison chart of the simulation performance of the double-island structure of a straight beam with stress holes and other beam-island (mass block) structures according to an embodiment of the present invention.

[0047] Figure 13 1 is the relationship between the P-type silicon piezoresistance coefficient factor and the doping concentration and temperature in an embodiment of the present invention.

[0048] Figure 14 This is a temperature compensation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention is described in detail below with reference to the embodiments and accompanying drawings.

[0050] Reference Figure 1 、 Figure 2 A high-pressure pressure sensor chip with a straight beam double-island structure and a stress hole includes a support layer 1, an insulating layer 2, and a device layer 3 arranged from bottom to top; a cavity 1-1 is etched on the back of the support layer 1, a sensitive film 1-2 is located directly above the cavity 1-1, and a straight beam double-island structure 4 is provided on the sensitive film 1-2; four piezoresistive strips 5-1, 5-2, 5-3, and 5-4 are arranged at the edge and center of the straight beam double-island structure 4, and the arrangement of the four piezoresistive strips 5-1, 5-2, 5-3, and 5-4 adopts a "center-edge" design. The effective length directions of the four piezoresistive strips 5-1, 5-2, 5-3, and 5-4 are all along the (100) The crystal direction with the largest crystal plane piezoresistive coefficient; the four varistor strips 5-1, 5-2, 5-3, and 5-4 are connected to form a semi-open-loop Wheatstone bridge through five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. Five metal point electrodes 7-1, 7-2, 7-3, 7-4, and 7-5 are arranged at the center of the five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5. A sealing ring 8 is arranged around the outside. Adjacent P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, and 6-5 are separated from the sealing ring 8 by a 10-20 μm wide gap 9.

[0051] The sensitive film 1-2 is a rectangular thick film, and the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity 1-1 is the same in shape and size as the plane of the sensitive film 1-2.

[0052] Reference Figure 3The one-beam double-island structure 4 includes two square islands 4-1, 4-2, and each of the two square islands 4-1, 4-2 is connected with a beam 4-3, the beam 4-3 is provided with a stress hole 4-4 at the center, the depth of the stress hole 4-4 is consistent with the height of the two square islands 4-1, 4-2 and the beam 4-3, and the distance between the two square islands 4-1, 4-2, the side length, the width of the beam 4-3 and the length and width of the stress hole 4-4 are determined through simulation optimization.

[0053] The thickness of the beam 4-3 is 10-40 μm, and the beam thickness is adjusted according to different sensitivity ranges.

[0054] The transverse and longitudinal stress difference directions of the two piezoresistance strips 5-1, 5-4 at the upper edge of the one-beam double-island structure 4 and the two piezoresistance strips 5-2, 5-3 at the center are opposite, and the corresponding Wheatstone bridge pair bridge resistance changes are opposite.

[0055] The piezoresistance strips 5-1, 5-2, 5-3, 5-4 are P-type heavily doped, the doping concentration is the same as that of the P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5, and the upper surfaces of the piezoresistance strips 5-1, 5-2, 5-3, 5-4 are flush with the upper surfaces of the P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4, 6-5.

[0056] The depth of the fine slit 9 is 1.5 μm, and the depth is equal to the depth of the device layer 3.

[0057] Referring to Figure 4 The front surface of the device layer 3 is vacuum-bonded with the silicon wafer 10, and the sensitive circuit is protected in the vacuum cavity composed of the device layer 3 and the silicon wafer 10.

[0058] Referring to Figure 5 , Figure 6 , Figure 7 The silicon wafer 10 is provided with five through silicon vias 11-1, 11-2, 11-3, 11-4, 11-5, which correspond in shape to the five metal point electrodes 7-1, 7-2, 7-3, 7-4, 7-5; the five through silicon vias 11-1, 11-2, 11-3, 11-4, 11-5 are filled with conductive metal 12; the silicon wafer 10 is provided with a recess 13 at the center, the recess 13 is rectangular in shape, the width of the recess 13 corresponds to the sensitive film 1-2, the length of the recess 13 corresponds to the farthest distance between the two piezoresistance strips 5-1, 5-4 at the edge, and the depth of the recess 13 ensures that the bottom surface of the recess 13 does not contact the one-beam double-island structure 4 when high voltage is input.

[0059] Referring to Figure 8 The preparation method of the one-beam double-island structure high-voltage pressure sensor chip with a stress hole includes the following steps:

[0060] 1) The chip uses SOI silicon wafer, and the SOI silicon wafer is composed of device layer 3, insulating layer 2 and support layer 1 from top to bottom, wherein the device layer 3 and the support layer 1 are N-type monocrystalline silicon, the upper surface of the device layer 3 is (100) crystal surface, and the insulating layer 2 is SiO2 layer, as shown in (a) of FIG. 1; Figure 8

[0061] 2) The chip is subjected to thermal oxidation, boron ion re-doping ion implantation is performed on the surface of the device layer 3, and annealing is performed to make the implanted ions uniformly distributed in the device layer 3, so as to realize electrical activation, as shown in (b) of FIG. 2; Figure 8

[0062] 3) The thickness of the device layer 3 is etched by ICP technology to form four piezoresistive strips 5-1, 5-2, 5-3 and 5-4, and five P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5, and a sealing ring 8, as shown in (c) of FIG. 3; Figure 8

[0063] 4) PECVD technology is used to deposit silicon dioxide and silicon nitride 2-1 on the entire surface of the chip, as shown in (d) of FIG. 4; Figure 8

[0064] 5) The silicon dioxide and silicon nitride 2-1 on the back of the support layer 1 are etched by ICP technology, and the etching area is limited to the positive surface area of the cavity 1-1, and then wet etching is performed, and the etching depth is to the bottom of the sensitive film 1-2 (0.5-0.7 times the thickness of the chip), as shown in (e) of FIG. 5; Figure 8

[0065] 6) The silicon dioxide and silicon nitride 2-1 on the surface of the chip are etched by ICP technology to expose the point electrode area, and then five metal point electrodes 7-1, 7-2, 7-3, 7-4 and 7-5 are formed by metal sputtering and stripping process, as shown in (f) of FIG. 6; Figure 8

[0066] 7) The device layer 3, the insulating layer 2 and the support layer 1 are etched by ICP technology, and the etching depth is 10-40 μm, so as to form a complete one-beam double-island structure 4 with a stress hole, as shown in (g) of FIG. 7; Figure 8

[0067] 8) The surface of the device layer 3 is vacuum bonded with a silicon wafer 10, and the five silicon vias 11-1, 11-2, 11-3, 11-4 and 11-5 are aligned with the positions of the five metal point electrodes 7-1, 7-2, 7-3, 7-4 and 7-5 on the device layer 3, as shown in (h) of FIG. 8; Figure 8

[0068] 9) The five silicon vias 11-1, 11-2, 11-3, 11-4 and 11-5 are filled with conductive metal 12 by electron beam evaporation technology, as shown in (i) of FIG. 9;​​​​​​​​Figure 8 The stress difference of the one-beam double-island structure with stress holes is the highest, indicating that this structure can produce more significant strain response under external pressure; in addition, the first-order modal (working modal) natural frequency of this structure is higher, ensuring that it has better dynamic response characteristics during operation. Considering its stress sensitivity and natural frequency, the one-beam double-island structure with stress holes can effectively meet the needs of high-pressure sensors in terms of high sensitivity and high linearity, and therefore has the most optimal performance among all the compared structures, and is suitable for high-precision high-pressure detection applications.

[0069] Referring to Figure 9 and Figure 10 In this embodiment, the sensitive film 1-2 adopts a rectangular film (aspect ratio of 2.04:1), which exhibits the smallest diaphragm displacement and the largest natural frequency under different working conditions compared with square and circular films; this indicates that the rectangular film has higher stiffness and overload capacity when subjected to external force, and can effectively inhibit excessive deformation of the diaphragm. The rectangular film sensor can provide the best output stability under high-frequency dynamic response working conditions, especially in rapidly changing high-pressure environments, it can quickly and accurately respond to external pressure changes, ensuring that the sensor maintains high performance stability and response accuracy under extreme working conditions. Therefore, this structure is suitable for high-precision and fast-response high-pressure detection applications.

[0070] Referring to Figure 11 , Figure 12 In this embodiment, the one-beam double-island structure with stress holes has the highest stress difference compared with the cross-beam structure, the one-beam structure, the cross-beam single-island structure, the cross-beam single-island-mass structure, the cross-beam four-island structure, the cross-beam four-island-mass structure, the one-beam single-island structure, the one-beam single-island-mass structure, the one-beam double-island structure, and the one-beam double-island-mass structure, indicating that this structure can produce more significant strain response under external pressure; in addition, the first-order modal (working modal) natural frequency of this structure is higher, ensuring that it has better dynamic response characteristics during operation. Considering its stress sensitivity and natural frequency, the one-beam double-island structure with stress holes can effectively meet the needs of high-pressure sensors in terms of high sensitivity and high linearity, and therefore has the most optimal performance among all the compared structures, and is suitable for high-precision high-pressure detection applications.

[0071] Referring to Figure 13 In this embodiment, the variation of the piezoresistive coefficient factor of P-type silicon with doping concentration and temperature can lead to the following conclusions: as the doping concentration increases, the difference between the piezoresistive coefficient factors of P-type silicon at different temperatures gradually decreases; this indicates that P-type silicon materials with higher doping concentrations exhibit smaller temperature drift (temperature drift) within different temperature ranges, and this phenomenon indicates that high-doped P-type silicon materials have better temperature stability, thereby reducing the sensitivity error caused by temperature changes, and are suitable for application in environments with large temperature changes, especially in high-temperature high-pressure sensor applications, which have strong adaptability and accuracy.

[0072] Referring to Figure 14The temperature compensation circuit of the embodiment is composed of a pressure-sensitive resistor strip and a compensation resistor, and the specific components and functions are as follows: the resistors R1, R2, R3 and R4 are the resistors of the pressure-sensitive resistor strips 5-1, 5-2, 5-3 and 5-4 respectively, for sensing external pressure and converting into corresponding electrical signals; Rz is a zero-point output compensation resistor, for correcting the initial output deviation of the sensor; Rp is a thermal zero-point drift compensation resistor, for compensating the zero-point drift caused by temperature change; Rs is a thermal sensitivity compensation resistor, for correcting the influence of temperature change on sensitivity; the resistors in the circuit are connected through P-type heavily doped silicon leads 6-1, 6-2, 6-3, 6-4 and 6-5, to form a complete Wheatstone bridge structure, and through the synergistic effect of the pressure-sensitive resistor strip and the compensation resistor, the accurate compensation of temperature drift and sensitivity drift is realized.

Claims

1. A high-pressure pressure sensor chip with a straight-beam double-island structure and stress holes, comprising a support layer (1), an insulating layer (2), and a device layer (3) arranged from bottom to top; a cavity (1-1) is etched on the back of the support layer (1), and a sensitive film (1-2) is located directly above the cavity (1-1), characterized in that: A single-beam double-island structure (4) is provided on the sensitive film (1-2); four piezoresistive resistor strips (5-1, 5-2, 5-3, 5-4) are arranged at the edge and center of the single-beam double-island structure (4), respectively; the four piezoresistive resistor strips (5-1, 5-2, 5-3, 5-4) are connected to form a semi-open-loop Wheatstone bridge via five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) are provided at the center of the region of the five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); a sealing ring (8) is provided on the outer side thereof; adjacent P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5) are separated from the sealing ring (8) by a fine gap (9).

2. The chip according to claim 1, wherein: The sensitive film (1-2) is a rectangular thick film, and the film thickness is 0.5-0.7 times the thickness of the chip; the upper surface of the cavity (1-1) is the same as the plane shape and size of the sensitive film (1-2); the arrangement of the four piezoresistive strips (5-1, 5-2, 5-3, 5-4) adopts a "center-edge" design, and the effective length directions of the four piezoresistive strips (5-1, 5-2, 5-3, 5-4) are all along the crystal direction with the maximum piezoresistive coefficient of the (100) crystal plane.

3. The chip according to claim 1, wherein: The one-beam double-island structure (4) comprises two square islands (4-1, 4-2), the two square islands (4-1, 4-2) are respectively connected to a beam (4-3), a stress hole (4-4) is provided at the center of the beam (4-3), and the depth of the stress hole (4-4) is consistent with the height of the two square islands (4-1, 4-2) and the beam (4-3); the distance and side length between the two square islands (4-1, 4-2), the width of the beam (4-3), and the length and width of the stress hole (4-4) are all determined through simulation optimization.

4. The chip according to claim 3, wherein: The thickness of the beam (4-3) is 10-40 μm, and the thickness of the beam is adjusted according to different sensitivity ranges.

5. The chip according to claim 1, wherein: The transverse and longitudinal stress differences of the two piezoresistive resistor strips (5-1, 5-4) at the upper edge and the two piezoresistive resistor strips (5-2, 5-3) at the center of the one-beam double-island structure (4) are in opposite directions, and the corresponding Wheatstone bridge resistance changes are opposite.

6. The chip according to claim 1, wherein: The varistor strips (5-1, 5-2, 5-3, 5-4) are heavily P-type doped, and the doping concentration is the same as that of the P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5). The upper surface of the varistor strips (5-1, 5-2, 5-3, 5-4) is flush with the upper surface of the P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5).

7. The chip according to claim 1, wherein: The depth of the fine slit (9) is 1.5 μm, which is equal to the depth of the device layer (3).

8. The chip according to claim 1, wherein: The front surface of the device layer (3) is vacuum bonded to the silicon wafer (10), protecting the sensitive circuit in a vacuum cavity formed by the device layer 3 and the silicon wafer (10).

9. The chip according to claim 8, characterized in that: The silicon wafer (10) is provided with five through-silicon vias (11-1, 11-2, 11-3, 11-4, 11-5), which respectively correspond to the shapes of the five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5); the five through-silicon vias (11-1, 11-2, 11-3, 11-4, 11-5) are filled with conductive metal (12); a groove (13) is provided at the center of the silicon wafer (10), the groove (13) is rectangular in shape, the width of the groove (13) corresponds to the sensitive film (1-2), the length of the groove (13) corresponds to the farthest distance between the two piezoresistive resistor strips (5-1, 5-4) at the edge, and the depth of the groove (13) ensures that when there is a high voltage input, the bottom surface of the groove (13) will not contact the single-beam double-island structure (4).

10. The method for preparing a high-pressure pressure sensor chip with a straight beam and double island structure and stress holes according to any one of claims 1 to 9, characterized in that: The following steps are involved: 1) The chip adopts SOI silicon wafer, and the SOI silicon wafer comprises a device layer (3), an insulating layer (2), and a support layer (1) from top to bottom, wherein the device layer (3) and the support layer (1) are N-type single crystal silicon, the upper surface of the device layer (3) is a (100) crystal plane, and the insulating layer (2) is a SiO2 layer; 2) thermally oxidizing the chip, heavily doping the surface of the device layer (3) with boron ions, and annealing to uniformly distribute the implanted ions in the device layer (3) to achieve electrical activation; 3) Using ICP technology to etch away silicon of the thickness of the device layer (3), forming four varistor strips (5-1, 5-2, 5-3, 5-4); five P-type heavily doped silicon leads (6-1, 6-2, 6-3, 6-4, 6-5); and a sealing ring (8); 4) Using PECVD technology to deposit silicon dioxide and silicon nitride (2-1) on the entire chip surface; 5) Using ICP technology to etch away the silicon dioxide and silicon nitride (2-1) on the back of the support layer (1), the etching area is based on the positive surface area of ​​the cavity (1-1), and then wet etching is used until the etching depth of the sensitive film (1-2) is 0.5-0.7 times the thickness of the chip; 6) Using ICP technology to etch away the silicon dioxide and silicon nitride (2-1) on the chip surface to expose the point electrode area, and then forming five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) through metal sputtering and lift-off processes; 7) using ICP technology to etch the device layer (3), the insulating layer (2) and the support layer (1) to a depth of 10-40 μm to form a complete three-dimensional structure of a beam double island structure (4) with stress holes; 8) vacuum bonding the surface of the device layer (3) to the silicon wafer (10), wherein the five through-silicon vias (11-1, 11-2, 11-3, 11-4, 11-5) are aligned with the positions of the five metal point electrodes (7-1, 7-2, 7-3, 7-4, 7-5) on the device layer (3); 9) Filling the five through-silicon vias (11-1, 11-2, 11-3, 11-4, 11-5) with conductive metal (12) using electron beam evaporation technology.

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