An ultrasonic echo signal acquisition and error correction method, device and ultrasonic flaw detector

Abstract

The present invention belongs to the technical field of signal acquisition, and provides an ultrasonic echo signal acquisition error correction method, device and ultrasonic flaw detection equipment. The technical solution is to receive an FCLK frame signal and decode the FCLK frame signal; determine whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channels, the data acquisition process is paused, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions; if it meets, the decoding is correct, and the echo data acquisition is started to obtain the ultrasonic echo signal. By determining the generation timing of the shift pulse, decoding errors are discovered and corrected without affecting normal operation, minimizing the time-consuming of subsequent steps caused by data errors, and improving the working efficiency of the ultrasonic flaw detection equipment.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal acquisition, and particularly relates to a method and device for correcting errors in ultrasonic echo signal acquisition and an ultrasonic flaw detection device. Background Art

[0002] The statements in this part only provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] In an ultrasonic system, the system needs to collect echo data for imaging analysis. Therefore, an ADC chip is required to convert analog signals into digital signals that the system can process. The frequency of ultrasonic signals is generally in the range of several hundred KHz to several tens of MHz. According to the sampling theorem, the ADC sampling speed must be at least twice that of the ultrasonic signal. In this case, the ADC must adopt high-speed data transmission technology to output the converted data in a timely manner. LVDS is a communication technology adopted by many high-speed multi-channel ADCs.

[0004] Traditional high-speed ADC chips have a built-in test mode for LVDS output data. After the FPGA master chip is powered on, in order to confirm whether the data output by the ADC is correct, the LVDS interface of the ADC chip will be set to the test mode first. In the test mode, the DATA data channel of LVDS usually outputs data in certain specific formats, such as all 1s or all 0s, to assist the FPGA master in bit error correction. After the error correction is completed, the FPGA master then sets the LVDS interface of the ADC to the normal working mode, and the system can enter the working state.

[0005] Traditionally, the system startup requires two steps, namely the test mode and the normal mode, with a relatively long startup time. Moreover, it cannot be guaranteed that the switching is synchronous, and there may be a situation where the test mode is normal but the data is misaligned in the normal mode, resulting in system startup failure. Summary of the Invention

[0006] In order to solve at least one of the technical problems existing in the above background art, the present invention provides a method and device for correcting errors in ultrasonic echo signal acquisition and an ultrasonic flaw detection device, which can discover and correct decoding errors without affecting normal operation by determining the generation timing of the bitslip pulse, minimizing the time consumption of subsequent steps caused by data errors, and improving the working efficiency of the ultrasonic flaw detection device.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] The first aspect of the present invention provides a method for correcting errors in ultrasonic echo signal acquisition, including the following steps:

[0009] Configure the ultrasonic echo signal acquisition to enter the normal working mode;

[0010] Receive the FCLK frame signal and decode the FCLK frame signal;

[0011] Determine whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channels. Pause the data acquisition process, generate a shift pulse, and perform a shift operation on the parallel output echo data until the decoding result meets the set conditions;

[0012] If it meets the conditions, the decoding is correct, start the echo data acquisition, and obtain the ultrasonic echo signal.

[0013] Furthermore, when the decoding result of the FCLK frame signal is not all 1s or all 0s, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0014] Furthermore, use the FCLK frame signal as the data input to access the ISERDESE2 module for decoding. Connect the other ultrasonic echo signal acquisition data channels to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory. One module decodes the FCLK frame signal, and the other modules decode the ultrasonic echo signal data channels.

[0015] Furthermore, if there is a misalignment in the decoding of the parallel echo data acquisition channels, generate a bitslip pulse to the ISERDESE2 module to perform an overall shift operation on the parallel output data and adjust the output data to shift to the correct data bit order.

[0016] Furthermore, wait for a set time after performing the shift operation. This set time is the same as the time required for internal shifting after receiving the bitslip pulse.

[0017] The second aspect of the present invention provides an ultrasonic echo signal acquisition error correction device, including:

[0018] A working module configuration module for configuring the ultrasonic echo signal acquisition to enter the normal working mode;

[0019] A signal decoding module for receiving the FCLK frame signal and decoding the FCLK frame signal;

[0020] A signal error correction module for determining whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the decoding of the parallel echo data acquisition channels. Pause the data acquisition process, generate a shift pulse, and perform a shift operation on the parallel output echo data until the decoding result meets the set conditions;

[0021] If it meets the conditions, the decoding is correct, start the echo data acquisition, and obtain the ultrasonic echo signal.

[0022] Further, the FCLK frame signal is used as a data input to access the ISERDESE2 module for decoding, and the data acquisition channels of other ultrasonic echo signals are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory. One module decodes the FCLK frame signal, and the other modules decode the data channels of the ultrasonic echo signals.

[0023] Further, in the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0024] Further, after performing the shift operation, wait for a set time, which is the same as the time required for internal shifting after receiving the bitslip pulse.

[0025] The third aspect of the present invention provides a computer-readable storage medium.

[0026] A computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps in an ultrasonic echo signal acquisition and error correction method as described above.

[0027] The fourth aspect of the present invention provides a computer device.

[0028] A computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in an ultrasonic echo signal acquisition and error correction method as described above.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] 1. By determining the generation timing of the bitslip pulse, the present invention discovers and corrects decoding errors without affecting normal operation, minimizing the time consumption of subsequent steps caused by data errors, and improving the working efficiency of ultrasonic flaw detection equipment.

[0031] 2. The present invention is applicable to most high-speed multi-channel ADC data acquisition scenarios using LVDS for communication, and is not specific to a certain FPGA platform. The situation described in this solution is to use the ISERDESE2 module for decoding on the xilinx ZYNQ platform. The decoding modules may be different in different FPGA integration schemes, but the method of using FCLK as the data input and decoding for comparison is universal.

[0032] 3. The present invention is applicable to data misalignment error correction of ADCs with different bit numbers. Correspondingly, only the number of all 1s or all 0s for comparison needs to be adjusted, and then the system method of the present invention can be used.

[0033] 4. The error correction of the method of the present invention takes a short time. Taking the decoding of 10-bit ADC data with a 50 MHz system clock as an example, in the worst case where all 10 bits are completely wrong and shifted 10 bits to the left or right, only 10×(3 + 1) = 40 system clocks are required to complete the error correction, and the time taken is 40×(1000000000 / 50000000) = 800 ns, which can meet the real-time requirements of the entire acquisition system. Compared with the traditional method of first configuring the ADC into the test mode, then performing comparison and error correction, and then configuring the ADC back to the normal mode, the efficiency is greatly improved. At the same time, it can also be used for ADCs that do not support the test mode.

[0034] 5. The present invention does not need to determine the specific data of the data source. The comparison data only comes from the result of the decoding module decoding the FCLK. The comparison result is used to control the bitslip shift operation of the decoding module, reducing the system design complexity and simplifying the development process.

[0035] Advantages of additional aspects of the present invention will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0037] Figure 1 is a schematic diagram of an LVDS signal;

[0038] Figure 2 is a schematic diagram of an LVDS data transmission channel;

[0039] Figure 3 is a schematic diagram of the ISERDESE2 decoding process;

[0040] Figure 4 is a flowchart of the ultrasonic echo signal acquisition and error correction method provided in this embodiment;

[0041] Figure 5 is a schematic diagram of the bitslip operation process provided in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0043] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0044] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0045] Term Explanation

[0046] LVDS (Low Voltage Differential Signaling) is a high-speed data transmission technology. As Figure 1 shown, it transmits data through differential signals and has advantages such as low power consumption, low noise, high bandwidth, and long-distance transmission. LVDS signals usually consist of a pair of differential pairs, CLKP and CLKN, and a pair of differential pairs can transmit one bit of data.

[0047] Bitslip is a function used in ISERDES (Input Serial to Parallel Converter) and is mainly used to rearrange the order of the parallel data stream entering the FPGA logic. Bitslip solves the data boundary alignment problem by delaying the data transmission by one clock cycle, enabling the data to realign to the word boundary.

[0048] Under normal operating conditions, LVDS transmission minimally has three channels, namely: the bit clock channel, the FCLK frame clock channel, and the DATA data channel;

[0049] Infinity Fabric Clock (FCLK) is the clock used in AMD processors to control the frequency of the Infinity Fabric communication bus. FCLK determines the operating performance of the Infinity Fabric and directly affects the data transmission speed and efficiency between components inside the processor.

[0050] As Figure 2The figure shows an LVDS data transmission channel. FCLK is an indication signal for data frame output. During the high and low levels of FCLK, they respectively represent a frame of data output on the DATA data line. The DATA channel is a data output channel. A 10 - bit data frame appears bit by bit in sequence starting from the high - order bit on the DATA channel. Its change frequency is the frequency of the clock signal on the BIT clock channel. The edge of FCLK is the start of a data frame. The ADC data is serially output through the LVDS data channel, and the frame clock indicates a complete ADC data through its high and low levels. For example, during the high - level period, the data of ADC channel 1 is transmitted, and during the low - level period, the data of ADC channel 2 is transmitted, alternating output to improve the utilization rate of the data line; the bit clock is used to indicate when the receiving end receives a new bit. The data bit is usually valid at the bit - clock transition edge, that is, DDR, and the data output frequency is twice that of the bit clock.

[0051] Using LVDS is usually for high - speed data transmission occasions. Generally, an FPGA platform is used for decoding and subsequent operations.

[0052] Using the xilinx zynq platform for decoding, the platform provides an ISERDESE2 module for receiving and decoding operations, as Figure 3 shown. It is a serial - to - parallel conversion module. The D interface is a serial data input interface. EDCBA are respectively the bit data input serially. Q1 - Q8 are parallel output ports. The serial data is serially input through the D interface and is parallel - output at the data output ports Q1 - Q8 after several clocks. CLK_RX is the clock of the serial data at the D end, and CLKDIV_RX is a divided - frequency version of the serial data clock at the D end, used to provide data - boundary differentiation.

[0053] The time from when the chip is powered on to when the clock is stable is very difficult to accurately predict. Therefore, it is not easy to determine the starting position of the data. However, Figure 2 as can be seen, the boundaries between two independent data are distinguished by the level of the FCLK clock. The unstable state after power - on can easily cause the misalignment of the starting position of the data. Therefore, the decoding module needs to provide an operation that can dynamically adjust the starting position of the decoded data through a pulse input signal to correct the data - shift error.

[0054] Moreover, there is also a problem. Even after the bit order has been adjusted correctly, due to problems such as temperature rise, the high - speed clock will generate jitter, resulting in data misalignment. Therefore, a reference data that is not affected by temperature or changes synchronously with the clock data is needed to dynamically adjust the bitslip to achieve data alignment.

[0055] Traditionally, the high-speed ADC chip has a test mode for LVDS output data. After the FPGA master chip is powered on, to confirm whether the data output by the ADC is correct, it will first set the LVDS interface of the ADC chip to the test mode. In the test mode, the DATA data channel of the LVDS usually outputs data in certain specific formats, such as all 1s or all 0s, which are used to assist the FPGA master in bit error correction. After the error correction is completed, the FPGA master then sets the LVDS interface of the ADC to the normal working mode, and the system can enter the working state.

[0056] Traditionally, the system startup requires two steps, namely the test mode and the normal mode, with a relatively long startup time. And it cannot be guaranteed that the switch is synchronous during the switching process. There may be a situation where the test mode is normal but the data in the normal mode is misaligned, resulting in the failure of the system startup.

[0057] The present invention abandons the two-step startup mode in the traditional situation. When the system is powered on, it directly configures the ADC to enter the normal mode. Through the solution of the present invention, the FPGA master end monitors the frame clock data output in real time and in parallel. Once an error is found, it starts the correction process, dynamically generates a bitslip pulse, and realizes automatic data error correction, greatly improving the startup speed of the system and reducing the probability of system startup failure.

[0058] Embodiment 1

[0059] As Figure 4 shown, this embodiment provides a data acquisition and error correction method. The present invention abandons the two-step startup mode in the traditional situation. When the system is powered on, it directly configures the ADC to enter the normal mode. Through this solution, the FPGA master end monitors the frame clock data output in real time and in parallel. Once an error is found, it starts the correction process, dynamically generates a bitslip pulse, and realizes automatic data error correction, greatly improving the startup speed of the system and reducing the probability of system startup failure.

[0060] Specifically, it includes the following steps:

[0061] Step 1: Configure the echo data acquisition to enter the normal working mode;

[0062] Traditionally, the system startup requires two steps, namely the test mode and the normal mode, with a relatively long startup time. And it cannot be guaranteed that the switch is synchronous during the switching process. There may be a situation where the test mode is normal but the data in the normal mode is misaligned, resulting in the failure of the system startup.

[0063] In this embodiment, directly configure the ADC to enter the normal mode;

[0064] Step 2: Receive the FCLK frame signal and decode the FCLK frame signal;

[0065] Connect the FCLK frame signal as data input to the ISERDESE2 module for decoding, and connect other ultrasonic echo signal acquisition data channels to the corresponding ISERDESE2 modules; in this way, there are multiple parallel ISERDESE2 modules in the system, one module decodes FCLK, and other modules decode DATA channels;

[0066] FCLK (Infinity Fabric Clock) is the internal bus frequency used to connect different cores and caches in AMD processors. FCLK is primarily used to coordinate data transmission between different modules within the CPU, ensuring data consistency and efficient transmission.

[0067] In this embodiment, decoding the FCLK frame signal specifically includes: connecting the FCLK frame to the D data input port of ISERDESE2, the data input clock is the bit clock, and finally outputting the data decoded from the FCLK at the output port of ISERDESE2.

[0068] Step 3: Determine whether the decoding result of the FCLK frame signal meets the set conditions. If not, there is a misalignment in the decoding of the parallel echo data acquisition channel. The data acquisition process is suspended, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions. If it does, the decoding is correct, echo data acquisition begins, and the ultrasonic echo signal is obtained.

[0069] In this embodiment, the ISERDESE2 module is used to decode the FCLK frame signal as an example. Figure 2 As shown, because the duration of FCLK high or low level is the same as the duration of a complete ADC data, that is, the duration of D0-D9 is the same as the high level duration of FCLK, D0-D9 is the bit position of a complete ADC data, that is, 10 bits of data, which are D 0, D 1, ... D 8， D9, its duration is 10 times the period of the bit clock. Therefore, if there is no decoding misalignment, the decoding output result of ISERDESE2 inputted by FCLK should be all 1s or all 0s, and the number of output bits should be the same as the number of bits of ADC output data. Next, determine whether the decoding result of ISERDESE2 inputted by FCLK is all 1s (or all 0s, low level condition).

[0070] Therefore, if the decoding result is not all 1s (or all 0s, low level), it can be determined that there is a misalignment in the ISERDESE2 module decoding.

[0071] In this embodiment, when there is a misalignment in the decoding of the ISERDESE2 module, a bitslip pulse is generated for the ISERDESE2 module to perform an overall shift operation on the parallel output data, so as to adjust the output data to shift in the bit order of the correct data.

[0072] The ISERDESE2 module provides a bitslip operation, that is, the sliding of bits. The external program only needs to give a pulse signal to the bitslip port at an appropriate time, and the ISERDESE2 module can automatically start a shift operation. For example, Figure 5 as shown Figure 5 is the block diagram of the bitslip function module of the Xilinx 7 series FPGA ISERDES2 module. The D interface is the input bit data, which are ABCD in sequence and output cyclically. CLK is the clock of the bit data, and CLKDIV is the divided-by-two version of CLK. Q4-Q1 are the parallel output data of the ISERDES2 module, and bitslip is the shift pulse input to ISERDES2. Before the bitslip pulse, the output of Q4-Q1 is CDAB, but the normal data input should be ABCD. Therefore, a shift adjustment is required. After the bitslip pulse, the output of Q4-Q1 is BCDA, which is a cyclic right shift of one bit as a whole relative to Q4-Q1 before the bitslip pulse. If another bitslip pulse is given, then Q4-Q1 can output ABCD, and the output shift error correction is completed.

[0073] The above is only a simple example. In actual situations, the decoding output shift situation is different each time the system is powered on. In this embodiment, by giving a pulse signal to the bitslip port at an appropriate time, the problem of misalignment in the decoding of the ISERDESE2 module is well solved.

[0074] Wait for three clocks (the time required for internal shifting after the ISERDESE2 receives a bitslip pulse), and then perform the above judgment process again until the decoding output is all 1 (or all 0, in the case of low level);

[0075] After the FCLK decoding is correct, the system outputs a pulse signal indicating that the data processing and storage module can operate normally;

[0076] During the normal operation of the data processing and storage module, the system will continuously monitor the FCLK decoding result until the system detects a decoding error situation again (the decoding result is not all 1 or all 0). The system sends a data error pulse to the subsequent data processing and storage module, pauses the subsequent processing, and then the system will enter the error correction process again until the error correction is completed.

[0077] The data acquisition error correction method of the present invention is applicable to most high-speed multi-channel ADC data acquisition scenarios using LVDS for communication. It is not specific to a certain FPGA platform. In this embodiment, the ISERDESE2 module is used for decoding on the ZYNQ platform of Xilinx for illustration. In different FPGA integration schemes, the decoding module may be different, but the method of using FCLK as the data input and decoding for comparison is common.

[0078] The data acquisition error correction method of the present invention is applicable to the data misalignment correction of ADCs with different bit numbers. Correspondingly, only the number of all-ones or all-zeros for comparison needs to be adjusted, and then the system method can be used.

[0079] The error correction of this system method takes a short time. Taking a 50MHz system clock and decoding 10-bit ADC data as an example, in the worst case where all 10 bits are completely misaligned to the left or right, only 10×(3 + 1)=40 system clocks are required to complete the error correction, and the time taken is 40×(1000000000 / 50000000)=800ns, which can meet the real-time requirements of the entire acquisition system. Compared with the traditional method of first configuring the ADC to the test mode, then performing comparison and error correction, and then configuring the ADC back to the normal mode, the efficiency is greatly improved, and it can also be used for ADCs that do not support the test mode.

[0080] This solution does not need to determine the specific data of the data source. The comparison data only comes from the result of decoding FCLK by ISERDESE2. The comparison result is used to control the bitslip shift operation of the decoding module, reducing the system design complexity and simplifying the development process.

[0081] Embodiment 2

[0082] This embodiment provides a data acquisition error correction device, including: [[ID=I7]]

[0083] A working module configuration module for configuring the acquisition of ultrasonic echo signals to enter the normal working mode;

[0084] A signal decoding module for receiving the FCLK frame signal and decoding the FCLK frame signal;

[0085] A signal error correction module for determining whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, there is a misalignment in the parallel echo data acquisition channels, the data acquisition process is paused, a shift pulse is generated, and a shift operation is performed on the parallel output echo data until the decoding result meets the set conditions; if it meets, the decoding is correct, and the echo data acquisition is started to obtain the ultrasonic echo signal.

[0086] In this embodiment, the FCLK frame signal is used as the data input to access the ISERDESE2 module for decoding, and the data channels for collecting other ultrasonic echo signals are connected to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory. One module decodes the FCLK frame signal, and the other modules decode the data channels of the ultrasonic echo signals.

[0087] In this embodiment, in the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, there is a misalignment in the decoding of the parallel echo data acquisition channels.

[0088] In this embodiment, in the signal error correction module, if there is a misalignment in the decoding of the parallel echo data acquisition channels, a bitslip pulse is generated to the ISERDESE2 module to perform an overall shift operation on the parallel output data and adjust the output data to shift in the bit order of the correct data.

[0089] In this embodiment, after performing the shift operation, wait for a set time, which is the same as the time required for internal shifting after receiving the bitslip pulse.

[0090] This device is applied to a highly integrated ultrasonic data acquisition system, such as a portable ultrasonic device, the ADC acquisition and error correction part of an ultrasonic flaw detection device, to solve the problem of data misalignment during high-speed ultrasonic data acquisition.

[0091] Embodiment III

[0092] This embodiment provides an ultrasonic flaw detection device, including an ADC acquisition module and the data acquisition and error correction device described in Embodiment II, and the ADC acquisition module is connected to the data acquisition and error correction device.

[0093] The specific implementation process of the data acquisition and error correction device is the same as that of Embodiment II.

[0094] Embodiment IV

[0095] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps in an ultrasonic echo signal acquisition and error correction method as described above.

[0096] Embodiment V

[0097] This embodiment provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in an ultrasonic echo signal acquisition and error correction method as described above.

[0098] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An ultrasonic echo signal acquisition and error correction method, characterized in that It includes the following steps: Configure the ultrasonic echo signal acquisition to enter the normal working mode; Receive the FCLK frame signal and decode the FCLK frame signal; Take the FCLK frame signal as the data input and connect it to the ISERDESE2 module for decoding. Connect the other ultrasonic echo signal acquisition data channels to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory. One module decodes the FCLK frame signal, and the other modules decode the ultrasonic echo signal data channels; Judge whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, the decoding of the parallel echo data acquisition channels is misaligned. Pause the data acquisition process, generate a shift pulse, and perform a shift operation on the parallel output echo data until the decoding result meets the set conditions; If it meets the conditions, the decoding is correct, start the echo data acquisition, and obtain the ultrasonic echo signal.

2. The method for collecting and correcting ultrasonic echo signals according to claim 1, characterized in that When the decoding result of the FCLK frame signal is not all 1 or all 0, the decoding of the parallel echo data acquisition channels is misaligned.

3. The method for collecting and correcting ultrasonic echo signals according to claim 1, characterized in that, If the decoding of the parallel echo data acquisition channels is misaligned, generate a bitslip pulse to the ISERDESE2 module to perform an overall shift operation on the parallel output data and adjust the output data to shift in the bit order of the correct data.

4. The ultrasonic echo signal acquisition and error correction method according to claim 1, wherein Wait for a set time after performing the shift operation. This set time is the same as the time required for internal shifting after receiving the bitslip pulse.

5. An ultrasonic echo signal acquisition and error correction device, characterized in that, It includes: A working module configuration module for configuring the ultrasonic echo signal acquisition to enter the normal working mode; A signal decoding module for receiving the FCLK frame signal and decoding the FCLK frame signal; Take the FCLK frame signal as the data input and connect it to the ISERDESE2 module for decoding. Connect the other ultrasonic echo signal acquisition data channels to the corresponding ISERDESE2 modules. There are multiple parallel ISERDESE2 modules in the memory. One module decodes the FCLK frame signal, and the other modules decode the ultrasonic echo signal data channels; A signal error correction module for judging whether the decoding result of the FCLK frame signal meets the set conditions. If the set conditions are not met, the decoding of the parallel echo data acquisition channels is misaligned. Pause the data acquisition process, generate a shift pulse, and perform a shift operation on the parallel output echo data until the decoding result meets the set conditions; If it meets the conditions, the decoding is correct, start the echo data acquisition, and obtain the ultrasonic echo signal.

6. The ultrasonic echo signal acquisition and error correction device according to claim 5, characterized in that, In the signal error correction module, when the decoding result of the FCLK frame signal is not all 1 or all 0, the decoding of the parallel echo data acquisition channels is misaligned.

7. The ultrasonic echo signal acquisition and error correction device according to claim 5, characterized in that, Wait for a set time after performing the shift operation. This set time is the same as the time required for internal shifting after receiving the bitslip pulse.

8. An ultrasonic flaw detection device, characterized in that, It includes an ADC acquisition module and the ultrasonic echo signal acquisition error correction device according to any one of claims 5 - 7, and the ADC acquisition module is connected to the data acquisition error correction device.

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