Chip test method, test equipment, test system and storage medium
By reading and comparing the unique identification code in the chip test method, detecting whether there are stacking or clamping problems in the chip to be tested, and supporting the chip that has passed the test for re-checking, the problem of stacking or clamping phenomena in chip test is solved, ensuring the accuracy and quality of the test.
Patent Information
- Application Number
- CN202510007862.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-25
AI Technical Summary
During the first Test (FT test) stage of the chip, stacking or pickling is prone to occur, which affects the test progress and quality control, and does not support the chips that have been tested for re-verification.
By reading and comparing the unique identification code in the chip test method, detecting whether there are stacking or clamping problems in the chip to be tested, and on the basis of supporting the chip that has passed the test for re-checking and testing, the original FT PASSID identification bit is retained to ensure that the chips tested are good products every time.
Effectively detect and deal with stacking or clamping problems, ensure the accuracy and quality of chip testing, and support the re-testing of good-quality chips, improving the reliability and efficiency of testing.
Smart Images
Figure CN119881593A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method, testing equipment, testing system and storage medium. Background Art
[0002] During the chip First Test (FT test, finished product test) stage, chip stacking or jamming is prone to occur. Stacking or jamming not only affects the chip testing progress, but may also lead to quality control failure, causing unqualified products to enter the next process or even flow directly to the market.
[0003] When checking for overlapping materials, an FT PASSID (FT test pass identification code) is usually written as an identification bit in the last test item of the test, and a test item for checking the FT PASS ID identification bit is set after the open-short circuit test. If the test equipment detects the FT PASSID identification bit, it means that the chip has been tested, that is, overlapping materials have occurred; if the test equipment does not detect the FT PASSID identification bit, it means that overlapping materials have not occurred. However, for "good" chips that have passed the test, since they are marked as "tested", additional verification cannot be performed again, and thus good retesting is not supported. Summary of the invention
[0004] The purpose of the present invention is to provide a chip testing method, testing equipment, testing system and storage medium, which can realize the inspection of stacking or jamming problems and support retesting of chips that have passed the test.
[0005] The technical solution provided by the present invention is as follows:
[0006] The present invention provides a chip testing method, comprising the following steps:
[0007] In the first test mode and / or the second test mode, an electrical connectivity test is performed on the chip to be tested; the unique identification code of the chip to be tested is read, and a determination is made as to whether the unique identification code is consistent with the unique identification code of the last chip that completed the test; if they are consistent, the chip to be tested has a material overlap or material jam problem, and the chip to be tested is classified as a first chip set; otherwise, the chip executes several other test items in the first test mode and / or the second test mode; the several other test items include current testing and functional testing.
[0008] Specifically, through the chip testing method proposed in the present invention, when executing the first test or the second test, the unique identification code is read and compared to detect whether the chip to be tested has overlapping or stuck problems. If there is a test abnormality, the chip needs to be classified and processed, and the chip that has passed the test can also be checked and tested again.
[0009] Furthermore, electrical connectivity tests are performed on the chip under test, including:
[0010] Establish a physical connection between the chip to be tested and the test equipment to detect whether the chip to be tested has an open or short circuit problem; if the chip to be tested does not have an open or short circuit problem, read the unique identification code of the chip to be tested; otherwise, classify the chip to be tested into the first chip set.
[0011] Specifically, through the chip testing method proposed by the present invention, the first test mode and the second test mode both include an electrical connectivity test (i.e., an open-short circuit test), which performs a preliminary screening of chips with physical problems, and if the chips fail, the chips to be tested are classified into the first chip set (i.e., a defective bin). For the chips that pass the preliminary test, the unique identification code is read again, and data support is provided for subsequent testing and tracking.
[0012] Furthermore, the chip under test executes several other test items in the first test mode and / or the second test mode, including:
[0013] If the chip under test passes several other test items in the first test mode and / or the second test mode, the chip under test is classified into the second chip set; the second chip set is a good chip; otherwise, the chip under test is classified into the first chip set; the first chip set includes pseudo-defective chips and defective chips.
[0014] Specifically, the chip testing method proposed in the present invention is helpful to distinguish good chips that meet the quality standards from defective chips that do not meet the standards. The first chip set may include some pseudo defective chips due to chip stacking or jamming problems, and these pseudo defective chips in the first chip set need to be tested again before they can be transferred to the second chip set.
[0015] Furthermore, before the chip under test executes other test items in the second mode, the following steps are performed:
[0016] Read the identification code in the identification register of the chip under test; determine whether the chip under test has the identification code, if not, classify the chip under test into the first chip set; otherwise, the chip under test continues to execute other test items.
[0017] Specifically, through the chip testing method proposed in the present invention, the original identification code for checking whether the chip has overlapping or stuck problems is retained, and when the second test mode is executed, it is checked whether the identification code is written, thereby ensuring that each sample inspection is of good quality.
[0018] Furthermore, after the chip under test executes several other test items of the first test mode, the process further includes:
[0019] If the chip under test passes other test items of the first test mode, an identification code indicating that the chip under test has passed the first test mode is written into the identification register of the chip under test.
[0020] Specifically, through the chip testing method proposed in the present invention, if the chip to be tested successfully passes all test items under the first test mode, a specific identification code will be written in the chip's identification register, indicating that the chip has passed the first test mode, so as to facilitate subsequent random inspection identification code identification.
[0021] Furthermore, in the first test mode, after executing the electrical connectivity test, if the electrical connectivity test passes, the unique identification code of the chip to be tested is read; it is determined whether the unique identification code is consistent with the unique identification code of the chip that last completed the first test; if not, several other test items of the first test mode are executed; it is determined whether several other test items of the first test mode pass the test; the first test mode is a finished product test.
[0022] Furthermore, in the second test mode, after the electrical connectivity test is performed, if the electrical connectivity test is passed, the unique identification code of the chip to be tested is read; it is determined whether the unique identification code is consistent with the unique identification code of the chip that last performed the second test; if not, the identification code of the chip to be tested is read; it is determined whether the chip to be tested has an identification code; if so, it is determined whether several other test items of the second test mode have passed the test; the second test mode is a good product quality control test.
[0023] The present invention also provides a testing device, comprising:
[0024] A test head is used to read the unique identification code of the chip to be tested; a test host is used to determine whether the unique identification code is consistent with the unique identification code of the previous chip to be tested; if they are inconsistent, the chip to be tested executes several test items in the first test mode and / or the second test mode; the several test items include current testing and functional testing; a test board is used to execute several test items in the first test mode and / or the second test mode and electrical connectivity testing on the chip to be tested.
[0025] The present invention also provides a chip testing system, comprising:
[0026] The chip to be tested is placed in the testing equipment for testing; the testing equipment performs an electrical connectivity test on the chip to be tested, reads the unique identification code of the chip to be tested, determines whether the unique identification code is consistent with the unique identification code of the previous chip to be tested, and executes several test items of the first test mode and / or the second test mode.
[0027] The present invention also provides a storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement any one of the chip testing methods described above.
[0028] Through the chip testing method, testing equipment, testing system and storage medium provided by the present invention, the unique identification code is read and compared to detect whether the chip to be tested has overlapping or stuck problems, while retaining the identification bit of the original detection method, thereby preventing overlapping and supporting retesting of chips that have passed the test, and ensuring that the chips sampled are all good products. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a chip testing method, testing equipment, testing system and storage medium.
[0030] Figure 1 is a flow chart of an embodiment of a chip testing method of the present invention;
[0031] Figure 2 is a flow chart of another embodiment of a chip testing method of the present invention;
[0032] Figure 3 is a flow chart of another embodiment of a chip testing method of the present invention;
[0033] Figure 4 is a flow chart of another embodiment of a chip testing method of the present invention;
[0034] Figure 5 is a flow chart of a specific embodiment of a chip testing method of the present invention;
[0035] Figure 6 It is a flow chart of another specific embodiment of a chip testing method of the present invention. DETAILED DESCRIPTION
[0036] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.
[0037] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.
[0038] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0039] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.
[0041] First Test (FT test, finished product test) is a series of electrical performance tests performed on packaged chips in the semiconductor industry. The main purpose of FT test is to ensure that the chip meets the design specifications in terms of function and performance. The test content mainly includes functional test to check whether the logic function of the chip is normal, and parameter test to measure the chip's voltage, current, frequency, timing and other electrical parameters.
[0042] During the chip First Test (FT test, finished product test) stage, chip stacking or jamming is prone to occur. Stacking or jamming not only affects the chip testing progress, but may also lead to quality control failure, causing unqualified products to enter the next process or even flow directly to the market.
[0043] In order to solve the problem of chip overlap or jam, a FTPASSID (FT test pass identification code) is usually written as the identification bit in the last test item of the test. After the open and short circuit test is passed, the FT PASSID identification bit test item is set to check. If the test equipment detects the FT PASSID identification bit, it means that the chip has been tested, that is, overlap has occurred; if the test equipment does not detect the FT PASSID identification bit, it means that no overlap has occurred.
[0044] However, when performing a sampling test on good products, the chips to be tested need to be extracted from the good product box that has already been tested. At this time, the chips to be tested have already been written with the FT PASSID identification bit. After performing the open-short circuit test, when judging the identification bit, since it is marked as "tested", additional verification cannot be performed again, and thus retesting of good products is not supported.
[0045] Therefore, the present invention proposes a chip testing method. When executing the first test, the unique identification code is read and compared to detect whether the chip to be tested has overlapping or stuck problems. When executing the second test, it supports retesting the chip that has completed the test and retains the FT PASSID identification bit, thereby ensuring that each sample is good.
[0046] The following is a description with reference to the accompanying drawings:
[0047] In one embodiment of the present invention, the chip testing system 100 includes: a chip to be tested 110 and a testing device 120 .
[0048] The chip to be tested 110 is placed in a testing device 120 for testing.
[0049] The testing device 120 performs an electrical connectivity test on the chip under test 110, reads the unique identification code of the chip under test, determines whether the unique identification code is consistent with the unique identification code of the previous chip under test, and executes several test items of the first test mode and / or the second test mode.
[0050] Specifically, the FT (First Test) test in which the chip to be tested 110 is placed in the test equipment 120 is an important part of the semiconductor finished product testing, which mainly includes environmental testing, aging testing and performance testing, such as simulating the impact of high temperature, low temperature, humidity and other environmental factors on chip performance.
[0051] The test device 120 first checks the stacking or stuck material problem through the unique identification code (UID) of the chip under test 110, and then determines whether the chip under test 110 passes several test items of the first test mode and / or the second test mode. If the chip passes all the test items, it will be marked as "good"; if it fails, further analysis and repair may be required.
[0052] Through the chip testing system proposed in the present invention, the testing equipment can detect the problems of overlapping or stuck materials occurring during the chip testing process, ensuring that each chip undergoes strict quality control, thereby improving the chip testing efficiency.
[0053] In one embodiment of the present invention, the test device 120 in the chip test system includes a test head 121 , a test host 122 and a test board 123 .
[0054] The test head 121 is used to read the unique identification code of the chip under test 110 .
[0055] The test host 122 is used to determine whether the unique identification code is consistent with the unique identification code of the previous chip under test; if inconsistent, the chip under test 110 executes several test items in the first test mode and / or the second test mode; the several test items include current testing and functional testing; the test host 122 is also used to determine whether the chip under test 110 passes several test items in the first test mode and / or the second test mode.
[0056] The test board 123 is used to perform a plurality of test items and an electrical connectivity test of the first test mode and / or the second test mode on the chip to be tested.
[0057] Specifically, the chip under test 110 is fixed on the test socket. In the electrical connectivity test (i.e., open and short circuit test), the test board 123 will move the probe to a specific test point of the chip under test 110, and the test equipment will apply voltage or current. If the response is not as expected, it means that the chip under test 110 has an open circuit or short circuit problem.
[0058] The test head 121 is a component that contacts the test points on the chip 110 to be tested. It is responsible for reading the unique identification code on the chip. The unique identification code is usually used to identify the serial number or batch number of the chip to ensure the traceability of the chip during the test process.
[0059] The test host 122 is the control center of the entire test equipment. It receives the unique identification code read by the test head 121 and compares it with the identification code of the previous chip to be tested. If the identification codes are inconsistent, it means that it is a new chip to be tested. The test host will guide the chip to be tested 110 to enter the first test mode and / or the second test mode, and determine whether the chip to be tested 110 has passed these test items.
[0060] In the first test mode or the second test mode, the test board 123 will execute several test items, such as current test, voltage test, function test and environment test, etc. These test items are mainly used to evaluate the electrical characteristics and functional characteristics of the chip.
[0061] Through the testing equipment proposed by the present invention, the probe station, the test head, the test host and the test board work together to detect the quality and performance of the chip to be tested.
[0062] In one embodiment of the present invention, Figure 1 As shown, it shows a flow chart of a chip testing method performed by the above-mentioned testing device 120 of the present disclosure, comprising the following steps:
[0063] S100 performs an electrical connectivity test on the chip under test in the first test mode and / or the second test mode.
[0064] S200 reads the unique identification code of the chip to be tested, and determines whether the unique identification code is consistent with the unique identification code of the previous chip to be tested.
[0065] If S300 is consistent, the chip under test has a material overlap or material jam problem, and the chip under test is classified as a first chip set; otherwise, the chip under test executes other test items in the first test mode and / or the second test mode; the other test items include current test and function test.
[0066] Specifically, the first test mode of the chip is the finished product test (FT, First Test), and the second test mode is the good quality control test (EQC, Excellent Quality Control). Among them, the good quality control test is carried out after the chip is packaged. The main purpose is to verify the internal burning code of the chips that have passed the test, and check whether there are wrong burning code products in the chips to be tested. When the good quality test fails, these chips will be re-tested.
[0067] In the first test mode and / or the second test mode, an electrical connectivity test (i.e., open and short circuit test) needs to be performed on the chip under test, which means that a series of electrical contact tests need to be performed on the chip under test under two different test configurations or conditions to verify the integrity and functionality of its circuit.
[0068] The unique identification code is unique, which includes the chip's LOT number (wafer batch number), SLOT number (wafer number) and the X / Y coordinates of the wafer chip, a total of 11 bytes. Read the unique identification code on the corresponding address of the chip to be tested, and store the read information in the system variables of the test equipment, and then use the test equipment command to judge and print the system variables.
[0069] According to the rules of the unique identification code, the card control is set to make judgments. When the judgment is passed, the unique identification code read is printed in the test data. The data of the chip can be found through the test data and compared with the unique identification code of the previous tested chip. If the 11Byte is exactly the same, it is judged to be the same chip and the material overlap has occurred. Card control is the control of key parameters of the chip to ensure that the product quality meets the standards. For example, the LOT number of the chip to be tested is AL450, and the wafer number is 0 to 16.
[0070] If the chip under test has overlapping or stuck material problems, the chip is classified as the first chip set. The chip under test with overlapping material can be good or defective. The first chip set refers to the chip set that needs further inspection or retesting to ensure the accuracy of the test process and the quality of the chip.
[0071] If the chip under test has no overlapping or stuck problems, it means that the test process is normal, and the chip under test will continue to execute the first test mode and / or other test items in the second test mode including current test, function test, and environmental test.
[0072] In this embodiment, through the chip testing method proposed in the present invention, when executing the first test or the second test, the unique identification code is read and compared to detect whether the chip to be tested has overlapping or stuck problems. If there is a test abnormality, the chip needs to be classified and processed, and the chip that has passed the test can also be checked and tested again.
[0073] In one embodiment of the present invention, Figure 2 As shown, to perform an electrical connectivity test on the chip to be tested, the above step S100 may include:
[0074] S110 establishes a physical connection between the chip under test and the test equipment to detect whether the chip under test has an open or short circuit problem.
[0075] S120: If the chip under test does not have an open-short circuit problem, read the unique identification code of the chip under test; otherwise, classify the chip under test into the first chip set.
[0076] Specifically, the electrical connectivity test can be an open-short circuit test. The open-short circuit test is usually placed at the front of the test program. Its main task is to verify whether the physical connection between the chip under test and the test equipment is normal, to ensure the smoothness of signal transmission, and it is also the basis for subsequent more complex electrical and physical tests.
[0077] If the chip under test fails the open-short test, the chip must be defective and will be classified as a first chip set. If there is an open circuit or short circuit problem between the pins of the chip under test, the subsequent electrical and physical test results may be affected, resulting in inaccurate test results. Therefore, performing O / S testing first can ensure the accuracy of subsequent tests.
[0078] In this embodiment, through the chip testing method proposed by the present invention, the first test mode and the second test mode both include electrical connectivity tests, which perform preliminary screening of chips with physical problems. If the test fails, the chips to be tested are classified into the first chip set. For the chips that pass the preliminary inspection, the unique identification code is read again to provide data support for subsequent testing and tracking.
[0079] In one embodiment of the present invention, Figure 3 As shown, the chip under test executes other test items in the first test mode and / or the second test mode, and the above step S300 also includes:
[0080] S310: If the chip to be tested passes other test items in the first test mode and / or the second test mode, the chip to be tested is classified into a second chip set; the second chip set is a good chip.
[0081] S320: Otherwise, the chips to be tested are classified into a first chip set; the first chip set includes pseudo defective chips and defective chips.
[0082] Specifically, after the unique identification code test is passed, if the chip under test fails to meet the standard in any subsequent test items, then the chip will be classified into the first chip set, which includes chips that need further analysis, repair or scrapping.
[0083] If the chip under test successfully passes all subsequent test items, that is, meets all performance and functional requirements, then the chip will be classified as the second chip set.
[0084] In this embodiment, the chip testing method proposed by the present invention is helpful to distinguish good chips that meet the quality standards from defective chips that do not meet the standards. The first chip set may include some pseudo defective chips due to chip stacking or jamming problems, and these pseudo defective chips in the first chip set need to be tested again before they can be transferred to the second chip set.
[0085] In one embodiment of the present invention, Figure 4 As shown, before the chip under test executes other test items in the second mode, the above step S310 includes:
[0086] S311 reads the identification code in the identification register of the chip to be tested.
[0087] S312 determines whether the chip under test has an identification code. If not, the chip under test is classified into the first chip set; otherwise, the chip under test continues to execute other test items.
[0088] Specifically, the present invention reserves the FT PASSID identification bit, and after the chip under test executes several other test items of the first test mode, further includes the step of: if the chip under test passes several other test items of the first test mode, writing an identification code indicating that it has passed the first test mode in the identification register of the chip under test.
[0089] In the second test mode (EQC test mode), the good chips are tested again. In order to ensure that the chips sampled are good, the original FT PASSID identification bit is still retained. By judging the identification bit, it is ensured that the sampled chips are good, which enhances the accuracy and effectiveness of the test and reduces the error rate.
[0090] In this embodiment, the chip testing method proposed by the present invention retains the original identification code for checking whether the chip has overlapping or stuck problems. When executing the second test mode, it is checked whether the identification code is written, thereby ensuring that each sample is good.
[0091] like Figure 5 As shown in the figure, it is the original flow chart of FT test for the chip to be tested. The original flow uses FT identification code to check for chip overlap or stuck problems. If the FT identification code has been written, it means that the chip has been tested and overlap has occurred. However, when the good chip needs to be retested, the subsequent test process cannot be executed because the FT identification code has been written.
[0092] like Figure 6 As shown, it is a flow chart of the FT test using a unique identification code proposed by the present invention. In the FT test mode, the unique identification code of the chip to be tested is read. When it is determined that the UID information of the chip to be tested is completely consistent with that of the previous chip, the chip to be tested may be a good product or a defective product, so it is divided into BINs and put into the defective box for re-inspection. The EQC test mode not only retains the detection and judgment of the FT identification code, but also adds the operation of reading the unique identification code and making a judgment. First, the unique identification code of the chip to be tested is read to determine whether the chip to be tested has overlapped materials, and then the FT identification code of the chip to be tested is read. This can prevent mixing of materials (ensuring that all samples sampled in the EQC mode are good products), and can prevent overlap and jamming of materials, thereby enhancing the accuracy and effectiveness of the test and reducing the error rate.
[0093] One embodiment of the present invention is a storage medium, in which at least one instruction is stored, and the instruction is loaded and executed by a processor to implement the operations performed by the corresponding embodiment of the above chip testing method. For example, the storage medium can be a read-only memory (ROM), a random access memory (RAM), a read-only compact disk (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.
[0094] They can be implemented with program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.
[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0096] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0097] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.
Claims
1. A chip testing method, characterized in that: The following steps are involved: In the first test mode and / or the second test mode, performing an electrical connectivity test on the chip to be tested; Read the unique identification code of the chip to be tested, and determine whether the unique identification code is consistent with the unique identification code of the last chip that has completed the test; If they are consistent, the chip under test has overlapping or stuck material problems, and the chip under test is classified as a first chip set; otherwise, the chip under test executes several other test items in the first test mode and / or the second test mode; the several other test items include current test and functional test.
2. The chip testing method according to claim 1, characterized in that: The electrical connectivity test of the chip to be tested includes: Establishing a physical connection between the chip under test and a test device to detect whether the chip under test has an open-short circuit problem; If the chip under test does not have the open-short circuit problem, the unique identification code of the chip under test is read; otherwise, the chip under test is classified as the first chip set.
3. The chip testing method according to claim 1, characterized in that: The chip under test executes several other test items in the first test mode and / or the second test mode, including: If the chip under test passes other test items in the first test mode and / or the second test mode, the chip under test is classified as a second chip set; the second chip set is a good chip; Otherwise, the chip to be tested is classified into the first chip set; the first chip set includes pseudo defective chips and defective chips.
4. The chip testing method according to claim 1, characterized in that: Before the chip under test executes other test items in the second mode, the method includes: Reading the identification code in the identification register of the chip to be tested; It is determined whether the chip under test has the identification code. If not, the chip under test is classified into the first chip set; otherwise, the chip under test continues to execute other test items.
5. The chip testing method according to claim 1, characterized in that: After the chip under test executes other test items of the first test mode, the method includes: If the chip under test passes other test items of the first test mode, an identification code indicating that the chip under test has passed the first test mode is written into the identification register of the chip under test.
6. The chip testing method according to any one of claims 1 to 5, characterized in that: In the first test mode, after executing the electrical connectivity test, if the electrical connectivity test is passed, reading the unique identification code of the chip to be tested; Determine whether the unique identification code is consistent with the unique identification code of the chip that last executed the first test, and if not, execute other test items of the first test mode; Determine whether other test items of the first test mode pass the test; the first test mode is a finished product test.
7. The chip testing method according to any one of claims 1 to 5, characterized in that: In the second test mode, after executing the electrical connectivity test, if the electrical connectivity test is passed, reading the unique identification code of the chip to be tested; Determine whether the unique identification code is consistent with the unique identification code of the chip that has completed the second test last time, and if not, read the identification code of the chip to be tested; Determine whether the chip under test has the identification code. If so, determine whether other test items of the second test mode pass the test; the second test mode is a good product quality control test.
8. A testing device, characterized in that: include: A test head, used to read the unique identification code of the chip to be tested; A test host, used to determine whether the unique identification code is consistent with the unique identification code of the last chip to be tested; If they are inconsistent, the chip under test executes several test items in the first test mode and / or the second test mode; the several test items include current test and function test; A test board is used to perform several test items and electrical connectivity tests of the first test mode and / or the second test mode on the chip to be tested.
9. A chip testing system, characterized in that: include: The chip to be tested is placed in a testing device for testing; The testing device performs an electrical connectivity test on the chip to be tested, reads a unique identification code of the chip to be tested, determines whether the unique identification code is consistent with a unique identification code of a previous chip to be tested, and executes several test items of a first test mode and / or a second test mode.
10. A storage medium, characterized in that: The storage medium stores at least one instruction, and the instruction is loaded and executed by the processor to implement the chip testing method according to any one of claims 1 to 7.