Method for searching trigger point based on automatic testing machine

Abstract

A method for searching a trigger point based on an automatic test machine comprises the following steps: selecting n + 1 segment points based on a value range of a working electric signal of a chip to be tested, and dividing the value range of a test electric signal provided by the automatic test machine into n segments, the segment where the trigger point is located is determined based on the test electric signals corresponding to at least one part of the n + 1 segment points, and n is a positive integer and is larger than or equal to 2; and (m + 1) test points are selected from the segment where the trigger point is located based on the test precision required by the chip to be tested, the trigger point is determined based on the (m + 1) test points and the test electric signals corresponding to at least one part of the two segments corresponding to the segment where the trigger point is located, and m is a positive integer and is greater than or equal to 2.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a method for finding a trigger point based on an automatic testing machine. Background Art

[0002] The field of integrated circuit testing technology belongs to the core industry of the new generation of information technology industry and has an extremely important strategic position. After integrated circuits, such as chips, are packaged, various tests are required to meet subsequent application requirements. Integrated circuit testing includes CP testing and FT testing. CP testing, also known as wafer testing, is a test performed after wafer manufacturing is completed and before chip packaging. FT testing, also known as final testing, is a test performed after chip packaging is completed. It is the last interception before the chip leaves the factory. Integrated circuit testing requires as accurate and fast execution as possible. The accuracy of test values ​​is indispensable for circuit design and device performance evaluation. Rapid execution of batch testing is also crucial for integrated circuit testing. Summary of the invention

[0003] The purpose of the present disclosure is to provide a method for finding a trigger point based on an automatic testing machine, the method comprising the following steps:

[0004] Based on the value range of the working electrical signal of the chip to be tested, n+1 segmentation points are selected to divide the value range of the test electrical signal provided by the automatic test machine into n segments, and based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the segment where the trigger point is located is determined, wherein n is a positive integer and n≥2;

[0005] Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the trigger point is determined based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located, wherein m is a positive integer and m≥2.

[0006] In some embodiments, the step of selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points includes the following steps:

[0007] Based on the value range of the working electrical signal of the chip to be tested, n+1 segmentation points are selected to divide the value range of the test electrical signal provided by the automatic tester into n uniform segments, wherein the increment of the test electrical signal corresponding to each segment is equal;

[0008] The test electrical signals corresponding to the n+1 segmentation points are discretely provided to the chip under test in sequence, the segmentation points where the state of the chip under test changes are determined, and then the segment where the trigger point of the chip under test is located is confirmed.

[0009] In some embodiments, the step of selecting m+1 test points in the segment where the trigger point is located based on the test accuracy required by the chip to be tested, and determining the trigger point based on the test electrical signals corresponding to the m+1 test points and at least a portion of the two segments corresponding to the segment where the trigger point is located comprises the following steps:

[0010] Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the m+1 test points divide the test electrical signal corresponding to the segment where the trigger point is located into m uniform sections, wherein the increment of the test electrical signal corresponding to each section is equal, and the increment of the test electrical signal corresponding to each section is substantially equal to the test accuracy required by the chip to be tested;

[0011] The test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence, the test points where the state of the chip under test changes are determined, and then the trigger point of the chip under test is confirmed.

[0012] In some embodiments, the step of discretely providing the test electrical signals corresponding to the n+1 segment points to the chip under test in sequence, determining the segment points where the state of the chip under test changes, and then confirming the segment where the trigger point of the chip under test is located includes:

[0013] The test electrical signals corresponding to the n+1 segmentation points are discretely provided to the chip to be tested in sequence until the test electrical signal corresponding to the i-th segmentation point is input to change the state of the chip to be tested, and the segment between the i-1-th segmentation point and the i-th segmentation point is determined as the segment where the trigger point of the chip to be tested is located, where i is a positive integer and n+1≥i≥2.

[0014] In some embodiments, discretely providing the test electrical signals corresponding to the m+1 test points to the chip under test in sequence, determining the test point at which the state of the chip under test changes, and then confirming the trigger point of the chip under test includes:

[0015] The test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence until the test electrical signal corresponding to the j-th test point is input to change the state of the chip under test, and the test electrical signal corresponding to the j-th test point or the j-1-th test point is determined as the trigger point for the majority of the chips under test, where j is a positive integer and m+1≥j≥1.

[0016] In some embodiments, n and m satisfy the following formula:

[0017]

[0018] Wherein, T represents the increment of the value range of the working electrical signal of the chip to be tested, and Δ represents the test accuracy required by the chip to be tested.

[0019] In some embodiments, n and m are determined based on the principle that the sum of n+1 and m+1 is as small as possible.

[0020] In some embodiments, before selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the method further includes the following steps:

[0021] The plurality of chips to be tested are placed on a plurality of test stations of an automatic test machine respectively, and a plurality of analog test electrical signals are provided to the plurality of chips to be tested respectively.

[0022] In some embodiments, when the test electrical signals corresponding to the n+1 segment points are discretely provided to the chip under test in sequence, the discrete test duration of each segment point is greater than or equal to the response time of the chip under test.

[0023] In some embodiments, when the test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence, the discrete test duration of each test point is greater than or equal to the response time of the chip under test.

[0024] Compared with the related art, the embodiments of the present disclosure have the following technical effects:

[0025] The present invention provides a method for finding trigger points based on an automatic test machine. The method divides the value range of the working electrical signal of the chip to be tested into segments, firstly determines the segment where the trigger point is located, and then performs a scan test on the segment where the trigger point is located to determine the trigger point of the chip to be tested. The automatic test machine can be used to find the trigger point of each chip to be tested by synchronously scanning multiple chips to be tested, thereby reducing the test time of batch testing while ensuring the test accuracy, improving the test efficiency and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0027] Figure 1 A flowchart of a method for finding a trigger point based on an automatic testing machine provided in some embodiments of the present disclosure;

[0028] Figure 2 A schematic diagram of a rough scanning waveform of a test electrical signal provided in some embodiments of the present disclosure;

[0029] Figure 3 A schematic diagram of a fine scanning waveform of a test electrical signal provided in some embodiments of the present disclosure;

[0030] Figure 4 for Figure 1 Flow chart of step S100;

[0031] Figure 5 for Figure 1 Flow chart of step S200;

[0032] Figure 6 A schematic diagram of the circuit structure of a chip to be tested provided in some embodiments of the present disclosure;

[0033] Figure 7 for Figure 6 The waveform diagram of the chip under test when performing a rough scan;

[0034] Figure 8 for Figure 6 Waveform diagram when the chip under test is scanned in detail. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. The singular forms "a", "said" and "the" used in the embodiments of the present disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0037] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0038] It should be understood that although the terms first, second, third, etc. may be used to describe in the present disclosure, these should not be limited to these terms. These terms are only used to distinguish. For example, without departing from the scope of the present disclosure, the first may also be referred to as the second, and similarly, the second may also be referred to as the first.

[0039] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such product or device. In the absence of more restrictions, the elements defined by the sentence "comprises a" do not exclude the presence of other identical elements in the product or device including the elements.

[0040] The present disclosure uses an automatic test machine, for example, an AWG function of an automatic test machine of an ETS-88 machine, to perform the test. The following describes the working principle of the AWG full scan of the automatic test machine:

[0041] AWG arbitrary waveform generator can send an excitation signal of arbitrary waveform to the chip. AWG is mostly used in analog chip testing. Analog signals are different from digital signals. Analog signals are continuous signals, which can be voltage, current or any other physical quantity. Their changes are continuous and can be infinitely close to any value. Digital signals are discrete signals that can only take a finite number of different values, usually binary, and are used to represent information. Analog signals can be approximately regarded as continuous signals composed of n discrete points. When the value of n is higher, the closer it is to the real waveform, and vice versa, the more distorted it is. When there are enough sampling points, we can get a signal that is infinitely close to the real continuous waveform. The more discrete points the automatic test machine uses AWG to generate waveforms, the closer it is to the accurate test value.

[0042] When the chip needs a continuously changing signal to find the trigger point, that is, the test threshold, the essence is that the automatic test machine transmits the test conditions represented by each discrete point of this signal, such as the corresponding test electrical signal, into the chip one by one, and synchronously monitors the corresponding output on the pin of the chip to be tested at each time point, and finds the value of the input condition corresponding to the time point that changes the output state, such as voltage reversal or circuit conduction, which is the threshold. Therefore, each discrete point can be approximately regarded as a transient voltage or current condition, and the time interval between each two discrete points is also the clock interval set by the automatic test machine, which is slightly longer than the response time of the chip to be tested in most cases. After turning on the AWG function in the control program of the automatic test machine, it is necessary to set the parameters of this waveform, including the number of discrete points of the waveform and the value it represents. The main focus of this disclosure is the number of discrete points. Too few discrete points will cause waveform distortion and test value deviation; too many discrete points will cause a significant increase in test time.

[0043] In the related technology 1, the AWG function of the automatic test machine is used to send a waveform to the chip under test, and the waveform is scanned throughout to find the trigger point, that is, the threshold. After the voltage or current conditions represented by each discrete point of the excitation signal are transmitted to the chip under test one by one, the chip under test will have a corresponding output, so that the output waveform curve can be drawn point by point. We call this process scanning waveform. This method will take a long time when the number of scanning points is large, which is not conducive to improving test efficiency.

[0044] In the related technology 2, the binary search method is used to find the target trigger point, that is, the threshold. When this test method is used, when the test is multi-site (multiple chips are tested in parallel), it will greatly limit the resource boards that can be selected by the automatic tester, and it is difficult to send different voltage values ​​to different sites (chips in different test positions) at the same time. Only serial testing can be performed, which will also take more time.

[0045] In order to overcome the above problems, the present disclosure provides a method for finding a trigger point based on an automatic testing machine, the method comprising the following steps: selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic testing machine into n segments, and determining the segment where the trigger point is located based on the test electrical signals corresponding to at least a part of the n+1 segmentation points, wherein n is a positive integer and n≥2; selecting m+1 test points in the segment where the trigger point is located based on the test accuracy required by the chip to be tested, and determining the trigger point based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located, wherein m is a positive integer and m≥2.

[0046] The present invention provides a method for finding trigger points based on an automatic test machine. The method divides the value range of the working electrical signal of the chip to be tested into segments, firstly determines the segment where the trigger point is located, and then performs a scan test on the segment where the trigger point is located to determine the trigger point of the chip to be tested. The automatic test machine can be used to find the trigger point of each chip to be tested by synchronously scanning multiple chips to be tested, thereby reducing the test time of batch testing while ensuring the test accuracy, improving the test efficiency and reducing the production cost.

[0047] The optional embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0048] Figure 1 A flowchart of a method for finding a trigger point based on an automatic test machine provided in some embodiments of the present disclosure. Figure 1 As shown, some embodiments of the present disclosure provide a method for finding a trigger point based on an automatic test machine, such as an automatic test machine using an ETS-88 machine. The method includes the following steps:

[0049] S100: selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, wherein n is a positive integer and n≥2;

[0050] S200: Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the trigger point is determined based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located, wherein m is a positive integer and m≥2.

[0051] That is to say, the embodiments of the present disclosure divide the process of finding trigger points based on the automatic test machine into two steps: coarse scanning and fine scanning, and no longer perform a full scan of all discrete points like in the related art. Figure 2 A schematic diagram of a rough scanning waveform of a test electrical signal provided in some embodiments of the present disclosure, Figure 3 A schematic diagram of a fine scanning waveform of a test electrical signal provided in some embodiments of the present disclosure.

[0052] Combination Figures 1 to 3As shown, firstly, step S100 is used to perform a rough scan, and all discrete points are first segmented into an appropriate number of segments, for example, 5 segments, and only the value of each segment point is scanned, so the number of scans is the number of segment points, for example, 6. At the same time, by monitoring the state changes of the output pins of the chip to be tested, and comparing the output of each segment point, it can be obtained that in the current segment, the target state has been triggered or has not been triggered. Through a rough scan, it can be detected that the trigger point is located in a certain segment, such as the third segment, but the detailed position is still uncertain. This step only greatly narrows the positioning range. Because the target value is not in other segments, they will no longer participate in the subsequent steps.

[0053] Then, a fine scan is performed in step S200. After eliminating most of the irrelevant values, a full scan is performed only on the segment where the trigger point is located, such as the third segment. The number of discrete points that need to be scanned in the segment where the trigger point is located has been greatly reduced compared to the full scan method in the related art. Only the test code needs to be modified to ignore the irrelevant segments in the coarse scan. The trigger point found in this step is the final value with higher accuracy.

[0054] Figure 4 for Figure 1 The flowchart of step S100 is as follows: Figure 4 As shown, in some embodiments, step S100: based on the value range of the working electrical signal of the chip to be tested, n+1 segmentation points are selected to divide the value range of the test electrical signal provided by the automatic tester into n segments, and based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the segment where the trigger point is located is determined, including the following steps:

[0055] S110: selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n uniform segments, wherein the increment of the test electrical signal corresponding to each segment is equal;

[0056] Specifically, even segmentation is helpful for quickly determining the segment where the trigger point is located and is beneficial for program execution of the automatic test machine.

[0057] S120: discretely providing the test electrical signals corresponding to the n+1 segment points to the chip under test in sequence, determining the segment points where the state of the chip under test changes, and further confirming the segment where the trigger point of the chip under test is located.

[0058] In the coarse scanning stage, the number of discrete detection points is n+1. Specifically, Figure 2 As shown, taking 6 segment points as an example, the output pins of the chip under test corresponding to points ①②③ are in an untriggered state, and the output pins of the chip under test corresponding to points ④⑤⑥ are in a triggered state. It can be determined that the trigger point is between ③ and ④, and there are 6 discrete detection points.

[0059] Figure 5 for Figure 1 The flowchart of step S200 is as follows: Figure 5 As shown, in some embodiments, step S200: selecting m+1 test points in the segment where the trigger point is located based on the test accuracy required by the chip to be tested, and determining the trigger point based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located includes the following steps:

[0060] S210: Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the m+1 test points divide the test electrical signal corresponding to the segment where the trigger point is located into m even sections, wherein the increment of the test electrical signal corresponding to each section is equal, and the increment of the test electrical signal corresponding to each section is substantially equal to the test accuracy required by the chip to be tested;

[0061] Specifically, Figure 3 As shown, the number of discrete points in the third segment of the waveform between point ③ and point ④ is redistributed. This time the number needs to be calculated and is basically equal to or slightly greater than the required test accuracy. The difference between every two points is the accuracy.

[0062] S220: discretely providing the test electrical signals corresponding to the m+1 test points to the chip under test in sequence, determining the test points where the state of the chip under test changes, and further confirming the triggering point of the chip under test.

[0063] Then, these discrete points are scanned in sequence, and the test electrical signals corresponding to each test point are sequentially input into the input pins of the chip under test, and its output pins are detected at the same time, so that the trigger point can be accurately determined. In the coarse scanning stage, the number of discrete detection points is m+1.

[0064] In some embodiments, step S120: discretely providing the test electrical signals corresponding to the n+1 segment points to the chip under test in sequence, determining the segment points where the state of the chip under test changes, and then confirming that the segment where the trigger point of the chip under test is located includes:

[0065] The test electrical signals corresponding to the n+1 segmentation points are discretely provided to the chip to be tested in sequence until the test electrical signal corresponding to the i-th segmentation point is input to change the state of the chip to be tested, and the segment between the i-1-th segmentation point and the i-th segmentation point is determined as the segment where the trigger point of the chip to be tested is located, where i is a positive integer and n+1≥i≥2.

[0066] For example, Figure 2As shown in the figure, the test scan from point ① to point ⑥ is executed in sequence. The output pins of the chip to be tested corresponding to points ①②③ are in the untriggered state. When the output pins of the chip to be tested corresponding to point ④ are detected to be in the triggered state, it can be determined that the trigger point is between ③ and ④, and there is no need to detect points ⑤ and ⑥. This method does not require monitoring of all segmented points, further reducing the number of discrete detection points, reducing monitoring time, and improving monitoring efficiency.

[0067] In some embodiments, step S220: discretely providing the test electrical signals corresponding to the m+1 test points to the chip under test in sequence, determining the test point at which the state of the chip under test changes, and then confirming the trigger point of the chip under test includes:

[0068] The test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence until the test electrical signal corresponding to the j-th test point is input to change the state of the chip under test, and the test electrical signal corresponding to the j-th test point or the j-1-th test point is determined as the trigger point for the majority of the chips under test, where j is a positive integer and m+1≥j≥1.

[0069] Similarly, this method does not require monitoring of all test points, further reducing the number of discrete detection points, reducing monitoring time, and improving monitoring efficiency.

[0070] In some embodiments, n and m satisfy the following formula:

[0071]

[0072] Wherein, T represents the increment of the value range of the working electrical signal of the chip to be tested, and Δ represents the test accuracy required by the chip to be tested.

[0073] The positive integer n represents the number of segments during coarse scanning, and the positive integer m represents the number of sections where the trigger point is located during fine scanning. Only when the above formula is satisfied can the accuracy of the final trigger point be guaranteed.

[0074] In some embodiments, n and m are determined based on the following principle that the sum of n+1 and m+1 is as small as possible. Based on the limitation of the accuracy of the detection trigger point in the previous formula, and the test time of each discrete detection point cannot be reduced indefinitely, it needs to be greater than or equal to the response time of the chip to be tested. In order to shorten the detection time, the values ​​of n and m can be reasonably designed so that the sum of n+1 and m+1 is as small as possible, that is, the discrete detection points are minimized as much as possible.

[0075] In some embodiments, Figure 1As shown, step S100: before selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the method further includes the following steps:

[0076] S010: placing a plurality of chips to be tested respectively at a plurality of test stations of an automatic test machine, and providing a plurality of analog test electrical signals respectively for the plurality of chips to be tested.

[0077] In batch testing of chips, the automatic tester can provide analog test electrical signals to multiple test tasks at the same time, and multiple chips to be tested can be tested in parallel using a combination of coarse scanning and fine scanning to determine the trigger point.

[0078] In some embodiments, when the test electrical signals corresponding to the n+1 segment points are discretely provided to the chip under test in sequence, the discrete test duration of each segment point is greater than or equal to the response time of the chip under test.

[0079] In some embodiments, when the test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence, the discrete test duration of each test point is greater than or equal to the response time of the chip under test.

[0080] This ensures the accuracy of the output pin signal of the chip under test, thereby ensuring the accuracy of the chip test.

[0081] The technical solution of the present disclosure is further clarified by taking a specific example as follows.

[0082] Figure 6 A schematic diagram of the circuit structure of a chip to be tested provided in some embodiments of the present disclosure, such as Figure 6 As shown, the MOS tube M1 in the chip to be tested needs to test the turn-on voltage Von. According to the data sheet of the chip to be tested, the output response time is 200μS, the operating voltage V1 is not less than 4.5V and not higher than 5.5V, and the current when fully turned on is V2 / R2=5V / 5Ω=1A. It is necessary to find the voltage threshold point that makes the MOS tube M1 turned on, that is, when the current reaches 10mA (equivalent to 1% of full conduction), the test accuracy is 10mV.

[0083] Figure 7 for Figure 6 The waveform diagram of the chip under test when performing a rough scan. Figure 8 for Figure 6 Waveform diagram when the chip under test is scanned in detail.

[0084] like Figure 7As shown in the figure, the voltage waveform of 4.5V to 5.5V that needs to be input to the MOS tube M1 is divided into 10 segments every 100mV, and 11 voltage points, i.e. segmentation points, are set, corresponding to 11 output current measurements, and the program setting of the automatic test machine is controlled to find the point corresponding to 10mA. At this time, the test machine returns a floating point number 3.278, indicating that the 3.278th point is the point corresponding to the target value 10mA. The point number needs to be forcibly converted to an integer through the code, for example, rounding down. The information fed back by this return value is: the trigger point, i.e. the voltage threshold point, is sampled between the 3rd and 4th voltage points, and the rough scan is successful.

[0085] The detailed scanning steps are as follows Figure 8 As shown, according to the previous step, it can be determined that the trigger point is located in the third section of the rough scan, that is, between 4.7V and 4.8V. At this time, 4.7V to 4.8V is divided into sections according to a gear of 10mV, and 10 sections with a total of 11 voltage points, namely test points, are drawn. The same process as the rough scan, the output current corresponding to these 11 voltage points is monitored, and the automatic test machine searches for the input voltage point corresponding to the output current of 10mA according to the test program. The automatic test machine returns a floating point number 1.22, and the feedback information is: the trigger point is found between the first point and the second point. The code is forced to convert to an integer, for example, after rounding to the nearest integer, it is point 1, corresponding to the input voltage of 4.7V, that is, the conduction voltage of this MOS tube M1 is 4.7V (in line with the accuracy requirement of 10mV error).

[0086] The discrete test duration of each discrete detection point including the segmentation point and the test point needs to be greater than or equal to 200 μS, and a discrete detection signal with a period of 500 μS can be set.

[0087] For the above Figure 6 In the case of synchronous detection of 10 chips in the corresponding example, using the test method in the embodiment of the present disclosure, a total of 11+11=22 discrete detection points need to be tested to determine the trigger point, and the required time is 500μS*22=11mS, that is, the time taken for parallel testing of 10 workstations is 11mS.

[0088] If the test method in the related art 1 is adopted, the number of discrete detection points to be tested is 1V / 10mV+1=101, and the time required is 500μS*101=50.5mS, that is, the time taken for parallel testing of 10 stations is 50.5mS.

[0089] If the testing method in the related technology 2 is adopted, the discrete detection points that need to be tested by the binary search method correspond to 101 elements in this embodiment, which is at most log2(101+1), that is, 7. The time required for automatic testing is 500μS*7=3.5mS. However, since 10 workstations cannot be tested in parallel using this method, the serial test takes 35mS.

[0090] In the embodiment of the present disclosure, when the segmentation point is roughly scanned, the floating point number fed back by the automatic test machine is usually a decimal, and the segment where the trigger point is located can be determined by rounding down. When the floating point number fed back by the automatic test machine is an integer, the segments on both sides of the segmentation point corresponding to the integer can be used as the target segments for fine scanning.

[0091] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

Claims

1. A method for finding a trigger point based on an automatic testing machine, characterized in that: The method comprises the following steps: Based on the value range of the working electrical signal of the chip to be tested, n+1 segmentation points are selected to divide the value range of the test electrical signal provided by the automatic test machine into n segments, and based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the segment where the trigger point is located is determined, wherein n is a positive integer and n≥2; Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the trigger point is determined based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located, wherein m is a positive integer and m≥2.

2. The method for finding a trigger point based on an automatic testing machine according to claim 1, characterized in that: The step of selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic test machine into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points comprises the following steps: Based on the value range of the working electrical signal of the chip to be tested, n+1 segmentation points are selected to divide the value range of the test electrical signal provided by the automatic tester into n uniform segments, wherein the increment of the test electrical signal corresponding to each segment is equal; The test electrical signals corresponding to the n+1 segmentation points are discretely provided to the chip under test in sequence, the segmentation points where the state of the chip under test changes are determined, and then the segment where the trigger point of the chip under test is located is confirmed.

3. The method for finding a trigger point based on an automatic testing machine according to claim 1 or 2, characterized in that: The step of selecting m+1 test points in the segment where the trigger point is located based on the test accuracy required by the chip to be tested, and determining the trigger point based on the test electrical signals corresponding to the m+1 test points and at least a part of the two segments corresponding to the segment where the trigger point is located comprises the following steps: Based on the test accuracy required by the chip to be tested, m+1 test points are selected in the segment where the trigger point is located, and the m+1 test points divide the test electrical signal corresponding to the segment where the trigger point is located into m uniform sections, wherein the increment of the test electrical signal corresponding to each section is equal, and the increment of the test electrical signal corresponding to each section is substantially equal to the test accuracy required by the chip to be tested; The test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence, the test points where the state of the chip under test changes are determined, and then the trigger point of the chip under test is confirmed.

4. The method for finding a trigger point based on an automatic testing machine according to claim 1 or 2, characterized in that: The step of discretely providing the test electrical signals corresponding to the n+1 segment points to the chip under test in sequence, determining the segment points where the state of the chip under test changes, and then confirming the segment where the trigger point of the chip under test is located comprises: The test electrical signals corresponding to the n+1 segmentation points are discretely provided to the chip to be tested in sequence until the test electrical signal corresponding to the i-th segmentation point is input to change the state of the chip to be tested, and the segment between the i-1-th segmentation point and the i-th segmentation point is determined as the segment where the trigger point of the chip to be tested is located, where i is a positive integer and n+1≥i≥2.

5. The method for finding a trigger point based on an automatic testing machine according to claim 3, characterized in that: The discretely providing the test electrical signals corresponding to the m+1 test points to the chip under test in sequence, determining the test point where the state of the chip under test changes, and then confirming the trigger point of the chip under test includes: The test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence until the test electrical signal corresponding to the j-th test point is input to change the state of the chip under test, and the test electrical signal corresponding to the j-th test point or the j-1-th test point is determined as the trigger point for the majority of the chips under test, where j is a positive integer and m+1≥j≥1.

6. The method for finding a trigger point based on an automatic testing machine according to claim 1 or 2, characterized in that: n and m satisfy the following formula: Wherein, T represents the increment of the value range of the working electrical signal of the chip to be tested, and Δ represents the test accuracy required by the chip to be tested.

7. The method for finding a trigger point based on an automatic testing machine according to claim 1 or 2, characterized in that: n and m are determined based on the principle that the sum of n+1 and m+1 should be as small as possible.

8. The method for finding a trigger point based on an automatic testing machine according to claim 1 or 2, characterized in that: Before selecting n+1 segmentation points based on the value range of the working electrical signal of the chip to be tested to divide the value range of the test electrical signal provided by the automatic tester into n segments, and determining the segment where the trigger point is located based on the test electrical signal corresponding to at least a part of the n+1 segmentation points, the method further includes the following steps: The plurality of chips to be tested are placed on a plurality of test stations of an automatic test machine respectively, and a plurality of analog test electrical signals are provided to the plurality of chips to be tested respectively.

9. The method for finding a trigger point based on an automatic testing machine according to claim 2, characterized in that: When the test electrical signals corresponding to the n+1 segment points are discretely provided to the chip to be tested in sequence, the discrete test duration of each segment point is greater than or equal to the response time of the chip to be tested.

10. The method for finding a trigger point based on an automatic testing machine according to claim 3, characterized in that: When the test electrical signals corresponding to the m+1 test points are discretely provided to the chip under test in sequence, the discrete test duration of each test point is greater than or equal to the response time of the chip under test.

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