Automatic chip testing method based on neural network algorithm

Abstract

The invention provides an automatic chip testing method based on a neural network algorithm, and relates to the technical field of integrated circuit testing, and the method mainly comprises the steps: taking a test item and a test condition of a chip as the input of a neural network, and taking a test resource and a test behavior of a chip test system needing to be called as the output of the neural network; packaging the neural network into a module which can be directly called by a chip test system; training a neural network by using the defined input and output; a chip needing to be tested formally is connected to the chip testing system, the chip testing system calls the trained neural network, corresponding testing resources and testing behaviors are called according to testing items and testing conditions needing to be conducted, and a formal testing result is generated. According to the invention, the neural network algorithm can be called on the basis of a traditional test system, and the intelligence of chip test is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a chip automatic testing method based on a neural network algorithm. Background Art

[0002] LSI test systems, such as Teradyne's UltraFlex test system and others, are the industry standard for cost-effective testing of a wide variety of microcontrollers, FPGAs, and digital audio and baseband devices.

[0003] Different test platforms use different programming languages, and there may be differences in the description of the same test method. The data processing development code on different platforms cannot be directly transplanted. For example, UltraFlex uses VB language, which has low data processing efficiency and is not suitable for processing large amounts of data. Especially for neural network algorithms that require a lot of floating-point operations, the efficiency of development directly on VB is very low. In addition, the test platform software development for the same category of devices based on UltraFlex requires engineers to intervene, even for minor parameter adjustments. For the same category of devices, after the hardware development is completed, the software development is related to the skill level of the development engineer, and the robustness and coverage of the test software cannot be guaranteed, making subsequent maintenance difficult. When maintaining the platform, the dynamic link library provides functions with various standard parameters, does not support variable parameter input, and the functions are relatively independent, which is not conducive to the debugging and use of the dynamic link library.

[0004] With the continuous development of artificial intelligence technology, neural networks have become a hot topic. For the field of integrated circuit testing, which has high repetitive operation frequency and basically the same test methods for the same category of products, artificial intelligence technology can greatly improve development efficiency and test efficiency. However, traditional test systems need to interact with hardware interfaces, and the programming environment they use often does not natively support the implementation of neural network algorithms, and cannot directly use neural networks to realize intelligent chip testing.

[0005] Some existing similar technologies, such as CN202311411750.3 "An AI chip test management system and method" and CN202110086583.4 "A test method, device, system, chip and electronic device", are mainly aimed at AI chip testing methods, rather than applying AI technology to the field of integrated circuit testing. At this stage, there is no case of directly applying neural network algorithms to traditional integrated circuit testing systems. Summary of the invention

[0006] Based on the above problems, the purpose of the present invention is to provide a chip automation testing method based on a neural network algorithm, which can call the neural network algorithm on a traditional testing system to realize the intelligent chip testing.

[0007] The technical solution adopted by the present invention to achieve its invention object is a chip automatic testing method based on a neural network algorithm, comprising the following steps:

[0008] S1. Parameterize the chip test requirements and the hardware interface of the chip test system, that is, use the chip test items and test conditions as the input of the neural network, and use the test resources and test behaviors of the chip test system to be called as the output of the neural network. The neural network is implemented using MATLAB.

[0009] S2. Encapsulating the neural network into a module that can be directly called by the chip testing system;

[0010] S3. The neural network is trained using the defined input and output. The specific training process is as follows: the chip participating in the training is connected to the chip test system, different test resources and test behaviors are called for various test items and test conditions, corresponding test results are generated and analyzed, and the result analysis information is fed back to the neural network for iterative training until the optimal test result is met and the neural network training is completed;

[0011] S4. Connect the chip to be formally tested to the chip testing system. The chip testing system calls the neural network trained in step S3, calls the corresponding test resources and test behaviors for the test items and test conditions to be performed, and generates formal test results.

[0012] Furthermore, the test items include at least open and short circuit test, leakage current, power supply current, functional test, and timing, and the test conditions include at least test method, applied current value, test pin name, test upper limit, and test lower limit.

[0013] Furthermore, the test resources at least include a pin parameter measurement unit PPMU and a high-density voltage source HDVS, and the test behavior at least includes adding current and measuring voltage, adding current and measuring current, adding voltage and measuring current, and adding voltage and measuring voltage.

[0014] Furthermore, the specific process of step S2 is: firstly encapsulate the neural network designed by MATLAB into a standard C interface, and then call it in the VB programming environment running the chip test system.

[0015] Furthermore, the content of the result analysis in step S3 at least includes upper and lower limits, optimal value determination and statistical values.

[0016] Furthermore, the upper and lower limit judgment conditions include that the upper limit exceeding the limit is judged as a failure FAIL, and the lower limit exceeding the limit is judged as a failure FAIL; the judgment conditions for the optimal value judgment include at least the best performance and the shortest time; the judgment conditions for the statistical value include at least that the smaller the root mean square value, the better, and the closer the distribution is to the 3σ distribution, the better.

[0017] The beneficial effects of the present invention are:

[0018] By adopting encapsulation methods, such as converting Matlab to C code and C code to VB, the neural network algorithm is implemented on the traditional integrated circuit test system, and then the neural network algorithm is called on the integrated circuit test system to realize automatic testing of the chip. This can save time for test development and maintenance on the traditional integrated circuit test system, avoid the problem of low efficiency of the VB language itself, and use Matlab algorithm to accelerate program execution, which greatly improves the intelligence level of chip testing and significantly improves test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A block diagram of a neural network implementation of an embodiment of the present invention;

[0020] Figure 2 Schematic diagram of a neural network training process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Example 1

[0023] Figures 1-2 A specific implementation of the chip automatic testing method based on the neural network algorithm of the present invention is shown, wherein the chip testing system adopts Teradyne's UltraFlex testing system;

[0024] The method comprises the following steps:

[0025] S1. Parameterize the test requirements of the chip and the hardware interface of the UltraFlex test system, that is, use the test items and test conditions of the chip as the input of the neural network, and use the test resources and test behaviors of the UltraFlex test system to be called as the output of the neural network. The neural network is implemented using MATLAB.

[0026] Test items and test conditions are used as inputs to the neural network. The key lies in the standardization of each test item and each test condition. The test requirements for chips can be broken down into specific test items, such as OS (open-short circuit test), II (leakage current), ICC (power supply current), Func (functional test), Timing, etc. The test items corresponding to a single chip category are basically fixed, so the test items and test conditions can be directly sent to the neural network as input conditions. For example, for the OS test item, its test conditions include test method, applied current value, test pin name, test upper limit, test lower limit, etc. These items can be listed as a test condition table, as shown in Table 1:

[0027] Table 1 Test conditions

[0028]

[0029]

[0030] The test resources at least include a pin parameter measurement unit PPMU and a high-density voltage source HDVS, and the test behaviors at least include adding current to measure voltage, adding current to measure current, adding voltage to measure current, and adding voltage to measure voltage. Test resources and test behaviors are the output of neural networks, and the key lies in the standardization of the description of each test resource and test behavior. For the hardware interface of the UltraFlex test system, it provides a very rich set of underlying options. Direct correspondence is obviously impossible, and a behavioral description is required. For example, when testing an OS, it is necessary to strip out the same properties and methods of the resources it uses, and use a template method to establish a test method library. When this part of the code needs to be generated, the code in the method library is used to describe the behavior of the test resources, as shown in Table 2:

[0031] Table 2 Behavior description table

[0032]

[0033] S2. Encapsulate the neural network into a module that can be directly called by the UltraFlex test system, so as to combine the convenience of MATLAB's neural network implementation and the highly flexible hardware testing capabilities of the UltraFlex system. The specific process is: first encapsulate the neural network designed by MATLAB into a standard C interface, that is, convert it into C code, and then call it in the VB programming environment where the UltraFlex test system runs. In this way, the neural network is embedded in the UltraFlex test system.

[0034] Steps S1 and S2 are as follows Figure 1 shown.

[0035] S3, using the defined input and output to train the neural network, the specific training process is: Figure 2 As shown, the chips participating in the training are connected to the UltraFlex test system, and different test resources and test behaviors are called for various test items and test conditions to generate corresponding test results and perform result analysis. The result analysis information is then fed back to the neural network for iterative training until the optimal test result is met and the neural network training is completed.

[0036] Result analysis is the key to normal training and iteration. Its content includes at least upper and lower limits, optimal value judgment and statistical value. The judgment conditions of the upper and lower limits include that the upper limit exceeds the limit and is judged as failure FAIL, and the lower limit exceeds the limit and is judged as failure FAIL. The judgment conditions of the optimal value judgment include at least the best performance and the shortest time. The judgment conditions of the statistical value include at least that the smaller the root mean square value, the better, and the closer the distribution is to the 3σ distribution, the better. The result analysis is shown in Table 3. By combining the upper and lower limits, optimal value judgment and statistical value data, data analysis is performed, and the analysis results are fed back to the neural network for training. For example, for the performance test of a chip, the results of different power-on and power-off sequences and unused test resources may be inconsistent. The neural network can automatically train and verify it to meet the optimal test results and test efficiency.

[0037] Table 3 Test result analysis coefficient table

[0038]

[0039] S4. Connect the chip to be formally tested to the UltraFlex test system. The UltraFlex test system calls the neural network trained in step S3, calls the corresponding test resources and test behaviors for the test items and test conditions to generate formal test results.

[0040] For example, if the chip needs to be tested on OS (open and short circuit test), the input items of the neural network are as follows: test item = OS test, test condition = test method, and the neural network calls the corresponding trained output items: test resource = PPMU, test behavior = add current and measure voltage, test resource = HDVS, test behavior = add voltage and measure current.

[0041] Then, the UltraFlex test system calls the neural network to perform specific tests on the chip under PPMU and HDVS resources and outputs the final test results.

Claims

1. A chip automation testing method based on a neural network algorithm, characterized in that: The steps include: S1. Parameterize the chip test requirements and the hardware interface of the chip test system, that is, use the chip test items and test conditions as the input of the neural network, and use the test resources and test behaviors of the chip test system to be called as the output of the neural network. The neural network is implemented using MATLAB. S2. Encapsulating the neural network into a module that can be directly called by the chip testing system; S3. The neural network is trained using the defined input and output. The specific training process is as follows: the chip participating in the training is connected to the chip test system, different test resources and test behaviors are called for various test items and test conditions, corresponding test results are generated and analyzed, and the result analysis information is fed back to the neural network for iterative training until the optimal test result is met and the neural network training is completed; S4. Connect the chip to be formally tested to the chip testing system. The chip testing system calls the neural network trained in step S3, calls the corresponding test resources and test behaviors for the test items and test conditions to be performed, and generates formal test results.

2. The chip automatic testing method based on neural network algorithm according to claim 1 is characterized in that: The test items include at least open and short circuit test, leakage current, power supply current, functional test, and timing, and the test conditions include at least test method, applied current value, test pin name, test upper limit, and test lower limit.

3. The chip automatic testing method based on neural network algorithm according to claim 1 is characterized in that: The test resources at least include a pin parameter measurement unit PPMU and a high-density voltage source HDVS, and the test behaviors at least include adding current to measure voltage, adding current to measure current, adding voltage to measure current, and adding voltage to measure voltage.

4. The chip automatic testing method based on neural network algorithm according to claim 1 is characterized in that: The specific process of step S2 is: first encapsulate the neural network designed by MATLAB into a standard C interface, and then call it in the VB programming environment running the chip test system.

5. The chip automatic testing method based on neural network algorithm according to claim 1 is characterized in that: The content of the result analysis in step S3 at least includes upper and lower limits, optimal value determination and statistical values.

6. The chip automatic testing method based on neural network algorithm according to claim 5 is characterized in that: The upper and lower limit judgment conditions include that the upper limit exceeding the limit is judged as failure FAIL, and the lower limit exceeding the limit is judged as failure FAIL; the judgment conditions for the optimal value judgment include at least the best performance and the shortest time; the judgment conditions for the statistical value include at least that the smaller the root mean square value, the better, and the closer the distribution is to the 3σ distribution, the better.

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