A readout electronics circuit system for a heavy ion beam telescope and its usage method

Abstract

The present invention relates to a readout electronics circuit system for a heavy ion beam telescope and a method of using the same. The system includes a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer. The front-end readout control module is used to receive the control signal from the data aggregation module and the clock and trigger signals provided by the trigger and clock module, and amplify and digitize the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope to obtain processed data frames. The data aggregation module is used to aggregate and process the data frames processed by several front-end readout control modules to determine the track of the particle. The trigger and clock module is used to generate multiple trigger signals and multiple clock signals. The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module. The present invention can be widely applied to the fields of high-energy physics experiments and nuclear detection technologies.

Description

Technical Field

[0001] The present invention relates to the field of high-energy physics experiments and nuclear detection technologies, and particularly to a readout electronics circuit system for a heavy ion beam telescope and a method for using the same. Background Art

[0002] The beam provided by a particle accelerator is a yardstick in the fields of particle physics and nuclear physics. During the development process of a detector, it is essential to use the beam to conduct principle verification, calibration, and optimization of the detector. To cooperate with the tasks of principle verification, calibration, and optimization of the developed detector on the beam, especially when testing parameters such as its track resolution and detection efficiency, a high-precision particle track detection system is generally required at the beam terminal to measure the track information of particles. This track detection system is generally referred to as a beam telescope. The silicon pixel detector has an extremely low material quantity, and the influence of particle scattering effects on position measurement is relatively small when applied to low-energy beam measurement. Therefore, the advantages of the silicon pixel detector, such as high position resolution, high integration, fast response time, low noise, and extremely low material quantity, give it natural and unique advantages in developing high-performance beam telescopes.

[0003] The prototype of the silicon pixel heavy ion beam telescope mainly consists of a detector module, a readout electronics module, a computer, a mechanical platform, etc. Among them, the detector module is composed of silicon pixel chips bonded to a PCB board by wire bonding to form a layer group. Several layer groups (such as 6) are respectively used to form two arms of the telescope, and the device under test is placed in the middle of the two arms. A trigger detector is placed on each side of the beam telescope for trigger readout; the readout electronics module mainly consists of a front-end readout control module for silicon pixel chips, a data aggregation module, and a trigger and clock module; the mechanical platform is used to complete the movement and adjustment between each layer group and the detector under test; the computer is used to run the upper computer control software. When the beam passes through the detector, the particle hit information provided by the silicon pixel chips forming the two arms and the detector under test will reconstruct the accurate track of the particle. Using the particle track information reconstructed by the beam telescope, performance indicators such as the track resolution and detection efficiency of the detector under test can be obtained.

[0004] However, there are still many challenges to overcome in successfully applying domestic silicon pixel chips to a heavy ion beam telescope. The most critical problems include: (1) Insufficient reliability of the electronics system: Traditional circuits are prone to single particle effects (such as single event upset (SEU), single event latch-up (SEL)) in a strong radiation environment; (2) Data transmission bottleneck: For the large number of pixels in the silicon pixel detector chip, the number of pixels per single chip exceeds 2×10 5, how to ensure reliable data transmission rate and improve the flexibility and scalability of the system; (3) Low efficiency of offline analysis: Traditional track reconstruction relies on GPU offline processing, with a delay of up to minutes, making it difficult to support real-time optimization of experiments. Summary of the Invention

[0005] In view of the above problems, the object of the present invention is to provide a readout electronics circuit system for a heavy ion beam telescope with high reliability, reliable data transmission, and high offline analysis efficiency, as well as a method for using the same.

[0006] To achieve the above object, the present invention adopts the following technical solutions: In the first aspect, a readout electronics circuit system for a heavy ion beam telescope is provided, including a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer;

[0007] The front-end readout control module is used to receive the control signal from the data aggregation module and the clock and trigger signals provided by the trigger and clock module, and is designed with an analog-digital hybrid architecture. It amplifies and digitizes the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope to obtain processed data frames; and provides a working power supply and a signal bias voltage to the corresponding silicon pixel chips, where each front-end readout control module corresponds to the signals of one or multiple silicon pixel chips;

[0008] The data aggregation module is used to aggregate and process the data frames processed by several front-end readout control modules; determine the track of particles based on the processed data frames; and send the control signal of the computer to the front-end readout control module;

[0009] The trigger and clock module is used to receive the hit signals of the trigger detector, perform coincidence and then fan out into multiple trigger signals, and provide them to the front-end readout control module, the data aggregation module, and the device under test respectively; and generate a global synchronous clock signal and fan out into multiple clock signals, and provide them to the front-end readout control module, the data aggregation module, and the device under test respectively;

[0010] The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module based on the control instructions of the host computer, and store the aggregated and processed data frames.

[0011] Further, the front-end readout control module includes a silicon pixel chip bonding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a current monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, a first FPGA chip, a first optical fiber circuit, and a multi-channel digital-to-analog converter;

[0012] The silicon pixel chip bonding board docking connector is used to receive the voltage pulse signals output by the corresponding silicon pixel chips and send them to the analog conditioning and single-ended to differential circuit; and to provide the working power supply and signal bias voltage to the corresponding silicon pixel chips.

[0013] The analog conditioning and single-ended to differential circuit is used to process the voltage pulse signals output by the silicon pixel chips to obtain 64-channel differential signals and send them to the two 32-channel analog-to-digital converters.

[0014] The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on the differential signals, obtain the digitized signals and send them to the first FPGA chip.

[0015] The current monitoring circuit is used to monitor the working current of the corresponding silicon pixel chips.

[0016] The first clock circuit is used to provide the system global clock signal during debugging.

[0017] The first power management circuit is used to send the working power supply of the corresponding silicon pixel chips to the silicon pixel chip bonding board docking connector based on the control of the first FPGA chip.

[0018] The first clock connector is used to receive the global clock signal of the trigger and clock module.

[0019] The first trigger connector is used to receive the trigger signal of the trigger and clock module.

[0020] The first FPGA chip is used to perform CRC check on the digitized signals and encapsulate them into data frames, and send them to the data aggregation module through the first optical fiber circuit; and based on the global clock signal and trigger signal, control the operation of the multi-channel digital-to-analog converter, the first power management circuit and the first optical fiber circuit.

[0021] The first optical fiber circuit is used to perform real-time data interaction with the data aggregation module.

[0022] The multi-channel digital-to-analog converter is used to provide the signal bias voltage required for the normal operation of the silicon pixel chips.

[0023] Further, the front-end readout control module further includes:

[0024] A temperature monitoring circuit, used to monitor the ambient temperature;

[0025] A humidity monitoring circuit, used to monitor the ambient humidity.

[0026] Further, the data aggregation module includes a peripheral interface circuit, a clock generator chip, a second FPGA chip, a DDR4 chip, a FLASH chip, and a second power management circuit. Among them, the peripheral interface includes a PCIe4.0×16 interface, 24 25 Gbps optical fiber interfaces, a second clock connector, and a second trigger connector;

[0027] The PCIe4.0×16 interface is used to receive the control signal of the computer and upload the aggregated and processed data frame to the computer for storage;

[0028] The 24 25 Gbps optical fiber interfaces are used to receive the processed data frames sent by the front-end readout control module and send the control signal of the computer to the front-end readout control module;

[0029] The second clock connector is used to receive the global clock signal of the trigger and clock module;

[0030] The second trigger connector is used to receive the trigger signal of the trigger and clock module;

[0031] The clock generator chip is used to generate the reference clocks required by the components of the data aggregation module;

[0032] The second FPGA chip is used to reconstruct and fit the particle track based on the processed data frame by using a neural network-based object detection algorithm to determine the track of the particle;

[0033] The DDR4 chip is used to cache and temporarily store the data of the front-end readout control module aggregated;

[0034] The FLASH chip is used to store the configuration for FPGA firmware update logic;

[0035] The second power management circuit is used to provide power supply for the components of the data aggregation module.

[0036] Further, the peripheral interface circuit further includes:

[0037] HP-FMC expansion interface, which is used to realize peripheral modular expansion;

[0038] The first JTAG debugging interface is used to perform online debugging on the second FPGA chip through JTAG.

[0039] Further, the geometric dimensions of the data aggregation module are determined according to the high-speed serial bus specification.

[0040] Further, the trigger and clock module includes a trigger module and a clock module. Among them, the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed discrimination circuit, a third FPGA chip, a second LEMO connector, and an FPGA peripheral circuit. The FPGA peripheral circuit includes a second clock circuit, a reset circuit, and a second JTAG debug interface;

[0041] Both of the two first LEMO connectors are used to receive the hit signals of the trigger detector;

[0042] Both of the two current-voltage conversion circuits are used to perform current-voltage conversion and amplification on the corresponding hit signals to obtain voltage signals;

[0043] The high-speed discrimination circuit is used to compare the voltage signals obtained by the current-voltage conversion circuit with the set threshold to generate digital trigger signals;

[0044] The third FPGA chip is used to perform coincidence and selection on the digital trigger signals to obtain effective trigger signals and fan them out into multiple LVTTL-level trigger signals;

[0045] The second LEMO connector is used to send multiple LVTTL-level trigger signals to the front-end readout control module, the data aggregation module, and the device under test through a single-ended coaxial cable;

[0046] The second clock circuit is used to provide a global clock signal for the FPGA system;

[0047] The reset circuit is used to provide a reset signal for the FPGA system.

[0048] Further, the FPGA peripheral circuit further includes a second JTAG debug interface, which is used to perform on-line debugging on the third FPGA chip through JTAG to track the processor core state in real time.

[0049] Further, the clock module includes a temperature-compensated oscillator, a clock fan-out chip, and a third LEMO connector;

[0050] The temperature-compensated oscillator is used to generate a global clock signal;

[0051] The clock fan-out chip is used to fan out the global clock signal generated by the temperature-compensated oscillator into multiple low-voltage differential signal level clock signals;

[0052] The third LEMO connector is used to send multiple low-voltage differential signal level clock signals to the front-end readout control module, the data aggregation module, and the device under test through a differential coaxial cable.

[0053] On the other hand, a method of using a readout electronics circuit system based on a heavy ion beam telescope is provided, including:

[0054] The trigger and clock module receives the hit signals of the trigger detector, performs coincidence, and then fans out into multiple trigger signals, which are respectively provided to the front-end readout control module, the data aggregation module, and the device under test;

[0055] The trigger and clock module generates a global synchronization clock signal and fans it out into multiple clock signals, which are respectively provided to the front-end readout control module, the data aggregation module, and the device under test;

[0056] The front-end readout control module receives the control signals of the data aggregation module and the clock and trigger signals provided by the trigger and clock module. It is designed with an analog-digital hybrid architecture to amplify and digitize the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope, and obtains the processed data frames;

[0057] The front-end readout control module provides the working power supply and signal bias voltage to the corresponding silicon pixel chips;

[0058] The data aggregation module aggregates and processes the data frames processed by several front-end readout control modules, determines the track of the particle based on the processed data frames, and uploads the aggregated and processed data frames to the computer for storage.

[0059] Due to the above technical solutions adopted by the present invention, it has the following advantages:

[0060] 1. The present invention can reduce the cost by 80%, and the supply chain is independently controllable.

[0061] 2. The track resolution of the present invention reaches 5 μm, the real-time processing ability is increased several times, and the performance is leading.

[0062] 3. The present invention can adapt to extreme radiation and temperature environments and has high reliability.

[0063] 4. The present invention can support ultra-large-scale experimental devices, lay a foundation for large-scale particle experiments, and has flexible expansion.

[0064] 5. The present invention can efficiently complete the particle track reconstruction task. The front-end readout control module is responsible for signal acquisition and processing, the data aggregation module realizes high-speed data transmission and online track reconstruction, and the trigger and clock module ensures the synchronization and stability of the system. Each module works together to accurately measure the particle track and evaluate the performance of the detector, providing reliable technical support for particle physics research.

[0065] 6. In the prior art, the reconstruction and fitting of particle tracks are carried out by using algorithms to process offline data, while the present application processes data online, with a fast processing speed and the ability to greatly compress data.

[0066] 7. The present invention can be applied not only to heavy ion beam telescopes, but also to beam telescopes of other ions (such as protons), and can also be applied to the readout electronics system of large-scale physical experiment devices.

[0067] In summary, the present invention can be widely used for real-time monitoring of beam tracks in particle accelerators, detector performance calibration, and experimental data optimization, and is particularly suitable for precision measurements in high-radiation and high-particle-flux environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0069] Figure 1 is a schematic structural diagram of a readout electronics circuit system of a heavy ion beam telescope provided by an embodiment of the present invention;

[0070] Figure 2 is a schematic structural diagram of a front-end readout control module provided by an embodiment of the present invention;

[0071] Figure 3 is a schematic structural diagram of a data aggregation module provided by an embodiment of the present invention;

[0072] Figure 4 is a schematic structural diagram of a trigger and clock module provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0073] Hereinafter, the exemplary embodiments of the present invention will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0074] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprising", "including", "containing", and "having" are inclusive and thus specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an execution order is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0075] Although the terms first, second, third, etc. may be used herein to describe multiple elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first", "second", and other numerical terms when used herein do not imply an order or sequence. Thus, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the example embodiments.

[0076] An embodiment of the present invention provides a readout electronics circuit system for a heavy ion beam telescope, including a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer. The front-end readout control module is used to receive the control signal from the data aggregation module and the clock and trigger signals provided by the trigger and clock module. Designed with an analog-digital hybrid architecture, it amplifies and digitizes the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope to obtain processed data frames. And it provides the working power supply and signal bias voltage to the corresponding silicon pixel chips, where each front-end readout control module corresponds to the signals of one or multiple silicon pixel chips. The data aggregation module is used to aggregate and process the data frames processed by several front-end readout control modules. Based on the processed data frames, it reconstructs and fits the particle tracks to determine the particle tracks. And it sends the control signal of the computer to the front-end readout control module. The trigger and clock module is used to receive the hit signals of the trigger detector, perform coincidence and then fan out into multiple trigger signals, and respectively provide them to the front-end readout control module, the data aggregation module, and the device under test. And it generates a global synchronous clock signal and fans it out into multiple clock signals, and respectively provides them to the front-end readout control module, the data aggregation module, and the device under test. The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module based on the control instructions of the host computer. The present invention can overcome the problems of the traditional system in terms of radiation environment stability, data transmission efficiency, and real-time processing ability. The present invention is mainly applied to the heavy ion beam telescope in the particle accelerator, and can accurately measure the track information of particles to realize the test, calibration, and optimization of the detector. By using domestic silicon pixel detector chips, the present invention can provide a high-performance detection method that is independently controllable. The present invention can not only meet the current needs of domestic particle accelerators, but also has a wide application prospect and can support future higher-intensity particle experimental devices. In addition, the present invention uses a neural network optimization algorithm to perform online particle track reconstruction, greatly improving the speed and accuracy of particle track reconstruction, effectively solving the challenges brought by the huge amount of data, and can be widely applied to particle accelerator devices at home and abroad, providing an efficient test means for particle physics research.

[0077] Embodiment 1

[0078] As Figure 1 shown, this embodiment provides a readout electronics circuit system for a heavy ion beam telescope, including a front-end readout control module 1, a data aggregation module 2, a trigger and clock module 3, and a computer 4.

[0079] The front-end readout control module 1 is used to receive the control signals from the data aggregation module 2 and the clock and trigger signals provided by the trigger and clock module 3. It is designed with a mixed analog-digital architecture to amplify and digitize the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope, obtaining processed data frames; and to provide working power supplies and signal bias voltages, etc., to the corresponding silicon pixel chips. Among them, each front-end readout control module 1 corresponds to the signals of one silicon pixel chip or multiple silicon pixel chips.

[0080] The data aggregation module 2 is used to aggregate and process the data frames processed by several front-end readout control modules 1; based on the processed data frames, reconstruct and fit the particle tracks to determine the particle tracks; and send the control signals of the computer 4 to the front-end readout control module 1.

[0081] The trigger and clock module 3 is used to receive the hit signals of the trigger detectors, perform coincidence and then fan out into multiple trigger signals, and provide them to the front-end readout control module 1, the data aggregation module 2, and the device under test respectively; and generate a global synchronous clock signal and fan out into multiple clock signals, and provide them to the front-end readout control module 1, the data aggregation module 2, and the device under test respectively, so as to achieve clock synchronization of the entire system.

[0082] The computer 4 is used to control the front-end readout control module 1, the data aggregation module 2, and the trigger and clock module 3 based on the control instructions of the host computer, and store the data frames aggregated and processed by the data aggregation module 2.

[0083] In a preferred embodiment, the design of the front-end readout control module 1 of the present invention needs to meet the following main requirements: 1) strictly limit the use of resources such as power consumption, volume, and the number of leads; 2) be able to work stably in a radiation environment. For the above two requirements, as Figure 2 shown, the front-end readout control module 1 includes a silicon pixel chip bonding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a current monitoring circuit, a temperature monitoring circuit, a humidity monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, a first FPGA chip, a first optical fiber circuit, and a multi-channel digital-to-analog converter.

[0084] The silicon pixel chip bonding board docking connector is used to receive the voltage pulse signals output by the corresponding silicon pixel chips and send them to the analog conditioning and single-ended to differential circuit; and to provide working power supplies and signal bias voltages, etc., to the corresponding silicon pixel chips.

[0085] The analog conditioning and single-ended to differential circuit is used to perform single-ended to differential conversion, amplification, and bias adjustment, etc., on the voltage pulse signals output by the silicon pixel chips, obtaining 64-channel differential signals and sending them to two 32-channel analog-to-digital converters.

[0086] The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on differential signals, obtain the digitized signals and send them to the first FPGA chip.

[0087] The current monitoring circuit is used to monitor the working current of the corresponding silicon pixel chip.

[0088] The temperature monitoring circuit is used to monitor the ambient temperature.

[0089] The humidity monitoring circuit is used to monitor the ambient humidity.

[0090] The first clock circuit is used to provide the system global clock signal during debugging.

[0091] The first power management circuit is used to send the working power supply of the corresponding silicon pixel chip to the silicon pixel chip bonding board docking connector based on the control of the first FPGA chip.

[0092] The first clock connector is used to receive the global clock signal of the trigger and clock module 3.

[0093] The first trigger connector is used to receive the trigger signal of the trigger and clock module 3.

[0094] The first FPGA chip is used to perform CRC check (Cyclic Redundancy Check) on the digitized signals and encapsulate them into 512-bit data frames, and send them to the data aggregation module 2 through the first optical fiber circuit; and based on the global clock signal and the trigger signal, control the operation of the multi-channel digital-to-analog converter, the first power management circuit and the first optical fiber circuit.

[0095] The first optical fiber circuit is used to perform real-time data interaction with the data aggregation module 2, including the data frames encapsulated by the upstream FPGA and the control commands downlink through the data aggregation module 2.

[0096] The multi-channel digital-to-analog converter is used to provide the signal bias voltage required for the normal operation of the silicon pixel chip.

[0097] Specifically, the first FPGA chip can adopt the model of MICROCHIP M2S090T FPGA; the 32-channel analog-to-digital converter can adopt the model of ADS52J90ZZE, with a dynamic range of 84 dB; the analog conditioning and single-ended to differential circuit can adopt the model of AD8138, with a bandwidth of 200 MHz; the DC-DC in the first power management circuit can adopt LTM4644, with high integration and high efficiency, and the efficiency can reach more than 95%; the LDO in the first power management circuit can adopt the model of LT3045, with a ripple <0.5 mV; the current monitoring circuit can adopt an accuracy of ±0.5 mA; the temperature monitoring circuit and the humidity monitoring circuit can adopt an accuracy of ±0.2°C.

[0098] Specifically, the first FPGA chip has radiation-resistant design: triple modular redundancy design for key FPGA modules and regular reloading of configurations; current-limiting resistors are added to the power inputs of all integrated circuit chips to suppress SEL and protect the chips from damage; a π-type filter circuit (cutoff frequency 10 kHz) is embedded in the power network, and the radiation noise suppression ratio is > 40 dB.

[0099] In a preferred embodiment, the data aggregation module 2 serves as a connection link between the front-end readout control module 1 and the computer 4, enabling simultaneous communication with multiple (e.g., 6) front-end readout control modules 1. The data aggregation module 2 mainly completes high-speed caching of events, coincidence selection, online track reconstruction, event packaging, and interaction with the computer 4, such as Figure 3 As shown, the data aggregation module 2 includes a peripheral interface circuit, a clock generator chip, a second FPGA chip, a DDR4 chip, a FLASH chip, and a second power management circuit. Among them, the peripheral interface includes a PCIe4.0×16 interface, 24 25 Gbps optical fiber interfaces, a second clock connector, a second trigger connector, an HP-FMC expansion interface, and a first JTAG debugging interface.

[0100] The PCIe4.0×16 interface is used to receive the control signals from the computer 4 and upload the aggregated and processed data frames to the computer 4 for storage.

[0101] The 24 25 Gbps optical fiber interfaces are used to receive the processed data frames sent by the front-end readout control module 1; and send the control signals of the computer 4 to the front-end readout control module 1.

[0102] The second clock connector is used to receive the global clock signal from the trigger and clock module 3.

[0103] The second trigger connector is used to receive the trigger signal from the trigger and clock module 3.

[0104] The clock generator chip is used to generate the reference clocks required by the components of the data aggregation module 2.

[0105] The second FPGA chip is used to reconstruct and fit the particle tracks based on the processed data frames using a neural network-based target detection algorithm to determine the particle tracks. It should be noted that the algorithm for determining the particle tracks based on the neural network-based target detection algorithm is a publicly disclosed algorithm in the prior art, and the specific process will not be elaborated here.

[0106] The DDR4 chip is used to cache and temporarily store the data of the aggregated front-end readout control module 1.

[0107] The FLASH chip is used to store the configuration for FPGA firmware update logic.

[0108] The second power management circuit is used to provide a stable and isolated power supply for each component of the data aggregation module 2.

[0109] The HP-FMC expansion interface is used to achieve modular expansion of high-speed peripherals.

[0110] The first JTAG debugging interface is used to perform on-line debugging of the second FPGA chip through JTAG and track the status of the processor core in real time.

[0111] Specifically, the geometric dimensions of the data aggregation module 2 are designed according to the high-speed serial bus (PCIe) specification, and it can be directly installed on the PCIe slot of the computer 4 for use, and multiple data aggregation modules 2 are allowed to be installed on adjacent PCIe slots.

[0112] Specifically, the second FPGA chip can adopt an FPGA chip of the Xilinx UltraScale+ series; the DDR4 chip can adopt a DDR4 chip with a capacity of 8 GB, and the number is eight; the FLASH chip can adopt a 512 Mbit FLASH chip.

[0113] Specifically, the total capacity of the eight DDR4 chips is 64 GB, and the maximum working data rate is 3200 Mbps.

[0114] In a preferred embodiment, as Figure 4 shown, the trigger and clock module 3 includes a trigger module and a clock module. Among them, the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed discrimination circuit, a third FPGA chip, a second LEMO connector, and an FPGA peripheral circuit. The clock module includes a temperature-compensated oscillator, a clock fan-out chip, and a third LEMO connector. The FPGA peripheral circuit includes a second clock circuit, a reset circuit, and a second JTAG debugging interface.

[0115] Both of the two first LEMO connectors are used to receive the hit signals of the trigger detector.

[0116] Both of the two current-voltage conversion circuits are used to perform current-voltage conversion and amplification on the corresponding hit signals to obtain voltage signals.

[0117] The high-speed discrimination circuit is used to compare the voltage signals obtained by the current-voltage conversion circuit with the set threshold value to generate a digital trigger signal.

[0118] The third FPGA chip is used to perform coincidence and selection on the digital trigger signals to obtain effective trigger signals and fan them out into multiple LVTTL-level trigger signals.

[0119] The second LEMO connector is used to send multiple LVTTL-level trigger signals to the front-end readout control module 1, the data aggregation module 2, and the device under test through a single-ended coaxial cable.

[0120] The temperature-compensated oscillator is used to generate a high-precision and low-jitter global clock signal.

[0121] The clock fan-out chip is used to fan out the global clock signal generated by the temperature-compensated oscillator into multiple low-voltage differential signal (LVDS) level clock signals.

[0122] The third LEMO connector is used to send multiple low-voltage differential signal (LVDS) level clock signals to the front-end readout control module 1, the data aggregation module 2, and the device under test through a differential coaxial cable.

[0123] The second clock circuit is used to provide a global clock signal for the FPGA system

[0124] The reset circuit is used to provide a reset signal for the FPGA system.

[0125] The second JTAG debug interface is used to perform on-line debugging on the third FPGA chip through JTAG to track the processor core status in real time.

[0126] Specifically, the temperature-compensated oscillator can use an oscillator with the model number OH300-50503CV; the clock fan-out chip can use a clock fan-out chip with the model number 8T39S11ANLGI.

[0127] Embodiment 2

[0128] This embodiment provides a method for using a readout electronics circuit system of a heavy ion beam telescope, including the following steps:

[0129] 1) The trigger and clock module 3 receives the hit signal of the trigger detector, performs coincidence, and then fans out into multiple trigger signals, which are respectively provided to the front-end readout control module 1, the data aggregation module 2, and the device under test.

[0130] 2) The trigger and clock module 3 generates a global synchronous clock signal and fans it out into multiple clock signals, which are respectively provided to the front-end readout control module 1, the data aggregation module 2, and the device under test to achieve clock synchronization of the entire system.

[0131] 3) The data aggregation module 2 sends the control signal of the computer 4 to the front-end readout control module 1.

[0132] 4) The front-end readout control module 1 receives the control signals from the data aggregation module 2 and the clock and trigger signals provided by the trigger and clock module 3. Designed with an analog-digital hybrid architecture, it amplifies and digitizes the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope to obtain processed data frames.

[0133] 5) The front-end readout control module 1 provides the working power supply, signal bias voltage, etc. to the corresponding silicon pixel chips.

[0134] 6) The data aggregation module 2 aggregates and processes the data frames processed by several front-end readout control modules 1, determines the track of the particle based on the processed data frames, and uploads the aggregated and processed data frames to the computer 4 for storage.

[0135] The above embodiments are only used to illustrate the present invention. The structures, connection methods, manufacturing processes, etc. of each component can all be changed. Any equivalent transformation and improvement made on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims

1. A readout electronics circuit system for a heavy ion beam telescope, characterized in that, It includes a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer; The front-end readout control module is used to receive the control signal from the data aggregation module and the clock and trigger signals provided by the trigger and clock module. It is designed with an analog-digital hybrid architecture to amplify and digitize the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope, obtaining processed data frames; and to provide working power supply and signal bias voltage to the corresponding silicon pixel chips. Among them, each front-end readout control module corresponds to the signals of one silicon pixel chip or multiple silicon pixel chips; The data aggregation module is used to aggregate and process the data frames processed by several front-end readout control modules; to determine the track of particles based on the processed data frames; and to send the control signal of the computer to the front-end readout control module; The trigger and clock module is used to receive the hit signals of the trigger detector, perform coincidence and then fan out into multiple trigger signals, and provide them to the front-end readout control module, the data aggregation module, and the device under test respectively; and to generate a global synchronous clock signal and fan out into multiple clock signals, and provide them to the front-end readout control module, the data aggregation module, and the device under test respectively; The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module based on the control instructions of the host computer, and to store the aggregated and processed data frames; The front-end readout control module includes a silicon pixel chip bonding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a first FPGA chip with radiation-resistant design; The silicon pixel chip bonding board docking connector is used to receive the voltage pulse signals output by the corresponding silicon pixel chips and send them to the analog conditioning and single-ended to differential circuit; and to provide working power supply and signal bias voltage to the corresponding silicon pixel chips; The analog conditioning and single-ended to differential circuit is used to process the voltage pulse signals output by the silicon pixel chips, obtaining 64-channel differential signals and sending them to the two 32-channel analog-to-digital converters; The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on the differential signals, obtaining digitized signals and sending them to the first FPGA chip; The first FPGA chip is used to perform CRC check on the digitized signals and encapsulate them into data frames, sending them to the data aggregation module; and to control the operation of the multi-channel digital-to-analog converter based on the global clock signal and the trigger signal; The multi-channel digital-to-analog converter is used to provide the signal bias voltage required for the normal operation of the silicon pixel chips; The data aggregation module includes a peripheral interface circuit, a second FPGA chip, and a DDR4 chip, where the peripheral interface includes 24 25 Gbps optical fiber interfaces; The 24 25 Gbps optical fiber interfaces are used to receive the processed data frames sent by the front-end readout control module; and to send the control signal of the computer to the front-end readout control module; The second FPGA chip is used to reconstruct and fit the particle track based on the processed data frame by using a neural network-based object detection algorithm to determine the particle track; The DDR4 chip is used to cache and temporarily store the data of the summarized front-end readout control module.

2. The readout electronics circuit system of a heavy ion beam telescope according to claim 1, characterized in that The front-end readout control module further includes a current monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, and a first optical fiber circuit; The current monitoring circuit is used to monitor the operating current of the corresponding silicon pixel chip; The first clock circuit is used to provide a system global clock signal during debugging; The first power management circuit is used to send the operating power of the corresponding silicon pixel chip to the silicon pixel chip bonding board docking connector based on the control of the first FPGA chip; The first clock connector is used to receive the global clock signal of the trigger and clock module; The first trigger connector is used to receive the trigger signal of the trigger and clock module; The first optical fiber circuit is used to perform real-time data interaction with the data summarization module The first FPGA chip is further used to control the operation of the first power management circuit and the first optical fiber circuit based on the global clock signal and the trigger signal.

3. The readout electronics circuit system of a heavy ion beam telescope according to claim 2, characterized in that, The front-end readout control module further includes: A temperature monitoring circuit for monitoring the ambient temperature; A humidity monitoring circuit for monitoring the ambient humidity.

4. The readout electronics circuit system of a heavy ion beam telescope according to claim 1, characterized in that, The data summarization module further includes a clock generator chip, a FLASH chip, and a second power management circuit, and the peripheral interface further includes a PCIe4.0×16 interface, a second clock connector, and a second trigger connector; The PCIe4.0×16 interface is used to receive the control signal of the computer and upload the summarized and processed data frame to the computer for storage; The second clock connector is used to receive the global clock signal of the trigger and clock module; The second trigger connector is used to receive the trigger signal of the trigger and clock module; The clock generator chip is used to generate the reference clock required by each component of the data summarization module; The FLASH chip is used to store the configuration for FPGA firmware update logic; The second power management circuit is used to provide power supply for each component of the data summarization module.

5. The readout electronics circuit system of a heavy ion beam telescope according to claim 4, characterized in that The peripheral interface circuit further includes: An HP-FMC expansion interface for realizing peripheral modular expansion; A first JTAG debugging interface for online debugging of the second FPGA chip through JTAG.

6. The readout electronics circuit system of a heavy ion beam telescope according to claim 1, characterized in that, The geometric size of the data summarization module is determined according to the high-speed serial bus specification.

7. The readout electronics circuit system of a heavy ion beam telescope according to claim 1, characterized in that, The trigger and clock module includes a trigger module and a clock module. Among them, the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed discrimination circuit, a third FPGA chip, a second LEMO connector, and an FPGA peripheral circuit. The FPGA peripheral circuit includes a second clock circuit and a reset circuit; Both of the two first LEMO connectors are used to receive the hit signals of the trigger detector; Both of the two current-voltage conversion circuits are used to perform current-voltage conversion and amplification on the corresponding hit signals to obtain voltage signals; The high-speed discrimination circuit is used to compare the voltage signals obtained by the current-voltage conversion circuit with a set threshold to generate digital trigger signals; The third FPGA chip is used to perform coincidence and selection on the digital trigger signals to obtain effective trigger signals and fan them out into multiple LVTTL-level trigger signals; The second LEMO connector is used to send multiple LVTTL-level trigger signals to the front-end readout control module, data aggregation module, and device under test through a single-ended coaxial cable; The second clock circuit is used to provide a global clock signal for the FPGA system; The reset circuit is used to provide a reset signal for the FPGA system.

8. The readout electronics circuit system of a heavy ion beam telescope according to claim 7, characterized in that, The FPGA peripheral circuit further includes a second JTAG debugging interface, which is used to perform on-line debugging on the third FPGA chip through JTAG to track the processor core status in real time.

9. The readout electronics circuit system of a heavy ion beam telescope according to claim 7, characterized in that The clock module includes a temperature-compensated oscillator, a clock fan-out chip, and a third LEMO connector; The temperature-compensated oscillator is used to generate a global clock signal; The clock fan-out chip is used to fan out the global clock signal generated by the temperature-compensated oscillator into multiple low-voltage differential signal-level clock signals; The third LEMO connector is used to send multiple low-voltage differential signal-level clock signals to the front-end readout control module, data aggregation module, and device under test through a differential coaxial cable.

10. A method for using the readout electronics circuit system of a heavy ion beam telescope according to any one of claims 1 to 9, characterized in that, Including: The trigger and clock module receives the hit signals of the trigger detector, performs coincidence, and then fans out into multiple trigger signals, and provides them to the front-end readout control module, data aggregation module, and device under test respectively; The trigger and clock module generates a global synchronous clock signal and fans it out into multiple clock signals, and provides them to the front-end readout control module, data aggregation module, and device under test respectively; The data aggregation module sends the control signals of the computer to the front-end readout control module; The front-end readout control module receives the control signals of the data aggregation module and the clock and trigger signals provided by the trigger and clock module, and is designed with an analog-digital hybrid architecture to amplify and digitize the voltage pulse signals output by the corresponding silicon pixel chips in the heavy ion beam telescope to obtain processed data frames; The front-end readout control module provides a working power supply and a signal bias voltage for the corresponding silicon pixel chips; The data aggregation module aggregates and processes the data frames processed by several front-end readout control modules, determines the track of the particle based on the processed data frames, and uploads the aggregated and processed data frames to the computer for storage.

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