Mask pattern processing method, device, equipment, medium and product

Abstract

The application discloses a mask plate graph processing method, device, equipment, medium and product, and relates to the technical field of semiconductor integrated circuits. The mask plate graph processing method comprises the following steps: performing photolithography rule checking on a target mask plate graph to obtain target mask plate graph feature information; processing the target mask plate graph feature information by using a defect correction model to obtain a target defect correction strategy of the target mask plate graph, wherein the defect correction model is a model obtained by fine-tuning a large model according to historical mask plate graph feature information and corresponding historical defect correction strategies; and performing defect correction on the target mask plate graph based on the target defect correction strategy to obtain a target mask plate graph after defect correction.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a mask layout processing method and device, equipment, medium and product. BACKGROUND

[0002] At present, before the actual manufacture of a chip, a layout design and a mask are manufactured. Before the mask is delivered to a mask manufacturer, a simulation model is used to detect the mask, that is, a designed mask is simulated to obtain a profile after exposure, and then a lithography rule check (LRC) is used to obtain defects existing in the mask. In the case where defects are detected in the mask, correction of the defects is a crucial link.

[0003] In the existing method, after the defects of the mask are obtained through the LRC detection, a skilled optical proximity correction (OPC) engineer manually adjusts the graphic parameters around the defects in the mask to make up for the correction.

[0004] However, in the existing method, experienced engineers are relied on to correct the defects, which cannot directly give an accurate correction scheme, resulting in low efficiency and poor accuracy of defect correction. SUMMARY

[0005] The embodiments of the present application provide a mask layout processing method, device, equipment, medium and product, which can improve the efficiency and accuracy of defect correction.

[0006] In an aspect of the embodiments of the present application, a mask layout processing method is provided, comprising:

[0007] Performing lithography rule check on a target mask layout to obtain target layout feature information of the target mask layout, the layout feature information comprising layout defect information and surrounding environment information of the layout defect;

[0008] Processing the target layout feature information through a defect correction model to obtain a target defect correction strategy of the target mask layout, the defect correction model being a model obtained by fine-tuning a large model according to historical layout feature information and a corresponding historical defect correction strategy; and performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction.

[0009] In an aspect of the embodiments of the present application, a mask layout processing device is provided, comprising:

[0010] The layout inspection module is configured to perform photolithography rule inspection on the target mask layout to obtain target layout feature information of the target mask layout, and the layout feature information comprises layout defect information and surrounding environment information of the layout defect.

[0011] The policy determination module is configured to process the target layout feature information by using a defect correction model to obtain a target defect correction policy of the target mask layout, and the defect correction model is a model obtained by fine-tuning a large model according to historical layout feature information and a corresponding historical defect correction policy.

[0012] The layout correction module is configured to perform defect correction on the target mask layout based on the target defect correction policy to obtain a target mask layout after defect correction.

[0013] In an aspect of an embodiment of the present application, an electronic device is provided, which comprises a memory and a program or instructions stored in the memory and executable on a processor, and the program or instructions are executed by the processor to implement the mask layout processing method provided in any aspect of the above embodiments of the present application.

[0014] In an aspect of an embodiment of the present application, a readable storage medium is provided, and the readable storage medium stores a program or instructions, and the program or instructions are executed by a processor to implement the mask layout processing method provided in any aspect of the above embodiments of the present application.

[0015] In an aspect of an embodiment of the present application, a computer program product is provided, and instructions in the computer program product are executed by a processor of an electronic device to enable the electronic device to perform the mask layout processing method provided in any aspect of the above embodiments of the present application.

[0016] In the mask layout processing method provided in the embodiments of the present application, the defect correction model is obtained by fine-tuning a large model according to historical layout feature information and a corresponding historical defect correction policy. After performing photolithography rule inspection on the target mask layout to obtain target layout feature information of the target mask layout, the target defect correction policy of the target mask layout can be obtained by inputting the target layout feature information into the defect correction model, and the defect correction of the target mask layout is completed according to the target defect correction policy. Thus, the defect correction model can be used to directly determine the defect correction policy corresponding to various layout defects, and the defect correction of the target mask layout can be automatically completed. Therefore, the defect correction does not need to rely on experienced engineers, and the efficiency and accuracy of the defect correction can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. Those drawings can help the ordinary skilled in the art to obtain other drawings without any creative effort.

[0018] Figure 1 is a flow diagram of a mask pattern processing method provided by an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a mask pattern in an ideal case provided by an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a bridge defect type mask pattern provided by an embodiment of the present application;

[0021] Figure 4 is a structural schematic diagram of a mask pattern processing device provided by an embodiment of the present application;

[0022] Figure 5 is a structural schematic diagram of a mask pattern processing device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0024] It should be noted that, in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be noted that the acquisition, storage, use, processing, etc. of data in the technical solutions of the present application comply with relevant provisions of national laws and regulations.

[0026] It should be noted that in the embodiments of the present application, some industry existing solutions of software, components, models, etc. may be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility in the implementation of the technical solutions of the present application, but it does not mean that the applicant has or will necessarily use the solutions.

[0027] In the prior art, after the defects of the mask are obtained by LRC detection, the pattern parameters around the defects in the mask are generally manually adjusted by experienced OPC engineers for compensation and correction. However, in the prior art, experienced engineers are relied on to correct defects, which cannot directly give an accurate correction scheme, resulting in low efficiency and poor accuracy of defect correction.

[0028] The purpose of the present application is to provide a mask pattern processing method, device, equipment, medium and product. In the mask pattern processing method provided in the embodiments of the present application, the historical pattern feature information and the corresponding historical defect correction strategy are used to fine-tune the large model to obtain a defect correction model. After performing lithography rule checking on the target mask pattern to obtain target pattern feature information of the target mask pattern. Only need to input the target pattern feature information into the defect correction model, can obtain the target defect correction strategy of the target mask pattern, so as to complete the defect correction of the target mask pattern according to the target defect correction strategy. In this way, the embodiments of the present application can directly determine the defect correction strategy corresponding to various pattern defects through the defect correction model, thereby automatically completing the defect correction of the target mask pattern. Without relying on experienced engineers to correct defects, the efficiency and accuracy of defect correction can be improved.

[0029] The specific embodiments of the mask pattern processing method, device, equipment, medium and product provided in the embodiments of the present application will be introduced below. First, the mask pattern processing method will be introduced. Figure 1 A flowchart of a mask pattern processing method is provided, which can be applied to a server. The mask pattern processing method can include the following S101-S103.

[0030] S101, performing lithography rule checking on a target mask pattern to obtain target pattern feature information of the target mask pattern, the pattern feature information including pattern defect information and surrounding environment information of the pattern defect.

[0031] In the present embodiment, the pattern feature information includes the pattern defect information and the surrounding environment information of the pattern defect, and the target pattern feature information includes the pattern defect information of the target mask pattern and the surrounding environment information of the pattern defect of the target mask pattern.

[0032] The layout defect information of the target mask layout is used to represent mask pattern defects existing in the target mask layout. For example, the mask pattern defects can be at least one of a bridge defect type defect pattern, a necking defect type defect pattern, and a sub-resolution assist feature defect type defect pattern.

[0033] The surrounding environment information of the layout defect can include the shape and coordinates of the patterns around the defect coordinates, and the distance between these patterns and the distance from these patterns to the defect. By considering the surrounding environment information of the defect position, other defects are avoided in the surrounding area after the defect is corrected. Photolithography rule checking refers to obtaining the manufacturability problems that the design of the mask layout may face in advance through a photolithography imaging model before the photolithography process is implemented, to ensure that the design of the mask layout meets the requirements of the photolithography process, thereby avoiding manufacturing failures caused by improper design in the manufacturing process. For example, photolithography rule checking can include critical dimension variation checking, layout defect verification, line end variation checking, via coverage checking, assist feature imaging checking, and process window checking.

[0034] As an example, the server performs photolithography rule checking on the target mask layout through a photolithography imaging simulation software, thereby obtaining target layout feature information of the target mask layout. Specifically, the photolithography imaging simulation software uses an optical imaging model and a corresponding process window to quickly and accurately detect rule hotspots on the full-chip mask layout. By simulating the influence of various factors (such as light source, mask, photoresist, etc.) on layout imaging during the photolithography process, layout errors that can occur can be predicted and discovered.

[0035] In S102, the target layout feature information is processed through a defect correction model to obtain a target defect correction strategy of the target mask layout. The defect correction model is a model obtained by fine-tuning a large model according to historical layout feature information and corresponding historical defect correction strategies.

[0036] In this embodiment, the defect correction model is constructed based on machine learning or deep learning, and is obtained by training using historical layout feature information and corresponding historical defect correction strategies. Based on the training of the defect correction model, the defect correction model can be further fine-tuned according to new historical layout feature information and corresponding historical defect correction strategies to improve the recognition accuracy and efficiency of the defect correction model.

[0037] The target defect correction strategy is used to represent the corresponding correction measures that need to be taken for the defects of the target mask layout. For example, the defect correction strategy can include operations such as breaking, moving, deleting, enlarging, shrinking, etc. on the defect pattern and / or the mask pattern around it, and operations such as adding or deleting sub-resolution assist features, etc.

[0038] As an example, the server inputs the target mask layout feature information of the target mask layout into the fine-tuned defect correction model, the defect correction model analyzes the defect type to which the target layout feature information belongs, and outputs the corresponding target defect correction strategy.

[0039] S103, based on the target defect correction strategy, performing defect correction on the target mask layout to obtain the target mask layout after defect correction.

[0040] In this embodiment, the server uses the electronic design automation tool to correct the defects of the target mask layout according to the target defect correction strategy output by the defect correction model. Specifically, it can include operations such as breaking edges, moving, deleting, enlarging, shrinking, etc. on the defect patterns in the target mask layout and / or the mask patterns around them, as well as adding or deleting sub-resolution auxiliary patterns. Thus, the target mask layout after defect correction is obtained.

[0041] The processing method of the mask layout provided in this embodiment uses historical layout feature information and corresponding historical defect correction strategies to fine-tune a large model to obtain a defect correction model. After performing lithography rule checking on the target mask layout to obtain the target layout feature information of the target mask layout, only the target layout feature information needs to be input into the defect correction model to obtain the target defect correction strategy of the target mask layout, so that the defect correction of the target mask layout is completed according to the target defect correction strategy. In this way, the embodiments of the present application can directly determine the defect correction strategies corresponding to various layout defects through the defect correction model, thereby automatically completing the defect correction of the target mask layout. Without relying on experienced engineers to correct defects, the efficiency and accuracy of defect correction can be improved.

[0042] As an optional embodiment, before S102, the processing method of the correction mask layout can further include:

[0043] Obtaining target training data, a target large model, and a target fine-tuning algorithm, the target training data including historical layout feature information and corresponding historical defect correction strategies;

[0044] Based on the historical layout feature information, the historical defect correction strategy, and the target fine-tuning algorithm, training the target large model until the training stop condition is met to obtain the defect correction model.

[0045] In this embodiment, the historical layout feature information includes historical layout defect information of the historical mask layout and surrounding environment information of the layout defects of the historical mask layout.

[0046] The historical layout feature information is usually obtained from actual layout data in a semiconductor manufacturing or design process, which contains various known defects and the surrounding environment of the defects. The historical layout feature information needs to be stored in a computer-readable form, such as an image file, a vector graphics file, or a specific layout description language file.

[0047] For each known defect in the historical layout feature information, one or more corresponding historical defect correction strategies need to be recorded. These historical defect correction strategies can be instructions for automatic correction operations (such as filling missing parts, removing redundant parts, adjusting sizes, etc.), or recommended manual correction steps.

[0048] The target large model is a deep learning model used for training, which should have the ability to process image or graphics data. For example, the target large model can be a large model of the BERT series and the GPT series.

[0049] The target fine-tuning algorithm is a fine-tuning algorithm used when training the target large model. For example, the target fine-tuning algorithm can be Prefix Tuning, Adapter Tuning, Prompt Tuning, P-Tuning, LoRA, etc.

[0050] As an example, the server inputs the historical layout feature information and the corresponding historical defect correction strategy as training data into the target large model. Using the target fine-tuning algorithm, the target large model parameters are iteratively adjusted through methods such as backpropagation and gradient descent to minimize the loss function.

[0051] Then, when the training stop condition is met, the training of the target large model is stopped, and the corresponding defect correction model is obtained. Specifically, the performance on the validation set (such as accuracy, recall, F1 score, etc.), the number of training rounds, and whether the loss value converges can be used to determine when to stop training.

[0052] Through this embodiment, a defect correction model that can automatically recommend defect correction strategies for specific defects is constructed by combining historical layout feature information, historical defect correction strategies, large models, and fine-tuning algorithms. In this way, by constructing the defect correction model, the efficiency and accuracy of defect correction can be improved.

[0053] As an optional embodiment, the target mask layout includes a defect pattern of the bridge connection defect type;

[0054] S103 can specifically include:

[0055] Obtain the bridge connection region in the target mask layout;

[0056] A first pattern correction operation is performed on the first mask patterns in the bridge area to separate the exposure profiles between the first mask patterns, thereby obtaining a target mask layout after defect correction, wherein the first mask patterns are the mask patterns whose exposure profiles are connected in the bridge area.

[0057] In this embodiment, the bridge defect type refers to a phenomenon in which exposure profiles of different mask patterns are connected, which is generally caused by the mask patterns being too close to each other or being affected by sub-resolution auxiliary patterns.

[0058] like Figure 2 FIG. 2 shows a schematic diagram of a mask pattern under an ideal condition, wherein the exposure profile 202 generated by each mask pattern is generally within the pattern boundary range 201 thereof.

[0059] like Figure 3 , a schematic diagram of a mask pattern of a bridge defect type is provided, wherein the exposure profile 202 generated by each mask pattern obviously exceeds its pattern boundary range 201, and the exposure profiles 202 generated by each mask pattern are connected.

[0060] The first mask pattern is a mask pattern in which the exposure contour connection phenomenon occurs in the bridge area of ​​the target mask pattern, that is, a defect pattern of the bridge defect type in the target mask pattern.

[0061] The first pattern correction operation is used to represent a correction operation for separating exposure profiles between the first mask patterns, thereby overcoming the influence of bridge defects.

[0062] As an example, the server marks the corresponding bridge area in the target mask layout according to the target layout feature information, and identifies the first mask patterns where all exposure profiles are connected in the bridge area.

[0063] Next, for each first mask pattern, first pattern correction operations such as line movement, scaling, rotation, deletion, and addition are performed to separate the exposure profiles between the first mask patterns, thereby eliminating bridging defects. After the first pattern correction operations are completed, a defect-corrected target mask layout is obtained and output to a manufacturing-ready file format, ready for subsequent manufacturing processes.

[0064] This embodiment performs a first pattern correction operation on a target mask layout containing defective patterns of the bridge defect type, thereby separating the exposure profiles of the first mask patterns whose exposure profiles are connected in the bridge region. This allows for precise defect correction of the target mask layout with the bridge defect type, improving the accuracy of defect correction.

[0065] As an optional embodiment, the first pattern correction operation comprises at least one of the following:

[0066] moving each first mask pattern in a target direction, the target direction being a direction in which the distance between the first mask patterns increases;

[0067] deleting sub-resolution assist patterns that are within a preset distance threshold from the first mask patterns, or moving the sub-resolution assist patterns in a direction away from the first mask patterns so that the distance between the sub-resolution assist patterns and the first mask patterns is greater than or equal to the preset distance threshold;

[0068] increasing the first distance between each first mask pattern and the second distance, the first distance being the minimum distance between the inflection points of two first mask patterns, and the second distance being the minimum distance between the inflection points of two first mask patterns and the end points of a line segment. In this embodiment, as a first example, after determining the first mask patterns in the bridge connection region, the server determines a target direction according to the first mask patterns, which should increase the distance between the first mask patterns, thereby eliminating the bridge connection defect.

[0069] Then, using the move tool in the layout editing software, select the first mask pattern that needs to be moved. Drag the first mask pattern in the target direction, or input the specific moving distance and angle parameters, so that the first mask pattern moves to a new position. Finally, after the moving operation is completed, verify the corrected mask pattern to check whether the bridge connection defect is eliminated, and stop the operation until the bridge connection defect is eliminated.

[0070] As a second example, after determining the first mask patterns in the bridge connection region, the server needs to identify the sub-resolution assist patterns associated with the first mask patterns, which may be located near or inside the first mask patterns. Specifically, each sub-resolution assist pattern that is within a preset distance threshold from the first mask pattern is a sub-resolution assist pattern associated with the first mask pattern. The preset distance threshold is the distance threshold set when adding the sub-resolution assist pattern to the first mask pattern. If the distance between the sub-resolution assist pattern and the first mask pattern is too small, it may cause a bridge connection defect. At this time, these sub-resolution assist patterns can be deleted, or the sub-resolution assist patterns can be moved in a direction away from the first mask pattern to increase the distance between them, until the distance between the sub-resolution assist pattern and the first mask pattern is greater than or equal to the preset distance threshold. Then, verify the corrected first mask pattern to check whether the bridge connection defect is eliminated, and stop the operation until the bridge connection defect is eliminated. At the same time, further confirm whether the deletion or movement of the sub-resolution assist pattern has a negative impact on the lithography process.

[0071] As a third example, after the server determines the first mask patterns in the bridge connection region, the server selects each first mask pattern that needs to increase the distance using the adjustment tool in the layout editing software. Then, the server adjusts the position of the inflection point or the length of the line segment in the first mask pattern according to actual needs, so as to increase the minimum distance between the inflection points of each first mask pattern and the minimum distance between the inflection point of the first mask pattern and the end point of the line segment. Then, the server verifies the corrected first mask pattern, checks whether the bridge connection defect is eliminated, and stops the operation until the bridge connection defect is eliminated.

[0072] Through the embodiment, a plurality of first pattern correction operations are provided to separate the exposure contours between the first mask patterns. In this way, the most appropriate first pattern correction operation can be selected for defect correction according to the specific defect situation of the target mask layout, and the accuracy of defect correction can be improved.

[0073] As an optional embodiment, the target mask layout includes a defect pattern of the necking defect type;

[0074] S103 can specifically include:

[0075] Obtaining a necking region in the target mask layout;

[0076] Performing a second pattern correction operation on the second mask pattern in the necking region to obtain a target mask layout after defect correction, the second mask pattern being a mask pattern that cannot form an exposure contour in the necking region, and the second pattern correction operation including at least one of adjusting the position of the second mask pattern and expanding the pattern size of the second mask pattern.

[0077] In the embodiment, the necking defect type refers to a defect type in which a mask pattern cannot form a corresponding exposure contour due to reasons such as too small size of the mask pattern or poor photolithography effect.

[0078] The second mask pattern is a mask pattern that cannot form a corresponding exposure contour in the necking region of the target mask layout, that is, a defect pattern of the necking defect type in the target mask layout.

[0079] The second pattern correction operation is used to represent an operation for overcoming the necking defect. For example, the second pattern correction operation can be adjusting the position of the second mask pattern or expanding the pattern size of the second mask pattern.

[0080] As an example, the server marks the corresponding necking region in the target mask layout according to the target layout feature information, and identifies all second mask patterns that cannot form an exposure contour in the necking region.

[0081] Then, for each second mask pattern, a second pattern correction operation is respectively taken to enable each second mask pattern to form a corresponding exposure profile, so as to eliminate the necking defect. After the second pattern correction operation is completed, the target mask template pattern after defect correction is obtained, and the target mask template pattern after defect correction is output in a file format that can be used for manufacturing, to prepare for subsequent manufacturing processes.

[0082] Specifically, for some second mask patterns, the conflict with adjacent patterns can be avoided by slightly moving the position thereof, so as to improve the photolithography effect and reduce the possibility of necking; for other second mask patterns, the size thereof can be directly increased to ensure that there is sufficient material to fill in the photolithography process, so as to avoid the formation of necking.

[0083] Through the embodiment, a plurality of second pattern correction operations are provided to enable each second mask pattern in the target mask template pattern to form a corresponding exposure profile. In this way, the most appropriate second pattern correction operation can be selected for defect correction according to the specific defect condition of the target mask template pattern, and the accuracy of defect correction can be improved.

[0084] As an optional embodiment, the target mask template pattern includes a defect pattern of a sub-resolution assist pattern defect type;

[0085] S103 can specifically include:

[0086] An abnormal sub-resolution assist pattern in the target mask template pattern is obtained, the abnormal sub-resolution assist pattern being a sub-resolution assist pattern that forms an exposure profile in the target mask template pattern;

[0087] A third pattern correction operation is performed on the sub-resolution assist pattern to obtain the target mask template pattern after defect correction, the third pattern correction operation including at least one of a deletion operation on the sub-resolution assist pattern and an area reduction operation on the sub-resolution assist pattern.

[0088] In the embodiment, the sub-resolution assist pattern does not form an exposure profile in an ideal state, and the sub-resolution assist pattern defect type is used to represent that the sub-resolution assist pattern forms a corresponding exposure profile.

[0089] The abnormal sub-resolution assist pattern is a sub-resolution assist pattern that forms an exposure profile in the target mask template pattern, that is, a defect pattern of the sub-resolution assist pattern defect type in the target mask template pattern.

[0090] The third pattern correction operation is used to represent an operation for overcoming the sub-resolution assist pattern defect. For example, the third pattern correction operation can be deleting the corresponding sub-resolution assist pattern or reducing the area of the corresponding sub-resolution assist pattern.

[0091] As an example, the server marks the corresponding abnormal sub-resolution assist patterns in the target mask layout according to the target layout feature information.

[0092] Then, for each abnormal sub-resolution assist pattern, a third pattern correction operation is respectively taken to make each abnormal sub-resolution assist pattern no longer form the corresponding exposure contour, so as to eliminate the sub-resolution assist pattern defects. After the third pattern correction operation is completed, the defect-corrected target mask layout is obtained, and the defect-corrected target mask layout is output in a file format that can be used for manufacturing, in preparation for subsequent manufacturing processes.

[0093] Specifically, for those abnormal sub-resolution assist patterns that obviously do not meet the design requirements or may have a negative impact on the performance of the chip, a deletion operation is directly performed, which usually requires removing all related parts of these patterns from the target mask layout.

[0094] For some cases, if deleting the abnormal sub-resolution assist patterns may cause significant changes to adjacent patterns or deterioration of the process window, area reduction operations can be considered for them. This usually requires reducing the size of the abnormal sub-resolution assist patterns to the extent that they no longer form exposure contours, while maintaining their positive impact on the lithography process.

[0095] Through the embodiment, a plurality of third pattern correction operations are provided to make each abnormal sub-resolution assist pattern in the target mask layout no longer form the corresponding exposure contour. In this way, the most appropriate third pattern correction operation can be selected for defect correction according to the specific defect situation of the target mask layout, and the accuracy of defect correction can be improved.

[0096] As an optional embodiment, after S103, the method for processing the modified mask layout can further include:

[0097] performing a manufacturing rule check operation on the target mask layout to obtain a layout check result;

[0098] in a case where the layout check result indicates that the target mask layout does not have manufacturing rule violation problems, determining the target mask layout as a final mask layout;

[0099] in a case where the layout check result indicates that the target mask layout has manufacturing rule violation problems, modifying the violation area of the target mask layout until the target mask layout does not have layout defects and does not have manufacturing rule violation problems, to obtain a final mask layout.

[0100] In this embodiment, the manufacturing rule check is a process of verifying whether the design of the target mask layout meets certain standards and specifications through predefined rules. These predefined rules usually cover aspects such as circuit design, constraints, testing process, etc., aiming to find and correct problems that may affect testing or fault simulation.

[0101] As an example, after defect correction on the target mask layout, the server obtains the defect-corrected target mask layout. Further manufacturing rule check is performed on the defect-corrected target mask layout to obtain the layout inspection result, ensuring that the defect-corrected target mask layout still meets the design requirements.

[0102] If the layout inspection result indicates that there is no manufacturing rule violation problem in the target mask layout, the target mask layout can be directly determined as the final mask layout for subsequent production and manufacturing processes; if the layout inspection result indicates that there is a manufacturing rule violation problem in the target mask layout, the violation area needs to be corrected. And after correction, manufacturing rule check is performed again until the target mask layout does not have layout defects and does not have manufacturing rule violation problems, and the target mask layout is determined as the final mask layout for subsequent production and manufacturing processes.

[0103] Through this embodiment, after defect correction on the target mask layout, the defect-corrected target mask layout is obtained, and the manufacturing rule check is performed on the target mask layout again. In this way, it can be ensured that the final mask layout can meet the requirements of production and manufacturing.

[0104] As an optional embodiment, before S101, the method for correcting the mask layout can further include:

[0105] For at least one mask pattern in the target mask layout, at least one sub-resolution auxiliary pattern is added within a range with a distance less than a preset distance threshold from the mask pattern, to obtain an updated mask layout.

[0106] S101 can specifically include:

[0107] Performing photolithography rule check on the updated mask layout to obtain target layout feature information of the updated mask layout.

[0108] In this embodiment, the updated mask layout is used to represent the mask layout obtained after adding a sub-resolution auxiliary pattern to at least one mask pattern in the target mask layout.

[0109] As an example, before the photolithography rule check, in order to optimize the photolithography effect, at least one mask pattern in the target mask layout needs to be preprocessed.

[0110] Specifically, the server first identifies all mask patterns from the target mask layout. Then, for mask patterns with poor exposure effect, sub-resolution assist patterns are added respectively. The sub-resolution assist patterns are usually some small assist patterns that do not form actual circuit patterns. Their role is to improve the image contrast in the lithography process and reduce pattern deformation caused by diffraction and interference effects. The adding position and size of the sub-resolution assist patterns are usually determined according to lithography simulation results and process conditions.

[0111] After adding the sub-resolution assist patterns to each mask pattern, an updated mask layout is obtained. Finally, lithography rule checking is performed on the updated mask layout.

[0112] Through the embodiment, sub-resolution assist patterns are added to the mask patterns in the target mask layout, so that the image contrast in the lithography process can be improved and the exposure effect of the mask patterns can be improved.

[0113] The processing method based on the corrected mask layout is provided. Accordingly, the application also provides specific embodiments of a mask layout processing device.

[0114] As shown in Figure 4 The mask layout processing device 400 provided by the embodiments of the application includes a layout checking module 410, a strategy determining module 420, and a layout correcting module 430.

[0115] The layout checking module 410 is configured to perform lithography rule checking on the target mask layout to obtain target layout feature information of the target mask layout. The layout feature information includes layout defect information and surrounding environment information of the layout defect.

[0116] The strategy determining module 420 is configured to process the target layout feature information by using a defect correction model to obtain a target defect correction strategy of the target mask layout. The defect correction model is a model obtained by fine-tuning a large model according to historical layout feature information and corresponding historical defect correction strategies.

[0117] The layout correcting module 430 is configured to correct defects in the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction.

[0118] The mask plate processing apparatus provided by the embodiment can directly determine the defect correction strategy corresponding to various pattern defects through the defect correction model, thereby automatically completing the defect correction of the target mask plate. The defect correction does not need to rely on experienced engineers, and the efficiency and accuracy of the defect correction can be improved.

[0119] As an optional embodiment, before the defect correction model is used to process the target pattern feature information to obtain the target defect correction strategy of the target mask plate, the mask plate processing apparatus 400 can further include the following modules:

[0120] The data acquisition module is configured to acquire target training data, a target large model, and a target fine-tuning algorithm, wherein the target training data includes historical pattern feature information and corresponding historical defect correction strategies.

[0121] The model training module is configured to train the target large model based on the historical pattern feature information, the historical defect correction strategies, and the target fine-tuning algorithm until a training stop condition is met, and obtain a defect correction model.

[0122] As an optional embodiment, the target mask plate includes a defect pattern of a bridge defect type.

[0123] The pattern correction module 430 is specifically configured to:

[0124] Obtain a bridge region in the target mask plate.

[0125] Perform a first pattern correction operation on first mask patterns in the bridge region to separate the exposure contours of the first mask patterns from each other, and obtain a target mask plate after defect correction, wherein the first mask patterns are mask patterns with connected exposure contours in the bridge region.

[0126] As an optional embodiment, the target mask plate includes a defect pattern of a necking defect type.

[0127] The pattern correction module 430 is specifically configured to:

[0128] Obtain a necking region in the target mask plate.

[0129] performing a second pattern correction operation on a second mask pattern in the necking area to obtain the target mask layout after defect correction, the second mask pattern being a mask pattern in the necking area that cannot form an exposure contour, and the second pattern correction operation including at least one of adjusting a position of the second mask pattern and expanding a pattern size of the second mask pattern.

[0130] As an optional embodiment, the target mask layout includes a defect pattern of a sub-resolution assist pattern defect type.

[0131] The layout correction module 430 is specifically configured to:

[0132] obtaining an abnormal sub-resolution assist pattern in the target mask layout, the abnormal sub-resolution assist pattern being a sub-resolution assist pattern in the target mask layout that forms an exposure contour;

[0133] performing a third pattern correction operation on the sub-resolution assist pattern to obtain the target mask layout after defect correction, the third pattern correction operation including at least one of a deletion operation on the sub-resolution assist pattern and an area reduction operation on the sub-resolution assist pattern.

[0134] As an optional embodiment, after performing defect correction on the target mask layout based on a target defect correction strategy to obtain the target mask layout after defect correction, the mask layout processing device 400 can further include the following modules:

[0135] The layout inspection module 410 is further configured to perform a manufacturing rule inspection operation on the target mask layout to obtain a layout inspection result.

[0136] The layout determination module is configured to determine the target mask layout as a final mask layout in a case where the layout inspection result indicates that the target mask layout does not have a manufacturing rule violation problem.

[0137] The layout determination module is further configured to, in a case where the layout inspection result indicates that the target mask layout has a manufacturing rule violation problem, correct a violation area of the target mask layout until the target mask layout does not have a layout defect and does not have a manufacturing rule violation problem, to obtain the final mask layout.

[0138] As an optional embodiment, before performing lithography rule inspection on the target mask layout to obtain target layout feature information of the target mask layout, the mask layout processing device 400 can further include the following modules:

[0139] The layout update module is configured to, for at least one mask pattern in the target mask layout, add at least one sub-resolution assist pattern in a range in which a distance from the mask pattern is less than a preset distance threshold, to obtain an updated mask layout.

[0140] The layout inspection module 410 is specifically configured to:

[0141] Performing photolithography rule inspection on the updated mask layout to obtain target layout feature information of the updated mask layout.

[0142] The processing method of the mask layout. Accordingly, the present application also provides specific embodiments of the processing device of the mask layout.

[0143] Figure 5 The hardware structure schematic diagram of the processing device of the mask layout provided by the embodiments of the present application is shown.

[0144] The processing device of the mask layout can include a processor 501 and a memory 502 storing computer program instructions.

[0145] Specifically, the above-mentioned processor 501 can include a central processing unit (CPU), or a specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits of the embodiments of the present application.

[0146] The memory 502 can include a mass storage for data or instructions. By way of example and not limitation, the memory 502 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 502 can include removable or non-removable (or fixed) media. Where appropriate, the memory 502 can be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, the memory 502 is a non-volatile solid-state memory.

[0147] The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement any one of the processing methods of the mask layout in the above-mentioned embodiments.

[0148] In one example, the processing device of the mask layout can also include a communication interface 503 and a bus 510. Wherein, as shown in the figure, the processor 501, the memory 502, the communication interface 503 are connected through the bus 510 and complete the communication between each other. Figure 5

[0149] The communication interface 503 is mainly used to realize the communication between each module, device, unit and / or equipment in the embodiments of the present application.

[0150] ​Bus 510 includes hardware, software, or both, to couple components of the mask artwork processing device to each other in a form, for example, but not limited to, a computer bus, a graphics bus (e.g., Accelerated Graphics Port (AGP) or other graphics bus), a Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand (IB) interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association local (VLB) bus, or another suitable bus or a combination of two or more of these. Where appropriate, bus 510 can include one or more buses. Although the application embodiments described and illustrated herein focus on particular buses, the application contemplates any suitable bus or interconnect.

[0151] In addition, in combination with the mask artwork processing method in the above embodiments, the embodiments of the application can provide a computer storage medium to implement. The computer storage medium has computer program instructions stored thereon; the computer program instructions are executed by a processor to implement any one of the mask artwork processing methods in the above embodiments.

[0152] In addition, in combination with the mask artwork processing method in the above embodiments, the embodiments of the application can provide a computer program product to implement, the instructions in the computer program product are executed by the processor of the electronic device to make the electronic device execute the mask artwork processing method provided by any one of the above embodiments of the application.

[0153] It needs to be clear that the application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after understanding the spirit of the application.

[0154] The functions noted in the description of the structural block diagrams above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, functional cards, and the like. When implemented in software, the elements of the present application are program or code segments that are used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. A "machine-readable medium" includes any medium that can store or transport information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, and the like. The code segments can be downloaded via computer networks such as the Internet, intranets, and the like.

[0155] It is also important to note that the examples mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the steps mentioned above, that is, the steps can be performed in the order mentioned in the examples, or in an order different from the examples, or several steps can be performed simultaneously.

[0156] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer program instructions can also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other processing device to operate in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function / act specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer program instructions can also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other processing device to operate in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function / act specified in the flowchart and / or block diagram block or blocks.

[0157] The above merely describes a specific implementation of the present application. Those skilled in the art can clearly understand the specific working processes of the system, modules and units described above for the convenience and brevity of description, and can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein again. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A method for processing a mask layout, characterized in that: include: Performing a lithography rule check on a target mask layout to obtain target layout feature information of the target mask layout, wherein the layout feature information includes layout defect information and surrounding environment information of the layout defect; Processing the target layout feature information through a defect correction model to obtain a target defect correction strategy for the target mask layout, wherein the defect correction model is a model obtained by fine-tuning a large model based on historical layout feature information and corresponding historical defect correction strategies; Based on the target defect correction strategy, the target mask layout is defect corrected to obtain a target mask layout after defect correction; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: obtaining a bridge region in the target mask layout when the target mask layout includes a defect pattern of a bridge defect type; performing a first pattern correction operation on first mask patterns in the bridge region to separate exposure profiles between the first mask patterns, thereby obtaining the target mask layout after defect correction, wherein the first mask patterns are mask patterns having connected exposure profiles in the bridge region; After performing defect correction on the target mask layout based on the target defect correction strategy to obtain the defect-corrected target mask layout, the method further includes: performing a manufacturing rule check operation on the target mask layout to obtain a layout check result; when the layout check result indicates that the target mask layout does not have any manufacturing rule violation problem, determining the target mask layout as the final mask layout; when the layout check result indicates that the target mask layout has a manufacturing rule violation problem, correcting the violation area of ​​the target mask layout until the target mask layout has no layout defects and no manufacturing rule violation problem, thereby obtaining the final mask layout.

2. The method according to claim 1, characterized in that Before processing the target layout feature information by using the defect correction model to obtain the target defect correction strategy of the target mask layout, the method further includes: Obtaining target training data, a target large model, and a target fine-tuning algorithm, wherein the target training data includes the historical layout feature information and the corresponding historical defect correction strategy; Based on the historical layout feature information, the historical defect correction strategy and the target fine-tuning algorithm, the target large model is trained until the training stop condition is met to obtain the defect correction model.

3. The method according to claim 1, characterized in that The first graphics correction operation includes at least one of the following: moving each of the first mask patterns along a target direction, wherein the target direction is a direction in which a distance between the first mask patterns increases; Deleting a sub-resolution auxiliary pattern whose distance from the first mask pattern is less than a preset distance threshold, or moving the sub-resolution auxiliary pattern in a direction away from the first mask pattern so that the distance between the sub-resolution auxiliary pattern and the first mask pattern is greater than or equal to the preset distance threshold; The first distance and the second distance between each of the first mask patterns are increased, wherein the first distance is the minimum distance between the inflection points of two first mask patterns, and the second distance is the minimum distance between the inflection points of two first mask patterns and the endpoints of a line segment.

4. The method according to claim 1, wherein The target mask pattern includes a defect pattern of a necking defect type; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: Acquire a necking region in the target mask layout; A second graphic correction operation is performed on the second mask pattern in the necking area to obtain the target mask pattern after defect correction, wherein the second mask pattern is a mask pattern that cannot form an exposure profile in the necking area, and the second graphic correction operation includes at least one of adjusting the position of the second mask pattern and enlarging the graphic size of the second mask pattern.

5. The method according to claim 1, wherein The target mask pattern includes a defect pattern of a sub-resolution auxiliary pattern defect type; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: Acquiring an abnormal sub-resolution auxiliary pattern in the target mask layout, wherein the abnormal sub-resolution auxiliary pattern is a sub-resolution auxiliary pattern that forms an exposure profile in the target mask layout; A third pattern correction operation is performed on the sub-resolution auxiliary pattern to obtain the target mask pattern after defect correction, wherein the third pattern correction operation includes at least one of a deletion operation on the sub-resolution auxiliary pattern and an area reduction operation on the sub-resolution auxiliary pattern.

6. The method according to any one of claims 1 to 5, characterized in that Before performing the lithography rule check on the target mask layout to obtain target layout feature information of the target mask layout, the method further includes: For at least one mask pattern in the target mask layout, add at least one sub-resolution auxiliary pattern within a range where the distance from the mask pattern is less than a preset distance threshold, to obtain an updated mask layout; The performing of a lithography rule check on the target mask layout to obtain target layout feature information of the target mask layout includes: Performing a lithography rule check on the updated mask layout to obtain target layout feature information of the updated mask layout.

7. An electronic device, characterized in that: The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the mask layout processing method according to any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for processing a mask layout according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the mask layout processing method according to any one of claims 1 to 6.

Images