Digital PAD multiplexing method for SOC system

Abstract

The invention discloses a digital PAD multiplexing method for an SOC system, and the method comprises the following steps: a, setting the external connection of a digital PAD to have a strong pull-up state, a strong pull-down state and a high-resistance state, carrying out the broadening of k1 clock cycles on a reset signal of the SOC system, carrying out the broadening of k2 clock cycles on a reset signal of a detection module, and carrying out the broadening of k2lt; k1; k2; b, after the detection module is reset, starting to time n1 clock cycles, and latching a first input value of the digital PAD; c, a built-in pull-up / pull-down resistor of the digital PAD is switched, n2 clock periods are timed, and a second input value of the digital PAD is latched; d, confirming the operation mode of the SOC system through the two input values; and e, releasing the authority of the digital PAD. According to the method disclosed by the invention, one digital PAD can realize selection of multiple modes, the input of the digital PAD does not need to be modified, the input and output functions of the digital PAD are not influenced, and the digital PAD can also be multiplexed into other modes.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly to a digital PAD multiplexing method for a SOC system. Background Art

[0002] In a commonly used SOC system, a plurality of working modes are usually set, and when the SOC system is powered on, it is necessary to confirm the current working mode of the system to ensure that the system works according to the set mode.

[0003] The commonly used methods for confirming the working mode of the SOC system usually include the following:

[0004] Method 1: Use multiple digital PADs to control the selection of working modes, and each digital PAD controls one mode. If the current SOC system is set with three working modes, three digital PADs are required to confirm and control these three working modes; for example, PAD1 controls whether mode A is turned on, PAD2 controls whether mode B is turned on, and PAD3 controls whether mode C is turned on; but this method requires the addition of additional digital PADs. Each time the SOC system adds a working mode, a digital PAD needs to be added, which greatly reduces the utilization rate of the digital PAD. In addition, the digital PAD is directly connected to the power supply or ground, making the digital PAD non-reusable, thereby increasing the cost.

[0005] Method 2: Also use multiple digital PADs, and confirm the multiple modes of controlling the SOC system through the combinational logic of multiple digital PAD inputs. If the current SOC system is set with 3 working modes, 2 digital PADs are required. The system working mode is confirmed by judging the combinational logic of PAD1 and PAD2. For example, PAD1 and PAD2 input low level, the combinational logic is 00, and control mode A is turned on; PAD1 inputs high level, PAD2 inputs low level, the combinational logic is 01, and control mode B is turned on; PAD1 and PAD2 both input high level, the combinational logic is 11, and control mode CB is turned on. In this way, the number of digital PADs required is reduced from 3 to 2, but each digital PAD can only select 2 modes, the utilization rate of the digital PAD is not high, and the digital PAD is directly connected to the power supply or ground, which makes the digital PAD non-reusable, increasing the cost.

[0006] Method 3: Input through an external configuration interface. For example, an IIC Master (IIC host) is embedded in the SOC system, and data of an external EEROM or other Slave devices is read through the IIC bus to configure the system working mode. In this way, an external configuration data transmission channel is required, increasing the RTL logic. In addition, it takes a certain amount of time to read external data, and the SOC system needs to wait for the bus data transmission to complete before powering on to enter a specific working mode, extending the system power-on time. External devices are also needed to store data, increasing the application cost of the SOC system.

[0007] Therefore, it is necessary to provide an improved digital PAD multiplexing method for the SOC system to overcome the above defects. Summary of the Invention

[0008] The object of the present invention is to provide a digital PAD multiplexing method for the SOC system. The digital PAD multiplexing method of the present invention enables a digital PAD to implement multiple mode selections without modifying the input of the digital PAD, without affecting the input and output functions of the digital PAD, and the digital PAD can also be multiplexed into other modes.

[0009] To achieve the above object, the present invention provides a digital PAD multiplexing method for the SOC system, which includes the following steps: a. Set the external connection of the digital PAD to have a strong pull-up, strong pull-down or high-impedance state, widen the reset signal of the SOC system for k1 clock cycles, widen the reset signal of the detection module for k2 clock cycles, and k2 < k1; b. After the SOC system is powered on and the detection module is reset, start timing for n1 clock cycles and latch the first input value of the digital PAD into the first register; c. Switch the internal pull-up / pull-down resistors of the digital PAD, start timing for n2 clock cycles, and latch the second input value of the digital PAD into the second register; d. Confirm the operating mode of the SOC system through the two input values latched by the first register and the second register; e. Release the permission of the digital PAD.

[0010] Preferably, the digital PAD can selectively connect an external strong pull-up resistor and a strong pull-down resistor, so that the external connection of the digital PAD has three states: strong pull-up, strong pull-down and high impedance.

[0011] Preferably, the internal pull-up resistor of the digital PAD is an internal weak pull-up resistor, the internal pull-down resistor of the digital PAD is an internal weak pull-down resistor, and the internal default of the digital PAD is a weak pull-up resistor or a weak pull-down resistor.

[0012] Preferably, the widening time k1 of the reset signal of the SOC system, the widening time k2 of the reset signal of the detection module, and the timing times n1 and n2 satisfy the relationship: k1 > k2 + n1 + n2.

[0013] Preferably, when the built-in resistor of the digital PAD switches from pull-up to pull-down and from pull-down to pull-up, the values ​​latched in the first register and the second register are the same.

[0014] Preferably, the switching time of the built-in pull-up / pull-down resistor of the digital PAD is less than the sum of the reset signal widening time of the detection module and the first timing time, and the switching time of the built-in pull-up / pull-down resistor of the digital PAD is recorded as k3 clock cycles, then, k3 <k2+n1。

[0015] Compared with the prior art, the digital PAD multiplexing method for the SOC system of the present invention, by setting the external connection of the digital PAD to have three states of strong pull-up, strong pull-down and high resistance, enables the digital PAD to have the ability to select three modes, thereby realizing the multiplexing of the digital PAD; the entire confirmation process of the SOC system mode is completed during the reset process of the SOC system, and there is no need to increase the additional power-on time of the system, and does not affect the normal operation of the system; no external storage device is required, and only one pull-up or pull-down resistor is required to realize it, so the implementation structure is simple and the application cost is low; in addition, it is realized by external pull-up / pull-down resistors, which does not affect the input and output functions of the digital PAD, so the digital PAD can also be multiplexed into other modes, thereby expanding the application of the digital PAD.

[0016] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The figure is a flow chart of the digital PAD multiplexing method for SOC system of the present invention.

[0018] Figure 2a and Figure 2b It is a structural schematic diagram of a digital PAD of the present invention with an external strong pull-up resistor.

[0019] Figure 3a and Figure 3b It is a structural schematic diagram of a digital PAD externally connected to a strong pull-down resistor of the present invention.

[0020] Figure 4a and Figure 4b It is a schematic diagram of the structure of the digital PAD of the present invention being externally suspended. DETAILED DESCRIPTION

[0021] Reference is now made to the drawings, in which like reference numerals represent like elements. As described above, the present invention provides a digital PAD multiplexing method for an SOC system. The digital PAD multiplexing method of the present invention enables a digital PAD to implement multiple mode selections without modifying the input of the digital PAD, without affecting the input / output function of the digital PAD, and the digital PAD can also be multiplexed into other modes, expanding the function of the digital PAD.

[0022] Please refer to Figure 1 , Figure 1 which is a flowchart of the digital PAD multiplexing method for an SOC system according to the present invention. As shown in the figure, the digital PAD multiplexing method for an SOC system according to the present invention includes the following steps:

[0023] Step S001, set the external connection of the digital PAD to have a strong pull-up, strong pull-down or high-impedance state, and widen the reset signal of the SOC system for k1 clock cycles, and widen the reset signal of the detection module for k2 clock cycles, and k2 < k1; in this step, the digital PAD can selectively connect an external strong pull-up resistor and a strong pull-down resistor to make the external connection of the digital PAD have a strong pull-up, strong pull-down or high-impedance state; specifically, as Figure 2a and Figure 2b shown, the digital PAD is externally connected to a strong pull-up resistor, that is, one end of the 4.7k strong pull-up resistor is connected to the power supply voltage VCC and the other end is connected to the digital PAD, so that the external connection of the digital PAD is in a strong pull-up state; as Figure 3a and Figure 3b shown, the digital PAD is externally connected to a strong pull-down resistor, that is, one end of the 4.7k strong pull-down resistor is grounded and the other end is connected to the digital PAD, so that the external connection of the digital PAD is in a strong pull-down state; as Figure 4a and Figure 4b shown, the external connection of the digital PAD is floating, that is, the digital PAD is neither connected to a pull-up resistor nor a pull-down resistor, and the floating external connection of the digital PAD makes its external connection in a high-impedance state; therefore, comprehensively Figures 2a to 4bIt can be known that by setting the external connection situation of the digital PAD, the external connection of the digital PAD can have a strong pull-up, a strong pull-down or a high-impedance state, so as to correspondingly confirm and control three operating modes of the SOC system; in addition, in this step, the reset signals of both the SOC system and the detection module are widened. Widening the two reset signals mainly ensures the stability of the power supply voltage of the entire system and the electrical stability of the internal analog circuit, so that the system can quickly enter a normal and stable working state after reset; among them, the widening time (k1 clock cycles) of the reset signal of the SOC system is greater than the widening time (k2 clock cycles) of the reset signal of the detection module, that is, k2 < k1. Such a design enables the detection module to detect the digital PAD after its reset signal is reset, and then confirm the state of the digital PAD and use it to confirm the selection of the working mode of the SOC system, so as to assist the SOC system to complete the normal reset process.

[0024] Step S002, after the SOC system is powered on and the detection module is reset, start timing for n1 clock cycles, and latch the first input value of the digital PAD into the first register; in this step, as described above, the digital PAD has three external connection states, but these three external connection states cannot exist simultaneously, that is, at the same moment, the digital PAD has only one external connection state (one of the strong pull-up, strong pull-down, and high-impedance states). Therefore, after the SOC system is powered on, the detection module detects the digital PAD (after k2 time) to confirm one external connection state of the digital PAD. At this time, start timing for n1 clock cycles, and when the timing reaches n1 clock cycles, latch the first input value of the digital PAD at this time into the first register, and record the first input value of the digital PAD at this time as Va11; in the present invention, after the digital PAD is detected by the detection module, it is timed for n1 clock cycles before latching the first input value of the digital PAD, that is, the first input value of the digital PAD is latched after its external connection state is stable and the first input value is stable, so as to ensure the accuracy and reliability of the latched first input value of the digital PAD.

[0025] Step S003: Switch the built-in pull-up / pull-down resistors of the digital PAD, start timing for n2 clock cycles, and latch the second input value of the digital PAD into the second register; In this step, as is well known, the digital PAD can also be optionally provided with a pull-up resistor and a pull-down resistor inside. However, the input value of the digital PAD will be different when connecting the built-in pull-up resistor or pull-down resistor. Therefore, it is necessary to switch the built-in pull-up / pull-down resistors of the digital PAD to change the input value of the digital PAD, latch the changed second input value into the second register, and record the second input value as Va12; In addition, in the present invention, during the process of switching the built-in resistor of the digital PAD from pull-up to pull-down and from pull-down to pull-up, the values (Va11 and Va12) latched by the first register and the second register are the same. Therefore, in the present invention, whether the built-in resistor of the digital PAD is pull-up or pull-down does not affect the confirmation control of the operating mode of the SOC system, as long as the built-in resistor of the digital PAD can be normally switched between pull-up and pull-down. In addition, in the present invention, the built-in state of the digital PAD being floating is not within the scope of the solutions involved in the present invention. To avoid the built-in of the digital PAD switching from floating to weak pull-up resistor or weak pull-down resistor during the switching process, the built-in of the digital PAD is defaulted to a weak pull-up resistor or a weak pull-down resistor; Among them, in order to ensure that the input value after the switching of the digital PAD can be accurately recorded, after the built-in resistor of the digital PAD is switched between pull-up / pull-down, its input value is latched into the second register only after timing for n2 clock cycles to prevent the input values before and after the switching from being repeated; Further, the switching time of the built-in pull-up / pull-down resistors of the digital PAD is less than the sum of the reset signal broadening time of the detection module and the time of the first timing. Record the switching time of the built-in pull-up / pull-down resistors of the digital PAD as k3 clock cycles, then, k3 < k2 + n1, so as to ensure that the switching of the built-in pull-up / pull-down resistors of the digital PAD is completed during the period from when the digital PAD is powered on and detected to when the first input value (Va11) is latched, so as not to affect the subsequent latching of the second input value (Va12). In addition, in the present invention, the built-in pull-up resistor of the digital PAD is a built-in weak pull-up resistor, and its built-in pull-down resistor is a built-in weak pull-down resistor, that is, there is no strong pull-up resistor or strong pull-down resistor provided inside the digital PAD. This enables the resistance value of the external resistor connected to the digital PAD to be not too small to achieve external strong pull-up or strong pull-down, so as to reduce the area occupied by the external resistor. If a strong pull-up resistor or strong pull-down resistor is provided inside the digital PAD, to achieve the same external strong pull-up or strong pull-down, external pull-down resistors and pull-up resistors with very small resistance values need to be used, which is not only difficult to achieve but also greatly increases the area occupied by the external resistor. Among them, the matching situation between the built-in pull-up resistor or pull-down resistor of the digital PAD and its external connection is as Figures 2a to 4bThe corresponding relationship between the external connection situation, the internal connection situation and the first input value Va11 and the second input value Va12 of the digital PAD is shown in Table 1 below:

[0026] PAD built-in weak pull-up PAD built-in weak pull-down {Va11,Va12} PAD external strong pull-up resistor 1 1 {1,1} PAD external strong pull-down resistor 0 0 {0,0} PAD is suspended and connected externally 1 0 {0,1}

[0027] Table 1

[0028] Step S004, confirming the operation mode of the SOC system through the two input values ​​latched by the first register and the second register; in this step, the operation mode of the SOC system is confirmed by the values ​​Va11 and Va12 latched by the first register and the second register, wherein as shown in Table 1, there are three expressions for the combination of Va11 and Va12, namely (0, 0), (1, 1), and (1, 0), to realize the confirmation control of the three operation modes of the SOC system. Of course, at this time, one of the three expressions is used to confirm and control an operation mode of the SOC system.

[0029] Specifically, the digital PAD generates three sets of input values ​​(0, 0), (1, 1), (1, 0), and its confirmation control mode for the SOC system is as follows:

[0030] Mode A: Digital PAD is connected to a strong pull-up resistor, Val1=1, Val2=1;

[0031] Mode B: Digital PAD is connected to a strong pull-down resistor, Val1 = 0, Val2 = 0;

[0032] Mode C: The digital PAD is externally connected and left floating, Val1=1, Val2=0.

[0033] Step S005, releasing the authority of the digital PAD; as of step S004, the confirmation control of the digital PAD on an operating mode in the SOC system has been completed. In this step, by releasing the authority of the digital PAD, the digital PAD can be used for other logical controls in the SOC system, thereby realizing the multiplexing function of the current digital PAD.

[0034] In addition, in order to ensure that the confirmation control of the SOC system operation mode by the digital PAD during the SOC system reset does not affect the normal operation of the SOC system, in the present invention, the expansion time k1 of the reset signal of the SOC system, the expansion time k2 of the reset signal of the detection module, and the timing times n1 and n2 are further set to satisfy the relationship: k1>k2+n1+n2.

[0035] Please refer to Figures 1 to 4b , the scheme of the present invention is illustrated by example:

[0036] There are three working modes in the SOC system, Mode A, Mode B, and Mode C. Only one of the three working modes can be selected to work at the same time.

[0037] The working mode of the SOC system is now selected according to the external connection of the digital PAD, where:

[0038] External strong pull-up resistor: Mode A

[0039] External strong pull-down resistor: Mode B

[0040] Externally connected and left floating: Mode C.

[0041] (1) The reset signal extension time of the SOC system is 20ms, and the reset signal extension time of the detection module is 10ms; the clock frequency is 25MHZ, and the digital PAD defaults to the built-in weak pull-up input mode.

[0042] (2) 10ms after the SOC system is powered on, the timer is used to count 15ms, and then the input value Val1 of the digital PAD is latched. At the same time, the digital PAD is modified to be built-in weak pull-down input mode, and the timing is restarted for 15ms. The switching frequency of the digital PAD (switching of the built-in pull-up / pull-down resistor) can reach 133MHZ, and 15ms is much longer than the switching time of the digital PAD.

[0043] (3) Timing 15ms, latching the input value Val2 of the digital PAD, and releasing the control authority of the digital PAD;

[0044] (4) Determine the values ​​of Val1 and Val2 and confirm the system working mode according to the following relationship:

[0045] Mode A: Digital PAD is connected to a strong pull-up resistor, Val1=1, Val2=1;

[0046] Mode B: Digital PAD is connected to a strong pull-down resistor, Val1 = 0, Val2 = 0;

[0047] Mode C: Digital PAD is externally connected and left floating, Val1=1, Val2=0;

[0048] (5) After 20 ms, the SOC system completes the reset operation, and the digital PAD determines the working mode of the SOC system. The SOC system enters the determined mode and starts working, and releases the digital PAD authority to control other functions.

[0049] In summary, the digital PAD multiplexing method for the SOC system of the present invention, by setting the external connection of the digital PAD to have three states of strong pull-up, strong pull-down and high resistance, enables the digital PAD to have the ability to select three modes, thereby realizing the multiplexing of the digital PAD; the entire confirmation process of the SOC system mode is completed during the reset process of the SOC system, without increasing the additional power-on time of the system, and does not affect the normal operation of the system; no external storage device is required, and only one pull-up or pull-down resistor is required to achieve it, the implementation structure is simple, and the application cost is low; in addition, it is achieved by external pull-up / pull-down resistors, which does not affect the input and output functions of the digital PAD, so the digital PAD can also be multiplexed into other modes, thereby expanding the application of the digital PAD.

[0050] The present invention is described above in conjunction with the best embodiment, but the present invention is not limited to the above disclosed embodiment, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A digital PAD multiplexing method for a SOC system, characterized in that: The steps include: a. Set the external connection of the digital PAD to have strong pull-up, strong pull-down or high impedance state, and widen the reset signal of the SOC system for k1 clock cycles, and widen the reset signal of the detection module for k2 clock cycles, and k2 <k1; b. After the SOC system is powered on and the detection module is reset, it starts timing n1 clock cycles and latches the first input value of the digital PAD into the first register; c. Switch the built-in pull-up / pull-down resistor of the digital PAD, start timing n2 clock cycles, and latch the second input value of the digital PAD into the second register; d. Confirm the operating mode of the SOC system through the two input values ​​latched by the first register and the second register; e. Release the permissions of the digital PAD.

2. The digital PAD multiplexing method for a SOC system according to claim 1, characterized in that: The digital PAD can be selectively connected to a strong pull-up resistor and a strong pull-down resistor, so that the external connection of the digital PAD has three states: strong pull-up, strong pull-down and high impedance.

3. The digital PAD multiplexing method for a SOC system according to claim 1, characterized in that: The built-in pull-up resistor of the digital PAD is a built-in weak pull-up resistor, the built-in pull-down resistor of the digital AD is a built-in weak pull-down resistor, and the built-in default of the digital PAD is a weak pull-up resistor or a weak pull-down resistor.

4. The digital PAD multiplexing method for a SOC system according to claim 1, characterized in that: The expansion time k1 of the reset signal of the SOC system, the expansion time k2 of the reset signal of the detection module, and the timing times n1 and n2 satisfy the relationship: k1>k2+n1+n2.

5. The digital PAD multiplexing method for a SOC system according to claim 1, characterized in that: When the built-in resistor of the digital PAD switches from pull-up to pull-down and from pull-down to pull-up, the values ​​latched in the first register and the second register are the same.

6. The digital PAD multiplexing method for a SOC system according to claim 4, characterized in that: The switching time of the built-in pull-up / pull-down resistor of the digital PAD is less than the sum of the reset signal widening time of the detection module and the first timing time. The switching time of the built-in pull-up / pull-down resistor of the digital PAD is recorded as k3 clock cycles. Then, k3 <k2+n1。

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