Loss leveling operations in memory devices

Abstract

The invention relates to wear leveling operations in memory devices. A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unavailable management unit (UMU) of a plurality of management units specified for wear leveling; storing a physical address and a logical address of the identified at least one UMU in a data structure; excluding the physical address of the identified at least one UMU from a physical address space for wear leveling; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a cyclic manner.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to wear leveling operations in memory devices. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] On the one hand, the present disclosure provides a system comprising: a memory device; and a processing device coupled to the memory device, the processing device being used to perform operations including: identifying at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the at least one identified UMU in a data structure; excluding the physical address of the at least one identified UMU from a physical address space used for wear leveling; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a round-robin manner.

[0004] On the other hand, the present disclosure provides a method, comprising: identifying, by a processing device, at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the identified at least one UMU in a data structure; excluding the physical address of the identified at least one UMU from a physical address space used for wear leveling; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a cyclic manner.

[0005] On the other hand, the present disclosure provides a non-temporary computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the at least one identified UMU in a data structure; excluding the physical address of the at least one identified UMU from a physical address space used for wear leveling; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a round-robin manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2A to 2B is a flow chart of an example method for performing start-gap wear leveling with unavailable management units in a memory device according to some embodiments of the present disclosure.

[0009] Figures 3A to 3E An example of an algorithm and architecture for modified start-gap loss leveling according to some embodiments of the present disclosure is described.

[0010] Figures 4A to 4B An example of performing modified start-gap loss leveling according to some embodiments of the present disclosure is described.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to start-gap wear leveling using unavailable management units in a memory device. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. In some embodiments, a memory subsystem may be a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request data to be retrieved from the memory subsystem.

[0013] The memory subsystem may include a high-density non-volatile memory device where it is desirable to retain data when power is not supplied to the memory device. An example of a non-volatile memory device is a NAND memory device, such as a 3D flash NAND memory, which provides storage in a compact, high-density configuration. Figure 1 Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may include one or more planes. For some types of nonvolatile memory devices (e.g., NAND memory devices), each plane includes a set of physical blocks. Each block includes a page. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state may be represented by a binary value, such as "0" and "1", or a combination of such values.

[0014] The memory device may include a plurality of memory cells arranged in a two-dimensional or three-dimensional grid. The memory cells are formed onto a silicon wafer in an array of columns and rows. The memory device may further include conductive lines connected to the respective ones of the memory cells, referred to as word lines and bit lines. A word line may refer to one or more rows of memory cells of the memory device, and a bit line may refer to one or more columns of memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. A block refers to a unit of a memory device for storing data, and may include a group of memory cells, a word line group, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of a memory device so as to allow concurrent operations to occur on each plane. The memory device may include a circuit system for performing concurrent memory page accesses of two or more memory planes. For example, a memory device may include a plurality of access line driver circuits and power circuits that may be shared by the planes of the memory device to facilitate concurrent access to pages of two or more memory planes including different page types.

[0015] Memory devices at a memory subsystem may have specific properties that present challenges in the operation of the memory subsystem. Some memory devices, such as non-volatile memory devices, have limited endurance. For example, some memory devices may be written, read, or erased a limited number of times before the memory device begins to physically degrade or wear out and ultimately fails.

[0016] The memory subsystem controller may perform media management operations to mitigate the effects of physical wear on the memory device and extend the overall life of the memory subsystem. For example, the memory subsystem controller may perform wear leveling operations to distribute physical wear across management units of the memory device. A management unit refers to a specific amount of memory of a memory device, such as a page or block. In order to perform wear leveling operations, the memory subsystem controller may identify a management unit at the memory device that is subject to a large amount of physical wear, and may move data stored at the management unit to another management unit that is subject to a smaller amount of physical wear. In some cases, if a large number of memory access operations, such as write operations (i.e., programming operations) or read operations, are performed at a management unit, then the management unit may be subject to a large amount of physical wear. Thus, in some embodiments, the memory subsystem controller may identify a management unit that is subject to a large amount of physical wear based on, for example, a write count for each management unit. A write count refers to the number of times the memory subsystem controller performs a write operation at a specific management unit during the life of the management unit. Data from a management unit with a high write count may be exchanged with data from a management unit with a low write count in an attempt to evenly distribute wear across the management units of the memory component.

[0017] In some embodiments, the memory subsystem controller can use a large table to track write counts and relocate data to any other location in the memory in an unconstrained manner. Large tables and undirected relocation may require large storage, thus causing latency overhead and increasing power consumption. These disadvantages can be overcome by implementing start-gap wear leveling, which uses the mapping between logical addresses and physical addresses in a limited address space to avoid tracking a large number of write counts. The controller can then perform wear leveling operations by periodically moving each management unit to its adjacent position, regardless of the write traffic to the management unit. The start-gap wear leveling operation uses two registers: a start register and a gap register, as well as additional memory management units to facilitate data movement. The controller can use the gap register to track the number of management units that have been moved. When all management units in the management unit pool designated for wear leveling operations have been moved, the controller can increment the start register to track the number of times all management units have been moved. The mapping of management units from logical addresses to physical addresses is completed by the operation of the gap and start register using the logical address, as explained below.

[0018] Specifically, the memory system designates a plurality of management units in a management unit pool for wear leveling operations, and each management unit corresponds to a physical address (e.g., 16 management units correspond to physical addresses 0 to 15). In order to implement start-gap wear leveling, an additional management unit is added at a location adjacent to the plurality of management units (e.g., a location corresponding to physical address 16). The total management units including the additional management unit (e.g., 16 management units plus one additional management unit) may form a circular pool. The additional management unit is a memory location that does not contain useful data. The start register and the gap register are initialized so that the start register will initially point to a location corresponding to a physical address (e.g., physical address 0), and the gap register that always points to the location of the additional management unit will initially point to a location corresponding to a physical address (e.g., physical address 16). After a predefined number of memory write operations are performed, the content of the location referenced by the gap register is decremented by one (e.g., a location corresponding to physical address 15) and is copied to the location of the additional management unit (e.g., a location corresponding to physical address 16). That is, the content is moved to an adjacent location. The value stored by the gap register is then decremented so that it will reference the adjacent location, which after the contents are moved will be the location identified by the physical address immediately preceding the physical address in the address range (e.g., physical address 15). After the number of moves of the gap register reaches the number of management units in the pool of management units used for the wear leveling operation (e.g., 16 moves), the gap register wraps around the address range (e.g., points to physical address 0). For the next data move, the gap register is reset to the initial address of the range (e.g., points to physical address 16), and since the contents of all (e.g., 16) management units in the pool have been moved once, the start register is incremented by one. Thus, each move of the gap register provides a remapping of the contents (specific to a logical address) to its adjacent location (corresponding to a physical address).

[0019] However, this wear leveling scheme cannot exclude management units that have been deemed unavailable for storing data but are still used for wear leveling. Since management units are cycled to move data, data will be stored using unavailable management units. Eventually, the data stored at the management units becomes unreliable. Unavailable management units used in start-gap wear leveling may reduce overall efficiency and increase overall latency of the memory subsystem.

[0020] Aspects of the present disclosure address the above and other deficiencies by enabling a controller to exclude unusable management units from the address space used in start-gap wear leveling. A management unit refers to a group of memory cells, such as a data block or page that can be managed for wear leveling. An unusable management unit (UMU) refers to a management unit that is found to be unsuitable for data storage and therefore should no longer be used for wear leveling. The address space used in start-gap wear leveling (referred to as a wear leveling pool) refers to the addresses of the management units used in start-gap wear leveling and may include: a logical address space, which includes the logical addresses of the management units used in start-gap wear leveling; and a physical address space, which includes the physical addresses of the management units used in start-gap wear leveling.

[0021] The controller may manage the dynamic reduction of the wear leveling pool. The memory subsystem controller may identify one or more UMUs during a wear leveling operation. For example, after performing a predefined number of memory write operations, the memory subsystem controller moves data for wear leveling, which may be referred to as a step of a wear leveling operation, and the memory subsystem controller may identify one or more UMUs before, during, or after the step of a wear leveling operation. The memory subsystem controller may maintain a record of all identified UMUs so that the host system may access the record in order to identify the UMUs. For example, the memory subsystem controller may store the physical address and logical address of the UMU in a data structure (e.g., a logical to physical (L2P) table) comprising multiple records, so that each record maps the physical address of the UMU to a logical address. The memory subsystem controller may remove the location corresponding to the identified UMU from the wear leveling pool, i.e., exclude the address of the UMU from the address space used in start-gap wear leveling.

[0022] Using the dynamically reduced wear leveling pool, the memory subsystem controller can use the modified address space and the modified registers to perform start-gap wear leveling. In one example, the memory subsystem controller specifies a set of management units in the wear leveling pool, and each management unit corresponds to a physical address (e.g., N number of management units each correspond to physical addresses 0 to N-1). To implement start-gap wear leveling, an additional management unit that does not contain useful data is added at a location adjacent to the set of management units (e.g., a location corresponding to physical address N). During the wear leveling operation (e.g., a time after performing a predefined number of memory write operations), the memory subsystem controller identifies one or more (e.g., M) UMUs and deletes the identified UMUs from the wear leveling pool. The size of the reduced wear leveling pool becomes the number of management units minus the number of identified UMUs (e.g., NM), and the total management units including the additional management units (e.g., N+1-M management units) can form a recycling pool. The memory subsystem controller introduces a first function, which refers to a function that translates items from the original address space to the reduced address space. The memory subsystem controller uses the first function to translate the logical address in the address space (e.g., N management units) into the modified logical address in the reduced address space (e.g., NM management units). The memory subsystem controller also uses the first function to translate the values ​​of the start register and the gap register into the modified start register value and the modified gap register value, respectively.

[0023] When a predetermined number of memory write operations are performed, the memory subsystem controller identifies an adjacent position that does not correspond to a UMU (e.g., the nearest adjacent position along the moving direction of the gap register), and the memory subsystem controller copies the content of the identified adjacent position to the position of the additional management unit. Specifically, the memory subsystem controller determines whether the position decremented by one referenced by the modified gap register corresponds to the UMU. In response to determining that the position decremented by one referenced by the modified gap register does not correspond to the UMU, the memory subsystem controller copies the content of the position decremented by one referenced by the modified gap register to the position of the additional management unit, and the modified gap register value is decremented by one, that is, pointing to the position moved by one. Conversely, in response to determining that the position decremented by one referenced by the modified gap register corresponds to the UMU, and assuming that the position decremented by two referenced by the modified gap register does not correspond to the UMU, the memory subsystem controller then copies the content of the position decremented by two referenced by the modified gap register to the position of the additional management unit, and the modified gap register is decremented by two, that is, pointing to the position moved by two.

[0024] After the number of moves of the modified gap register reaches the number of management units in the reduced wear leveling pool (e.g., NM management units), the modified gap register wraps around the address range (e.g., points to a location corresponding to the first position in the recycle pool). For the next data move, the modified gap register is reset to the initial address of the range (e.g., points to a location corresponding to the last position in the recycle pool), and because the contents of the management units in the reduced wear leveling pool (e.g., NM management units) have been moved once, the modified start register is incremented by one. Thus, each move of the modified gap register provides a remapping of the contents (specific to a logical address) to its non-UMU adjacent location (corresponding to a physical address).

[0025] In the above example, if the memory subsystem controller determines that the position referenced by the modified gap register, which is decremented by two, corresponds to a UMU, then the memory subsystem controller will continue to look for the nearest neighboring position that does not correspond to a UMU, for example, the position referenced by the modified gap register, which is decremented by X. The controller then copies the contents of the position referenced by the modified gap register, which is decremented by X, to the location of the additional management unit, and the modified gap register is decremented by X, i.e., points to the position of the move X.

[0026] The memory subsystem controller may then introduce a second function, which refers to a function that translates items from the reduced address space to the original address space. The memory subsystem processor uses the second function to translate the modified physical address in the reduced address space (e.g., NM management units) to a logical address in the original address space (e.g., N management units). Thus, the memory subsystem controller performs modified start-gap wear leveling while excluding the UMU from the wear leveling pool.

[0027] Advantages of the present disclosure include, but are not limited to, increasing the overall life of a memory subsystem by performing wear leveling management operations on the memory subsystem. By excluding the UMU from the address space used for start-gap wear leveling, the memory subsystem controller improves the reliability of data stored after wear leveling is performed. As a result, the number of unnecessary wear leveling for management units at the memory device is reduced, which increases the amount of system resources available for other processes. The increase in available system resources leads to an increase in overall subsystem efficiency and a reduction in overall subsystem latency. Aspects of the present disclosure can be applied to emerging memory devices, not just traditional memory devices.

[0028] Figure 1An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0032] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0033] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages that may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0037] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0039] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0040] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] The memory subsystem 110 includes a wear leveling management component 113 that manages the execution of wear leveling operations of the memory devices 130, 140 during operation of the memory subsystem 110. The wear leveling management component 113 can facilitate the execution of modified start-gap wear leveling operations at management units (e.g., blocks, pages, etc.) at the memory devices 130 and 140. In some embodiments, the memory subsystem controller 115 includes at least a portion of the wear leveling component 113. In some embodiments, the wear leveling management component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the wear leveling management component 113 and is configured to perform the functionality described herein. Additional details regarding the operation of the wear leveling management component 113 are described below.

[0045] Figure 2A 2 is a flow chart of an example method 200A for performing a start-gap wear leveling operation with a UMU in a memory device according to some embodiments of the present disclosure. The method 200A may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200A is performed by Figure 1 The wear leveling management component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0046] At operation 210A, processing logic identifies one or more UMUs of a plurality of management units that are designated for wear leveling. In some embodiments, processing logic may identify the one or more UMUs by determining that an endurance metric (e.g., error rate, program / erase cycles) of the one or more management units satisfies a threshold criterion and identifying the management unit as a UMU. In some embodiments, processing logic may determine that one or more management units that have been used for wear leveling become unusable, e.g., have an error rate or program / erase cycle count that exceeds a predetermined threshold, and identify them as UMUs. In some embodiments, processing logic may determine that one or more management units that have been used for wear leveling are not suitable for use in wear leveling, and identify them as UMUs.

[0047] At operation 220A, the processing logic stores the physical address and the logical address of the identified UMU in the L2P table of the UMU. The L2P table of the UMU refers to a table for mapping the logical address of the UMU (recognizable by the host computing system) to the physical address (recognizable by the memory device), and each entry in the L2P table of the UMU includes the logical address and the physical address of the UMU.

[0048] At operation 230A, processing logic removes the physical address of the identified UMU from the wear-leveled physical address space to obtain a modified physical address space for wear leveling. The wear-leveled physical address space includes all physical addresses used for wear leveling, and after processing logic removes the physical address of the UMU, processing logic obtains a modified physical address space excluding the UMU.

[0049] At operation 240A, processing logic performs a start-gap wear leveling operation with the modified physical address space. Figure 2B Details of performing a start-gap wear-leveling operation with a modified physical address space are described.

[0050] Figure 2B 2 is a flow chart of an example method 200B for performing a start-gap wear leveling operation with a modified physical address space according to some embodiments of the present disclosure. The method 200B may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200B is performed by Figure 1 The wear leveling management component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments.

[0051] At operation 210B, processing logic determines that the logical address does not correspond to a UMU in a plurality of management units for wear leveling. In some implementations, processing logic may search in an L2P table of the UMU and determine whether any entry for the logical address matches the logical address, and in response to determining that there is no match, determine that the logical address does not correspond to a UMU in a management unit for wear leveling.

[0052] At operation 220B, processing logic uses the first function to translate the logical address into a modified logical address. Figure 3C An example of a first function is described. In some implementations, processing logic uses a start-gap wear leveling technique including a first register - a gap register and a second register - a start register, and processing logic uses the first function to translate the first register into a modified first register and the second register into a modified second register.

[0053] At operation 230B, the processing logic maps the modified logical address to the modified physical address using the modified first register and the modified second register, and uses the modified first register and the modified second register by modifying the value stored in the modified first register in a cyclic manner and modifying the value stored in the modified second register in a cyclic manner. Mapping the modified logical address to the modified physical address means that the content stored in the management unit identified by the modified logical address is now moved to the management unit identified by the modified physical address. That is, the data stored in the management unit is moved to the non-UMU adjacent management unit, and the non-UMU management units form a pool for wear leveling in a cyclic manner. For example, after data stored in a first non-UMU management unit in a pool is moved to a second non-UMU management unit for wear leveling operation, for the next move, data stored in a last non-UMU management unit in the pool is moved to the first non-UMU management unit for wear leveling operation, and the process continues, i.e., data stored in the second last non-UMU management unit in the pool is moved to the last non-UMU management unit for wear leveling operation, until data stored in a first non-UMU management unit in the pool is moved to a second non-UMU management unit for wear leveling operation again. Thus, data of management units are moved to non-UMU adjacent management units in a cyclic manner.

[0054] Data movement is facilitated by modifying the value stored in the modified first register in a cyclic manner and modifying the value stored in the modified second register in a cyclic manner. In one embodiment, the value stored in the modified first register is decremented after each data movement, and the value continues to decrement until the value reaches zero and is reset to its maximum value. The value stored in the modified second register is incremented when the number of data moves reaches the number of useful management units for wear leveling (i.e., the number of management units excluding UMUs), and the value continues to increase until the value reaches its maximum value and is reset to zero. Thus, the processing logic updates the values ​​stored in the modified first register and the modified second register. The updated values ​​stored in the modified first register and the modified second register will be used in the next step of the wear leveling operation. Figure 3A An example of mapping using a modified first register and a modified second register in a round-robin manner is described.

[0055] At operation 240B, processing logic uses the second function to translate the modified physical address into a physical address. Figure 3D An example of the second function is described.

[0056] Figures 3A to 3E An example of an algorithm and architecture for modified start-gap wear leveling according to some embodiments of the present disclosure is described. L represents a logical address in an address space including a UMU. P represents a physical address in an address space including a UMU. L1 represents a logical address in an address space excluding a UMU, which may be a modified logical address from an original logical address. P represents a physical address in an address space excluding a UMU, which may be a modified physical address from an original physical address. G represents a gap register in start-gap wear leveling for an address space including a UMU. S represents a start register in start-gap wear leveling for an address space including a UMU. G1 represents a gap register in start-gap wear leveling for an address space excluding a UMU. S1 represents a start register in start-gap wear leveling for an address space excluding a UMU. N represents the number of management units in start-gap wear leveling for an address space including a UMU. N1 represents the number of management units in start-gap wear leveling for an address space excluding a UMU.

[0057] refer to Figures 3A to 3B, if the logical address (L) corresponds to the UMU logical address (Hole_L), the memory subsystem controller obtains the physical address (P) as the UMU physical address (Hole_P) by searching in the UMU L2P table based on the UMU logical address (Hole_L). If the logical address (L) does not correspond to the UMU logical address (Hole_L), the memory subsystem controller translates the logical address (L) into a modified logical address (L1) using a first function (ord), translates the modified logical address (L1) into a modified physical address (P1) using start-gap wear leveling, and translates the modified physical address (P1) into a physical address (P) using a second function (dro). Figure 3C An example of the first function (ord) is given, and Figure 3D An example of a second function (dro) is described, where the second function is the inverse function of the first function. Figure 3E The following describes the circular movement of the gap register and the circular movement of the start register under the modified address space. Figures 4A to 4B Details of using these algorithms to perform modified start-gap wear leveling are described.

[0058] Figures 4A to 4B An example of performing modified start-gap loss equalization according to some embodiments of the present disclosure is illustrated. Each graph 400A, 400B illustrates the process and result of performing modified start-gap loss equalization. Figure 4A , the top row 410A represents physical locations identifiable by physical addresses, and includes 17 locations, namely, location 0 to location 16; the left column 420A represents the steps of the modified start-gap wear leveling, where each step corresponds to a shift of the content in the management unit and a movement of the gap register, and includes 25 wear leveling steps. The intersection of the physical location and the wear leveling step represents the content stored in the management unit, where the content can be referenced by the logical address. Because the association of content and logical address will not change during wear leveling, the graph 400A uses logical addresses to represent the stored content, which can better illustrate the mapping of physical addresses and logical addresses provided by the modified start-gap wear leveling.

[0059] At wear leveling step 1, the start register (represented by S) starts by pointing to physical location 3, which corresponds to logical address 0. The gap register (represented by G) starts by pointing to physical location 9, and the memory subsystem controller swaps the content stored at physical location 9 (represented by logical address -1) with the content stored at physical location 8 (represented by logical address 5). Logical address -1 may indicate that no useful data corresponding to the logical address is stored. The gap register is then decremented by one physical position. Therefore, after wear leveling step 1, the gap register points to physical location 8, which stores the content represented by logical address -1, and physical location 9 stores the content represented by logical address 5. At wear leveling step 2, the gap register starts by pointing to physical location 8, and the memory subsystem controller swaps the content stored at physical location 8 (represented by logical address -1) with the content stored at physical location 7 (represented by logical address 4), and the gap register is then decremented by one physical position to point to physical location 7.

[0060] The process continues as described above, and at wear leveling step 7, the memory subsystem controller identifies the management unit as the UMU, and identifies the physical location of the UMU as physical location 12 through the physical address. The subsystem controller can exclude the UMU from the physical location, i.e., the physical location now becomes 16 locations (locations 0 to 11 and 13 to 16). At wear leveling step 7, the gap register starts by pointing to physical location 3, and the memory subsystem controller swaps the content stored at physical location 3 (represented by "logical address -1") with the content stored at physical location 2 (represented by "logical address 15"), and the gap register is then decremented by one physical location to point to physical location 2. In addition, at wear leveling step 7, the start register is incremented and moved to point to physical location 4, because the contents of all management units within the physical location have been swapped once.

[0061] The process continues as described above, where at wear leveling step 10, the gap register starts by pointing to physical location 0, and the memory subsystem controller swaps the contents stored at physical location 0 (represented by "logical address -1") with the contents stored at physical location 16 (represented by "logical address 12"), and the gap register is then wrapped around and reset in a circular manner to the other end position of the pool to point to physical location 16.

[0062] The process continues as described above, and at the wear leveling step 12, the memory subsystem controller identifies the management unit as the UMU, and identifies the physical location of the UMU as physical location 5 through the physical address. The subsystem controller can exclude the UMU from the physical location, that is, the physical location now becomes 15 locations (locations 0 to 4, 6 to 11, and 13 to 16). At the wear leveling step 12, the gap register starts by pointing to physical location 15, and the memory subsystem controller swaps the content stored at physical location 15 (represented by "logical address -1") with the content stored at physical location 14 (represented by "logical address 10"), and the gap register is then decremented by one physical location to point to physical location 14.

[0063] The process continues as described above, and at the wear leveling step 14, the gap register starts by pointing to physical location 13, and the memory subsystem controller swaps the contents stored at physical location 13 (represented by "logical address -1") with the contents stored at physical location 11 (represented by "logical address 7") since physical location 12 has been excluded, and the gap register is then decremented by one physical position to point to physical location 11.

[0064] At the wear leveling step 15, the memory subsystem controller identifies the management unit as the UMU, and identifies the physical location of the UMU as physical location 8 through the physical address. The subsystem controller can exclude the UMU from the physical location, that is, the physical location now becomes 14 locations (locations 0 to 4, 6 to 7, 9 to 11, and 13 to 16). At the wear leveling step 12, the gap register starts pointing to the physical location, and the memory subsystem controller swaps the content stored at physical location 15 (represented by "logical address -1") with the content stored at physical location 14 (represented by "logical address 10"), and the gap register is then decremented by one physical location to point to physical location 14.

[0065] The process continues as described above, and at the wear leveling step 17, the gap register begins pointing to physical location 9, and the memory subsystem controller swaps the contents stored at physical location 9 (represented by "logical address -1") with the contents stored at physical location 7 (represented by "logical address 3") because physical location 8 has been excluded, and the gap register is then decremented by one physical position to point to physical location 7.

[0066] The process continues as described above, and at wear leveling step 19, the gap register starts by pointing to physical location 6, and the memory subsystem controller swaps the content stored at physical location 6 (represented by "logical address -1") with the content stored at physical location 4 (represented by "logical address 0"), since physical location 5 has been excluded, and the gap register is then decremented by one physical location to point to physical location 4. At wear leveling step 20, the start register is incremented and moved to point to physical location 6, since the contents of all management units within the physical locations have been swapped once, and physical location 5 has been excluded. Figure 4A , the process continues to the wear leveling step 25 as described above.

[0067] refer to Figure 4B , the top row 410B represents physical locations identifiable by physical addresses, and includes 9 locations, namely, location 0 to location 8; the left column 420B represents the steps of the modified start-gap wear leveling, where each step corresponds to a shift of the content in the management unit and a movement of the gap register, and includes 20 wear leveling steps. The intersection of the physical location and the wear leveling step represents the content stored in the management unit, where the content can be referenced by the logical address. Because the association of content and logical address will not change during wear leveling, the graph 400B uses logical addresses to represent the stored content, which can better illustrate the mapping of physical addresses and logical addresses provided by the modified start-gap wear leveling.

[0068] At wear leveling step 1, the start register (represented by S) starts by pointing to physical location 1, which corresponds to logical address 0. The gap register (represented by G) starts by pointing to physical location 5, and the memory subsystem controller swaps the content stored at physical location 5 (represented by logical address -1) with the content stored at physical location 4 (represented by logical address 3). Logical address -1 may indicate that no useful data corresponding to the logical address is stored. The gap register is then decremented by one physical location. Therefore, after wear leveling step 1, the gap register points to physical location 4, which stores the content represented by logical address -1, and physical location 5 stores the content represented by logical address 3. At wear leveling step 2, the gap register starts by pointing to physical location 4, and the memory subsystem controller swaps the content stored at physical location 4 (represented by logical address -1) with the content stored at physical location 3 (represented by logical address 2), and the gap register is then decremented by one physical location to point to physical location 3.

[0069] The process continues as described above, and at wear leveling step 4, the gap register starts by pointing to physical location 0, and the memory subsystem controller swaps the content stored at physical location 2 (represented by "logical address -1") with the content stored at physical location 1 (represented by "logical address 0"), and the gap register is then rotated one physical position to point to physical location 1. The start register is also changed to point to physical location 2.

[0070] The process continues as described above, and at wear leveling step 6, the memory subsystem controller identifies the two management units as UMUs, and identifies the physical locations of the UMUs as physical locations 2 and 4 through the physical addresses. The subsystem controller may exclude the UMUs from the physical locations, i.e., the physical locations now become 7 locations (locations 0 to 1, 3, and 5 to 8). At wear leveling step 6, the gap register starts by pointing to physical location 0, and the memory subsystem controller swaps the content stored at physical location 0 (represented by logical address -1) with the content stored at physical location 8 (represented by logical address 6), and the gap register is then wrapped around and reset in a circular manner to point to physical location 8. Furthermore, at wear leveling step 6, the start register still points to physical location 2. Then, at wear leveling step 7, the start register is incremented and moved to point to physical location 3, because physical location 2 has been excluded.

[0071] The process continues as described above, and at the wear leveling step 10, the gap register begins by pointing to physical location 5, and the memory subsystem controller swaps the contents stored at physical location 5 (represented by "logical address -1") with the contents stored at physical location 3 (represented by "logical address 1") since physical location 4 has been excluded, and the gap register is then decremented by two physical locations to point to physical location 3.

[0072] At the wear leveling step 11, the gap register starts by pointing to physical location 3, and the memory subsystem controller swaps the content stored at physical location 3 (represented by "logical address -1") with the content stored at physical location 1 (represented by "logical address 7"), because physical location 2 has been excluded, and the gap register is then decremented by two physical locations to point to physical location 1. In addition, at the wear leveling step 11, the start register is incremented and moved to point to physical location 5, because the contents of all management units within the physical location have been swapped once, and physical location 4 has been excluded. Figure 4A , the process continues to the wear leveling step 20 as described above.

[0073] As in Figure 4B, the right column 490B indicates the number of locations where the content changes at each step of wear leveling. Thus, the number at wear leveling step 1 is zero because no content changes in step 1, and the number at wear leveling steps thereafter is two because the content of only two locations changes. The numbers in the right column 490B are used to check whether each wear leveling step is performed correctly.

[0074] Figure 5 An example machine illustrating a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The computer may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0077] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0078] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 526 by the computer system 500, the instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502, which also constitute machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instructions 526 include instructions to implement a method corresponding to a media management component (e.g., Figure 1 The functionality of the wear leveling management component 113 of the present disclosure is provided. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into physical quantities similarly represented as within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; and A processing device coupled to the memory device, the processing device being configured to perform operations comprising: identifying at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the identified at least one UMU in a data structure; excluding the physical address of the identified at least one UMU from a physical address space used for wear leveling; as well as A wear leveling operation is performed using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a round-robin manner. 2 . The system of claim 1 , wherein identifying the at least one UMU further comprises determining that a value of a durability metric measured at at least one of the plurality of management units satisfies a threshold criterion.

3. The system of claim 1, wherein the data structure comprises a plurality of records, and wherein each record of the plurality of records maps a physical address of a UMU to a logical address.

4. The system of claim 1 , wherein using the physical address space to perform the wear leveling operation further comprises: translating the target logical address into a modified logical address using a first function; mapping the modified logical address to a modified physical address; as well as The modified physical address is translated into a target physical address using a second function.

5. The system of claim 4, wherein using the physical address space to perform the wear leveling operation further comprises: It is determined that the target logical address does not correspond to a logical address of a UMU in the data structure.

6. The system of claim 4, wherein mapping the modified logical address to the modified physical address further comprises: Content stored in the management unit corresponding to the modified logical address is copied to the management unit corresponding to the modified physical address.

7. The system of claim 4, wherein using the physical address space to perform the wear leveling operation further comprises: using a value stored in a modified first register referencing a neighboring management unit corresponding to the modified logical address; as well as In response to mapping the modified logical address to the modified physical address, the modified first register is decremented in a circular manner.

8. The system of claim 4, wherein using the physical address space to perform the wear leveling operation further comprises: using the value stored in the modified second register; as well as In response to mapping the plurality of modified logical addresses to the plurality of modified physical addresses in the modified physical address space, the modified second register is incremented in a circular manner.

9. The system of claim 4, wherein performing the wear leveling operation using the modified physical address space is in response to a number of write operations performed in the memory device satisfying a threshold.

10. The system of claim 4, wherein the second function is an inverse function of the first function.

11. A method comprising: Identifying, by a processing device, at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the identified at least one UMU in a data structure; excluding the physical address of the identified at least one UMU from a physical address space used for wear leveling; as well as A wear leveling operation is performed using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a round-robin manner.

12. The method of claim 11, wherein identifying the at least one UMU further comprises determining that a value of a durability metric measured at at least one of the plurality of management units satisfies a threshold criterion.

13. The method of claim 11, wherein the data structure comprises a plurality of records, and wherein each record of the plurality of records maps a physical address of a UMU to a logical address.

14. The method of claim 11, wherein using the physical address space to perform the wear leveling operation further comprises: translating the target logical address into a modified logical address using a first function; mapping the modified logical address to a modified physical address; as well as The modified physical address is translated into a target physical address using a second function.

15. The method of claim 14, wherein using the physical address space to perform the wear leveling operation further comprises: It is determined that the target logical address does not correspond to a logical address of a UMU in the data structure.

16. The method of claim 14, wherein mapping the modified logical address to the modified physical address further comprises: Content stored in the management unit corresponding to the modified logical address is copied to the management unit corresponding to the modified physical address.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying at least one unavailable management unit (UMU) among a plurality of management units designated for wear leveling; storing a physical address and a logical address of the identified at least one UMU in a data structure; excluding the physical address of the identified at least one UMU from a physical address space used for wear leveling; as well as A wear leveling operation is performed using the physical address space, wherein the wear leveling operation moves data of a management unit to an adjacent management unit in a round-robin manner.

18. The non-transitory computer-readable storage medium of claim 17, wherein identifying the at least one UMU further comprises determining that a value of a durability metric measured at at least one of the plurality of management units satisfies a threshold criterion.

19. The non-transitory computer-readable storage medium of claim 17, wherein the data structure comprises a plurality of records, and wherein each record of the plurality of records maps a physical address of a UMU to a logical address.

20. The non-transitory computer-readable storage medium of claim 17, wherein using the physical address space to perform the wear leveling operation further comprises: translating the target logical address into a modified logical address using a first function; mapping the modified logical address to a modified physical address; as well as The modified physical address is translated into a target physical address using a second function.

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