Adder, data operation method, memory and electronic equipment

Abstract

The invention relates to an adder, a data operation method, a memory and electronic equipment, and belongs to the field of electronic circuits. The adder comprises a control module and a plurality of operation modules, wherein each operation module comprises a first latch, a second latch and a first selection circuit; the first latch is used for storing a carry value obtained by adding the addend and the addend; the second latch is used for storing an addition value obtained by adding the addend and the addend under the condition that carry is ignored; the first output end of the second latch outputs an added value, and the second output end of the second latch outputs an opposite value of the added value; and the control module is used for controlling all the first selection circuits from the first operation module to the second operation module to output the value of the second output end of the second latch, and controlling all the first selection circuits in the other operation modules to output the value of the first output end of the second latch to obtain a final addition result. The problem that an existing full adder is low in operation speed can be solved.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to an adder and a data operation method, a memory and an electronic device. Background Art

[0002] Since adders are widely used in chip design, adders have always been the focus of research. Through continuous optimization of algorithms, architectures, etc., the indicators of adders (such as area and / or speed) are now facing design limits.

[0003] Common adders include full adders. Although the operation logic of full adders is simple, the ripple delay is large, especially when the number of addends or augends is large. The ripple delay refers to the delay caused by the step-by-step transmission of the carry signal from the lowest bit to the highest bit in the adder. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an adder and a data operation method, a memory and an electronic device to improve the problem of slow operation speed of the existing full adder.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides an adder, comprising: a control module and multiple operation modules, each operation module comprising a first latch, a second latch, and a first selection circuit; the first output end and the second output end of the second latch are both connected to the first selection circuit; the first latch is used to store the carry value of the addend and the addend; the second latch is used to store the added value of the addend and the addend when the carry is ignored; wherein the first output end of the second latch outputs the added value, and the second output end of the second latch outputs the opposite value of the added value; the control module is used to control all the first selection circuits in the first operation module to the second operation module to output the value of the second output end of the second latch, and control all the first selection circuits in the remaining operation modules to output the value of the first output end of the second latch to obtain the final addition result; wherein the first operation module is the next operation module of the operation module with a carry value of 1; the second operation module is the first operation module located after the operation module with a carry value of 1 and with an added value of 0.

[0007] In the above embodiment, the adder with the above structure is used, so that when performing addition operation, the first latch is used to store the carry value of the addend and the addend, and the second latch is used to store the added value of the addend and the addend when the carry is ignored (or not considered), and then the control module is used to control the operation module to output the correct value, so as to obtain the final addition result. Since the above adder performs the addition operation based on the two-step operation method, that is, the initial addition result of the direct addition of the addend and the addend when the carry is ignored is first obtained (the added values ​​stored in multiple second latches are combined to form the initial addition result), and then the added values ​​between the starting point added value (corresponding to the added value in the first operation module) and the end point added value (corresponding to the added value in the second operation module) and the two end points in the initial addition result are flipped (output from the second output end of the second latch), and the remaining added values ​​are not flipped (output from the first output end of the second latch), so as to obtain the final addition result, thereby greatly improving the operation speed.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, each operation module also includes: a second selection circuit and a third selection circuit, the first output end and the second output end of the first latch are connected to the second selection circuit, and the second selection circuit is also connected to the first input end of the second latch; the first output end and the second output end of the first latch are connected to the third selection circuit, and the third selection circuit is also connected to the second input end of the second latch; the first latch is also used to store first data; the second selection circuit and the third selection circuit are controlled by second data; wherein the first data is an addend and the second data is an addend, or the first data is an addend and the second data is an addend.

[0009] In the above embodiment, by adding a second selection circuit and a third selection circuit and using the second data to control the second selection circuit and the third selection circuit, the addition of the addend and the augend in the case of ignoring the carry can be indirectly realized, and the added value of the addend and the augend in the case of ignoring the carry is stored in the second latch, which greatly improves the calculation efficiency and simplifies the circuit structure.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the second selection circuit and the third selection circuit both include: a first switch and a second switch, the control signal of the first switch and the control signal of the second switch being opposite; the first output end of the first latch is connected to the first input end of the second latch through the first switch, and the second output end of the first latch is connected to the first input end of the second latch through the second switch; the first output end of the first latch is connected to the second input end of the second latch through the second switch, and the second output end of the first latch is connected to the second input end of the second latch through the first switch.

[0011] In the above embodiment, by using a low-cost and small-area switch as a selection device, the cost and area of ​​the circuit can be reduced while indirectly realizing the addition of the addend and the augend when the carry is ignored, and storing the added value of the addend and the augend when the carry is ignored in the second latch.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the second selection circuit and the third selection circuit both include: a selector, the first output terminal and the second output terminal of the first latch are both connected to the first input terminal of the second latch through one of the selectors; the first output terminal and the second output terminal of the first latch are both connected to the second input terminal of the second latch through another of the selectors.

[0013] In the above embodiment, by using a low-cost selector as a selection device, the cost of the circuit can be reduced while the addition of the addend and the augend when the carry is ignored is indirectly achieved, and the added value of the addend and the augend when the carry is ignored is stored in the second latch, and the control logic of the circuit can be simplified.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, each operation module also includes: a write control module, the write control module is connected to the first input end and the second input end of the first latch; the write control module is used to write the carry value of the addition of the addend and the addend into the first latch.

[0015] In the above embodiment, a write control module is added to write the carry value of the addend and the augend into the first latch, so that the control module can accurately control the flipping of the operation module according to the carry value to ensure the accuracy of the addition operation.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, each operation module also includes: a carry acquisition circuit, which is connected to the write control module; the carry acquisition circuit is used to obtain the carry value of the addition of the addend and the addend according to the addend and the addend, and send the carry value to the write control module.

[0017] In the above embodiment, a carry acquisition circuit is added to acquire the carry value of the addition of the addend and the augend, and the carry value is sent to the write control module, so that the write control module can accurately write the carry value.

[0018] In combination with a possible implementation manner of the first aspect embodiment, the control module includes: a plurality of control units corresponding one-to-one to the plurality of operation modules; each control unit includes: a carry value control branch, an addition value control branch and a transmission control line; the transmission control line is respectively connected to the carry value control branch, the addition value control branch and the first selection circuit, and the transmission control lines in each control unit are connected in sequence; the carry value control branch is used to control the level of the transmission control line according to the carry value; the addition value control branch is used to control whether the transmission control line in which it is located is connected to the transmission control line in the next control unit according to the addition value; the carry value of the carry value control branch in the first control unit is a default value, and the carry values ​​of the carry control branches from the second control unit to the last control unit are the carry values ​​in the first latch corresponding to the previous control unit.

[0019] In the above embodiment, the control module using the above hardware circuit structure, since each operation module corresponds to its own control unit, precise control can be performed when controlling the data flipping of the operation module; at the same time, the structure of each control unit is the same, which is conducive to reducing the design difficulty, and since the carry value of the carry control branch from the second control unit to the last control unit is the carry value in the first latch corresponding to the previous control unit, it is conducive to expansion.

[0020] In combination with a possible implementation manner of the embodiment of the first aspect, the adder is an in-memory adder, and the first latch and the second latch are latches in a memory.

[0021] In the above embodiment, by integrating the adder in the memory and reusing the existing latches in the memory, the circuit area can be further reduced, and the data inside the memory array can be directly read for addition operations, which reduces the time for data transfer and further improves the efficiency of data operations.

[0022] In a second aspect, an embodiment of the present application further provides a memory, comprising: a memory read circuit and an adder provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment, the memory read circuit comprising: a plurality of storage units, a plurality of sensitive amplifiers and a plurality of output circuits; each storage unit corresponds to a sensitive amplifier and an output circuit; the first latch in the adder is the latch in the sensitive amplifier, and the second latch is the latch in the output circuit.

[0023] In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory provided in the embodiment of the second aspect described above.

[0024] In a fourth aspect, an embodiment of the present application also provides a data calculation method for an adder, which is applied to an adder, and the method includes: obtaining an initial addition result of the addend and the addend when the carry is ignored; according to the carry value of the addend and the addend, flipping the addition values ​​between the starting point addition value and the end point addition value and the end points in the initial addition result, and not flipping the remaining addition values, to obtain a final addition result; wherein the starting point addition value is the next bit addition value with a carry value of 1 in the initial addition result, and the end point addition value is the first bit addition value with a value of 0 after the addition value with a carry value of 1 in the initial addition result.

[0025] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0027] Figure 1a A first principle schematic diagram of data operation of an adder provided in an embodiment of the present application is shown.

[0028] Figure 1b A second principle schematic diagram of data operation of the adder provided in an embodiment of the present application is shown.

[0029] Figure 1c A third principle schematic diagram of data operation of the adder provided in an embodiment of the present application is shown.

[0030] Figure 2A schematic diagram of the structure of an adder provided in an embodiment of the present application is shown.

[0031] Figure 3 A schematic diagram of the structure of a computing module provided in an embodiment of the present application is shown.

[0032] Figure 4 A schematic diagram showing the principle of a computing module provided in an embodiment of the present application is shown.

[0033] Figure 5 A structural schematic diagram of another operation module provided in an embodiment of the present application is shown.

[0034] Figure 6 A schematic structural diagram showing a control unit connected to a computing module provided in an embodiment of the present application is shown.

[0035] Figure 7 A schematic diagram showing the principle of connecting a control unit and a computing module provided in an embodiment of the present application is shown.

[0036] Figure 8 A schematic diagram showing the principle of connecting another control unit and a computing module provided in an embodiment of the present application is shown.

[0037] Fig. 9 A schematic diagram of the principle of a storage unit provided in an embodiment of the present application is shown.

[0038] Fig.10 A schematic diagram of the principle of a memory read circuit provided in an embodiment of the present application is shown.

[0039] Fig.11 A schematic diagram showing the principle of a latch in an output circuit provided in an embodiment of the present application is shown.

[0040] Fig.12 A schematic diagram of the principle of an improved memory read circuit provided in an embodiment of the present application is shown.

[0041] Fig.13 A schematic flow chart of a data operation method of an adder provided in an embodiment of the present application is shown.

[0042] Fig.14 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0044] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0045] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0046] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0047] In order to improve the problem of slow operation speed of the full adder, an embodiment of the present application provides an adder, which can obtain the addition result by using a two-step operation algorithm, thereby greatly improving the operation speed.

[0048] The data operation principle of the adder provided in the embodiment of the present application is introduced below. When calculating the addition result of the addend and the addend, the initial addition result of the addend and the addend directly added when the carry is ignored can be obtained first. Then, based on the carry value of the addend and the addend, the addition values ​​between the starting point addition value and the end point addition value and the two end points in the initial addition result are flipped, and the remaining addition values ​​are not flipped, so as to obtain the final addition result. Among them, the starting point addition value is the next addition value with a carry value of 1 (flip starting point); the end point addition value is the first addition value with a value of 0 after the addition value with a carry value of 1 (flip end point). The flip starting point can be equal to the flip end point.

[0049] To better illustrate the above flipping principle: flip the initial addition result between the starting point and the end point, and the addition values ​​at both ends, and do not flip the remaining addition values. Figure 1a , Figure 1b , Figure 1c To explain, Figure 1a , Figure 1b Take the addition operation of 1 Byte (8 bits) as an example. Figure 1c Take 4-bit addition operation as an example. Figure 1a , Figure 1b , Figure 1c In the above, read indicates the addend (or augend) directly read from the memory; add indicates the augend (or augend) that needs to be added to read from the external input; sum' indicates the result of directly adding read to add without carrying; c indicates the carry of each bit, where "1" indicates that the bit has a carry; sum indicates the final addition result. The final addition result can be obtained by flipping the next added value with a carry value of 1 in sum' (the flip start point) to the first added value with a value of 0 after the added value with a carry value of 1, and not flipping the remaining added values. Figure 1a , Figure 1b The end with the arrow in the direction indicates the end point of the flip, and the other end away from the arrow indicates the starting point of the flip.

[0050] Specifically, for Figure 1a In the order from right to left (i.e., from low to high), for the flipping of the first area: the next added value with a carry value of 1 in sum' is the added value of bit2; the first added value with a value of 0 after the added value with a carry value of 1 is the added value of bit5, so the added values ​​of bit2 to bit5 are flipped during flipping. For the flipping of the second area: the next added value with a carry value of 1 in sum' is the added value of bit6; the first added value with a value of 0 after the added value with a carry value of 1 is the added value of bit6, so the added value of bit6 is flipped during flipping.

[0051] Specifically, for Figure 1bIn the order from right to left, since the carry value of bit1 is 1, based on the above flipping principle, it can be determined that the added value of bit2 is the starting point added value and the added value of bit3 is the end point added value, so the added value of bit2 to bit3 will be flipped. Similarly, since the carry value of bit3 is 1, it can be determined that the added value of bit4 is both the starting point added value and the end point added value, so the added value of bit4 will be flipped. Similarly, since the carry value of bit4 is 1, it can be determined that the added value of bit5 is both the starting point added value and the end point added value, so the added value of bit5 will be flipped. Similarly, since the carry value of bit5 is 1, it can be determined that the added value of bit6 is both the starting point added value and the end point added value, so the added value of bit6 will be flipped.

[0052] Specifically, for Figure 1c In the sequence from right to left, the carry value of bit1 is 1. Therefore, based on the above flipping principle, since the carry value of bit0 is 1, it can be determined that the added value of bit1 is both the starting point added value and the end point added value, so the added value of bit1 will be flipped. Similarly, since the carry value of bit1 is 1, it can be determined that the added value of bit2 is both the starting point added value and the end point added value, so the added value of bit2 will be flipped. Similarly, since the carry value of bit2 is 1, it can be determined that the added value of bit3 is both the starting point added value and the end point added value, so the added value of bit3 will be flipped. Similarly, since the carry value of bit3 is 1, it can be determined that the added value of bit4 is both the starting point added value and the end point added value, so the added value of bit4 will be flipped. Among them, bit4 has no added value, which can be defaulted to 0, so it is 1 after flipping. In one implementation, since the next added value of the carry value of the highest bit of the addend or the augend does not exist, the carry value of the highest bit of the addend or the augend can be directly used as the next added value. For example, Figure 1c The carry value of bit3 in is the carry value of the highest bit of the addend or augend. Since the added value of bit4 does not exist, the carry value of bit3 can be directly used as the added value of bit4.

[0053] Based on the above data operation principle, such as Figure 2 As shown, the adder of the present application may include: a control module and a plurality of operation modules, each operation module including a first latch, a second latch, and a first selection circuit. The first output terminal (such as represented by Q) and the second output terminal (such as represented by QB) of the second latch are both connected to the first selection circuit. Each operation module is used for the addition operation of a single-bit addend and an augend.

[0054] In some possible implementations, the first latch and the second latch may also be replaced by registers or other devices with storage functions.

[0055] The first latch is used to store the carry value of the addition of the addend and the augend, and one first latch is used to store a carry value. The second latch is used to store the added value of the addition of the addend and the augend when the carry is ignored, and one second latch is used to store a one-bit added value. The added values ​​stored in multiple second latches are combined to form the initial addition result of the addition of the multi-bit addend and the augend. The first output terminal of the second latch outputs the added value, and the second output terminal of the second latch outputs the opposite value of the added value, for example, if Q=1, then QB=0, and vice versa, if Q=0, then QB=1.

[0056] The control module is connected to each operation module, and is used to control all first selection circuits from the first operation module to the second operation module to output the value of the second output end of the second latch, and control all first selection circuits in the remaining operation modules to output the value of the first output end of the second latch, so as to obtain the final addition result. The control module can be controlled by the first operation module to the second operation module according to the carry value and the addition value in each operation module, so as to output the value of the second output end of the second latch, and control all first selection circuits in the remaining operation modules to output the value of the first output end of the second latch.

[0057] The first operation module is the next operation module of the operation module with a carry value of 1. The second operation module is the first operation module whose logical position is located after the operation module with a carry value of 1 and whose addition value is 0. The first operation module serves as a flip starting point module, and the second operation module serves as a flip end point module. In some possible implementations, the first operation module and the second operation module can be the same operation module. Since the addition operation is performed in order from right to left, the logical position of the second operation module is located to the left of the logical position of the operation module with a carry value of 1.

[0058] The first selection circuit is used to respond to the control of the control module and selectively output the value of the first output terminal or the second output terminal of the second latch. For example, the control module can send a control signal to the first selection circuit to control the selection logic of the first selection circuit. For example, when the control signal is a high level 1, the first selection circuit outputs the value of the first output terminal of the second latch. On the contrary, when the control signal is a high level 0, the first selection circuit outputs the value of the second output terminal of the second latch. Of course, the selection logic can also be reversed.

[0059] In some possible implementations, the first selection circuit may include two switches, one of which is connected to the first output terminal of the second latch, and the other is connected to the second output terminal of the second latch, the control signals of the two switches are opposite, and only one switch is turned on at the same time. In some possible implementations, the first selection circuit may include a selector, and the two input terminals of the selector are respectively connected to the first output terminal and the second output terminal of the second latch.

[0060] In some possible implementations, such as Figure 3 As shown, each operation module also includes: a second selection circuit and a third selection circuit. The first output terminal (such as represented by Q) and the second output terminal (such as represented by QB) of the first latch are connected to the second selection circuit, and the second selection circuit is also connected to the first input terminal (such as represented by S) of the second latch. The first output terminal and the second output terminal of the first latch are connected to the third selection circuit, and the third selection circuit is also connected to the second input terminal (such as represented by R) of the second latch.

[0061] The first latch is also used to store the first data. The second selection circuit and the third selection circuit are controlled by the second data. For example, when the second data is 1, the second selection circuit selects to output the value of the second output terminal of the first latch, and the third selection circuit selects to output the value of the first output terminal of the first latch; when the second data is 0, the second selection circuit selects to output the value of the first output terminal of the first latch, and the third selection circuit selects to output the value of the second output terminal of the first latch. The first data is the addend, and the second data is the addend, or the first data is the addend and the second data is the addend.

[0062] In a possible implementation, the first latch is used to store the addend (or augend), and by controlling the second selection circuit and the third selection circuit, the second latch can be made to store the added value of the addend and the augend when the carry is ignored. Figure 1a For example, assuming the first data is Figure 1a The second data is Figure 1aFor bit0, since read is 0 and add is 1, the value of the first input terminal (S) of the second latch is 1, and the value of the second input terminal (R) is 0. At this time, the value of the second latch is 1. For bit1, since read is 1 and add is 1, the value of the first input terminal (S) of the second latch is 0, and the value of the second input terminal (R) is 1. At this time, the value of the second latch is 0. For bit2, since read is 1 and add is 0, the value of the first input terminal (S) of the second latch is 1, and the value of the second input terminal (R) is 0. At this time, the value of the second latch is 1. For bit3, since read is 0 and add is 1, the value of the first input terminal (S) of the second latch is 1, and the value of the second input terminal (R) is 0. At this time, the value of the second latch is 1. For bit4, since read is 1 and add is 0, the value of the first input terminal (S) of the second latch is 1, and the value of the second input terminal (R) is 0. At this time, the value of the second latch is 1, and so on.

[0063] Among them, the truth table of the input and output of the second latch is shown in Table 1.

[0064] Table 1

[0065] S R Q 0 0 Keep Q constant 0 1 0 1 0 1

[0066] In one possible implementation, the first latch may first store the first data (addend or augend), and by controlling the second selection circuit and the third selection circuit, complete the addition of the addend and the augend while ignoring the carry, and store the added value in the second latch; and then use the first latch to store the carry value of the addition of the addend and the augend.

[0067] In some possible implementations, the second selection circuit and the third selection circuit may have the same structure, for example, both include a first switch S1 and a second switch S2, wherein a control signal of the first switch is opposite to a control signal of the second switch.

[0068] like Figure 4 As shown, the first output end of the first latch is connected to the first input end of the second latch through the first switch, and the second output end of the first latch is connected to the first input end of the second latch through the second switch; the first output end of the first latch is connected to the second input end of the second latch through the second switch, and the second output end of the first latch is connected to the second input end of the second latch through the first switch. Figure 4 The middle switch S1 is closed when the control signal is at a low level 0, and the switch S2 is closed when the control signal is at a high level 1.

[0069] In some possible implementations, the second selection circuit and the third selection circuit may have the same structure, for example, both include a selector, wherein the first output terminal and the second output terminal of the first latch are connected to the first input terminal of the second latch through a selector; the first output terminal and the second output terminal of the first latch are connected to the second input terminal of the second latch through another selector.

[0070] In some possible implementations, each operation module further includes: an output port, and the output end of the first selection circuit is connected to the output port. Figure 4 The Output in can represent the output port.

[0071] In some possible implementations, such as Figure 5 As shown, each operation module further includes: a write control module. The write control module is connected to the first input terminal and the second input terminal of the first latch, and the write control module is used to write the carry value of the addend and the augend into the first latch. In some possible implementations, the write control module can also be used to write the first data into the first latch.

[0072] The write control module may write required data by inputting different values ​​into the first input terminal and the second input terminal of the first latch.

[0073] In some possible implementations, such as Figure 5 As shown, each operation module further includes: a carry acquisition circuit, and the carry acquisition circuit is connected to the write control module. Figure 5 Only the case where both the write control module and the carry acquisition circuit are included is shown. In some possible implementations, the carry acquisition circuit may not be included. The carry acquisition circuit is used to obtain a carry value of the addition of the addend and the augend according to the addend and the augend, and send the carry value to the write control module so that the write control module writes the carry value into the first latch.

[0074] In some embodiments, the carry acquisition circuit may include an AND gate, and the addend and the augend are ANDed by the AND gate to obtain a carry value. If the addend and the augend are both 1, the carry value is 1, otherwise the carry value is 0.

[0075] In some possible implementations, the control module may include a controller, which may be used to control each operation module based on the flipping mechanism to output a correct value, thereby obtaining a final addition result.

[0076] In other possible implementations, such as Figure 6As shown, the control module may include: a plurality of control units corresponding to the plurality of operation modules one by one, each control unit includes: a carry value control branch, an addition value control branch and a transmission control line. The transmission control line is respectively connected to the carry value control branch, the addition value control branch and the first selection circuit, and the transmission control lines in each control unit are connected in sequence. Among them, Figure 6 The number of control units in is not limited to 4 as shown in the example. Figure 6 This is just an example of a 4-bit addition operation.

[0077] The carry value control branch is used to control the level of the transmission control line according to the carry value. For example, if the carry value is 1, the level of the transmission control line is controlled to be low level. If the carry value is 0, the level of the transmission control line is controlled to be high level. Of course, it can also be reversed. The level of the transmission control line is used to control the selection logic of the first selection circuit.

[0078] The added value control branch is used to control whether the transmission control line where it is located is connected to the transmission control line in the next control unit according to the added value, thereby changing the level of the transmission control line in the next control unit.

[0079] The carry value of the carry value control branch in the first control unit is a default value of 0, and the carry values ​​of the carry control branches from the second control unit to the last control unit are the carry values ​​in the first latch corresponding to the previous control unit.

[0080] In some possible implementations, the circuit schematic diagram of each control unit may be as follows: Figure 7 As shown, the carry value control branch may include a plurality of switches connected in series, for example, a P switch and two N switches. Figure 7 The pre signal in is the control signal of the P tube, and the P tube is used to charge the transmission control line so that the level of the transmission control line is high in the initial state. The R_EN signal is the control signal of one of the N tubes, and is high by default. The control signal of the N1 tube is a carry value. The carry value of the N1 tube in the first control unit is the default value 0, and the carry value of the N1 tube from the second control unit to the last control unit is the carry value in the first latch corresponding to the previous control unit. In some possible implementations, the N tube controlled by R_EN can also be removed. In this case, the carry value control branch can include 2 switches in series, one is a P tube and the other is an N1 tube.

[0081] The added value control branch may include two switches connected in parallel, for example, a P switch and an N switch, thereby forming a bidirectional switch. Figure 7The control signal of the N tube in is the added value sum', and the control signal of the P tube is the opposite value sumB' of the added value. In some possible implementations, the added value control branch may include only one N tube, in which case the p tube may be removed.

[0082] In order to better illustrate the principle of the above control unit, the following Figure 8 The schematic diagram shown is used to illustrate, Figure 8 So Figure 1a The carry value and the added value of the 4 bits ([bit3:bit0]) on the right are used as examples. When the level of the default transmission control line B is low, the opposite value of the added value is output. In the initial state, the level of the transmission control line defaults to high level 1. From right to left, for the control unit where bit0 is located, since the carry value of the N1 tube is 0 and the N1 tube is not turned on, the level of the transmission control line is still high level 1, and the sum' of bit0 does not need to be flipped. For the control unit where bit1 is located, since the carry value of the N1 tube is 0 and the N1 tube is not turned on, the level of the transmission control line is still high level 1, and the sum' of bit1 does not need to be flipped. For the control unit where bit2 is located, since the carry value of the N1 tube is 1 (C of bit1=1), the N1 tube is turned on, pulling the level of the transmission control line down to a low level of 0, and the sum' of bit2 needs to be flipped to 0. At the same time, sum'=1, the transmission control line where bit2 is located is connected to the transmission control line of the control unit where bit3 is located, thereby pulling the level of the transmission control line of the control unit where bit3 is located down to a low level of 0. Therefore, the sum' of bit3 needs to be flipped to 0.

[0083] The above Figure 8 The 4-bit addition operation shown can be extended to more bits, such as 1-Byte or 2-Byte addition operations. Therefore, the 4-bit addition operation cannot be understood as a limitation on the application.

[0084] In some embodiments, the adder shown in the present application may be an in-memory adder, which is an adder integrated inside a memory, and allows addition operations to be performed directly inside a memory array. When the adder is an in-memory adder, in some embodiments, the first latch and the second latch may be latches in the memory, and the area overhead may be reduced by sharing the latches in the memory. For example, the first latch may be a latch in a sense amplifier of the memory, and the second latch may be a latch in an output circuit of the memory.

[0085] Based on the same inventive concept, the embodiment of the present application provides a memory including: a memory read circuit and the above-mentioned adder, the memory read circuit including: a plurality of storage cells, a plurality of sense amplifiers and a plurality of output circuits. Each storage cell corresponds to a sense amplifier and an output circuit. Multiple storage cells can be controlled by the same word line.

[0086] The first latch in the adder is a latch in the sense amplifier, and the second latch is a latch in the output circuit. The present application provides an addition operation combined with a memory, which reduces area overhead by effectively utilizing the sense amplifier and the output circuit while achieving fast operation.

[0087] Combine the following Fig. 9 Explain the reading and writing principles of the storage unit. Fig. 9 As shown in the figure, it is a common 6-transistor storage unit. Fig. 9 WL in the figure represents word line, BL and BLB are a pair of bit lines, PU and PD form two inverters connected end to end with PU_X and PD_X, that is, the output of one inverter (composed of PU and PD) is connected to the input of another inverter (composed of PU_X and PD_X), and vice versa. The two inverters are connected end to end to form a latch. When there is no external influence, the data stored in Q and QB are very stable and the two are complementary. For example, when Q=0, QB=1 or, when Q=1, QB=0.

[0088] Assume Q=0, QB=1, BL=BLB=Float1 (that is, after the bit lines BL and BLB are charged to 1, the charging circuit is turned off to make them float at 1). When reading data, after WL=1, PG and PG_X are both in the on state. Since Q=0, PG will pull BL=Float1 down after being turned on, and BLB remains unchanged, so that a voltage difference (DeltaV) is generated between BL and BLB. The voltage difference is amplified by the subsequent sense amplifier (Sense Amplifier, SA) to read the data, and then BL and BLB are charged to 1 to complete a data read.

[0089] When writing data, BL and BLB will form a pair of complementary signals. When the WL signal is enabled (WL=1), if the current values ​​stored in Q and QB are different from the values ​​you want to write, the data of BL and BLB will be driven forcefully to flip the values ​​of Q and QB. For example, assuming that Q=0 and QB=1 before writing, to make QB=0 and Q=1, you need to make BL=1 and BLB=0. In this process, there will be a situation where BLB's 0 and QB=1 "fight (or compete)" at PU_X. BLB's 0 must be strong enough to beat QB=1 to ensure data writing.

[0090] In one implementation, the memory read circuit may be configured as follows: Fig.10 As shown, Fig.10 Only one storage unit, one sense amplifier and one output circuit are shown. The memory read circuit may include multiple Fig.10 The structure shown. Fig.10 The PSA0, NSA0, PSA1 and NSA1 transistors in the circuit constitute the first latch. The output circuit includes: Fig.11 The latch shown can be called the second latch. When the storage is stable, SACI=SATI=1, and Q and QB maintain the previous storage value (Q=QB inverse); when new data is input, SACI=SATI inverse, such as SACI=0, SATI=1, and Q=0, QB=1, and when SACI changes from 0 back to 1, the state of Q or QB remains unchanged. That is, when the latch is in the locked state: SACI=SATI=1, Q=QB inverse; when the latch is in the updated state: SACI=SATI inverse, Q=SATI, Q=QB inverse.

[0091] Through Fig.10 The memory read circuit shown in FIG. 1 is modified to integrate the above adder into the memory. In one implementation, the modified memory read circuit is as follows: Fig.12 As shown, Fig.12 The part with the dotted line frame is the improved part. Fig.12 Only some improvements are shown. By adding selection switches S1 and S2 between the sense amplifier and the output circuit, that is, adding selection switches between the first latch and the second latch, the addition of the addend and the augend is realized when the carry is ignored. At the same time, NT tubes and NC tubes are added to change the potentials of SACI and SATI, so as to store the carry value in the sense amplifier, wherein the control signals of the NT tube and the NC tube are opposite, which can be the carry value C and the opposite value of the carry value C'. When the carry value is written into the first latch by controlling the NT tube and the NC tube, in order to save circuit power consumption, the tail tube 303 can be controlled to be in a closed state by adding an AND gate (And). When the circuit is working, SAEN=1, and if a low-level signal is input to the other input end of the AND gate, the tail tube 303 can be turned off. In addition, it is necessary to add the above-mentioned first selection circuit at the output end of the second latch, and add a corresponding control module.

[0092] The adder provided by the memory embodiment has the same implementation principle and technical effects as those of the aforementioned adder embodiment. For the sake of brief description, for matters not mentioned in the memory embodiment, reference may be made to the corresponding contents in the aforementioned adder embodiment.

[0093] Based on the same inventive concept, the embodiment of the present application also provides a data operation method of an adder based on a two-step operation algorithm, which can be applied to an adder. Fig.13 The principle is explained.

[0094] S1: Get the initial addition result of the addend and the augend while ignoring the carry.

[0095] S2: According to the carry values ​​of the addend and the augend, the added values ​​between the starting point added value and the end point added value and the two end points in the initial addition result are flipped, and the remaining added values ​​are not flipped to obtain the final addition result. Among them, the starting point added value is the next bit added value with a carry value of 1 in the initial addition result, and the end point added value is the first bit added value with a value of 0 after the added value with a carry value of 1 in the initial addition result.

[0096] For the specific flipping principle, please refer to the above Figure 1a , Figure 1b , Figure 1c The part shown, wherein the structure of the adder provided by the method embodiment is not limited to the above-mentioned adder structure, and can be any adder that adopts the operation principle shown in this application.

[0097] The implementation principle and technical effects provided by the method embodiment are the same as those of the aforementioned adder embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding contents in the aforementioned adder embodiment. Based on the same inventive concept, the present application embodiment also provides an electronic device, which includes the above-mentioned memory. In some possible implementations, the present application embodiment provides a structural block diagram of an electronic device, such as Fig.14 As shown, the electronic device includes: a transceiver, a memory, a communication bus and a processor.

[0098] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store a computer program, wherein the computer program includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The processor is used to execute the software function module or computer program stored in the memory.

[0099] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (ElectricErasable Programmable Read-Only Memory, EEPROM), etc.

[0100] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.

[0101] The above-mentioned electronic devices include but are not limited to smart phones, tablets, notebooks, and computers.

[0102] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0104] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An adder, characterized in that: include: A control module and a plurality of operation modules, each operation module comprising a first latch, a second latch, and a first selection circuit; The first output terminal and the second output terminal of the second latch are both connected to the first selection circuit; The first latch is used to store a carry value of the addition of the addend and the augend; The second latch is used to store the added value of the addend and the augend when the carry is ignored; wherein the first output terminal of the second latch outputs the added value, and the second output terminal of the second latch outputs the opposite value of the added value; The control module is used to control all the first selection circuits from the first operation module to the second operation module to output the value of the second output end of the second latch, and control all the first selection circuits in the remaining operation modules to output the value of the first output end of the second latch to obtain a final addition result; The first operation module is the next operation module of the operation module with a carry value of 1; the second operation module is the first operation module located after the operation module with a carry value of 1 and with an added value of 0.

2. The adder according to claim 1, characterized in that Each computing module also includes: a second selection circuit, wherein the first output terminal and the second output terminal of the first latch are connected to the second selection circuit, and the second selection circuit is also connected to the first input terminal of the second latch; a third selection circuit, the first output terminal and the second output terminal of the first latch are connected to the third selection circuit, and the third selection circuit is also connected to the second input terminal of the second latch; The first latch is also used to store first data; the second selection circuit and the third selection circuit are controlled by second data; wherein the first data is an addend and the second data is an augend, or the first data is an augend and the second data is an addend.

3. The adder according to claim 2, characterized in that The second selection circuit and the third selection circuit both include: A first switch and a second switch, wherein a control signal of the first switch is opposite to a control signal of the second switch; The first output terminal of the first latch is connected to the first input terminal of the second latch through the first switch, and the second output terminal of the first latch is connected to the first input terminal of the second latch through the second switch; The first output terminal of the first latch is connected to the second input terminal of the second latch through the second switch, and the second output terminal of the first latch is connected to the second input terminal of the second latch through the first switch.

4. The adder according to claim 2, characterized in that: The second selection circuit and the third selection circuit both include: A selector, the first output end and the second output end of the first latch are both connected to the first input end of the second latch through one of the selectors; the first output end and the second output end of the first latch are both connected to the second input end of the second latch through another of the selectors.

5. The adder according to claim 1, characterized in that: Each operation module further includes: a write control module, the write control module being connected to a first input terminal and a second input terminal of the first latch; The write control module is used to write a carry value of the sum of the addend and the augend into the first latch.

6. The adder according to claim 5, characterized in that Each operation module further includes: a carry acquisition circuit, the carry acquisition circuit being connected to the write control module; The carry acquisition circuit is used to acquire a carry value of the addition of the addend and the augend according to the addend and the augend, and send the carry value to the write control module.

7. The adder according to claim 1, characterized in that: The control module comprises: a plurality of control units corresponding to the plurality of operation modules one by one; each control unit comprises: a carry value control branch, an addition value control branch and a transmission control line; The transmission control line is connected to the carry value control branch, the addition value control branch, and the first selection circuit respectively, and the transmission control lines in each control unit are connected in sequence; The carry value control branch is used to control the level of the transmission control line according to the carry value; The added value control branch is used to control whether the transmission control line where the added value is located is connected with the transmission control line in the next control unit according to the added value; The carry value of the carry value control branch in the first control unit is a default value, and the carry values ​​of the carry control branches in the second control unit to the last control unit are the carry values ​​in the first latch corresponding to the previous control unit.

8. The adder according to any one of claims 1 to 7, characterized in that: The adder is an in-memory adder, and the first latch and the second latch are latches in a memory.

9. A memory, characterized in that: include: A memory read circuit, the memory read circuit comprising: a plurality of storage cells, a plurality of sense amplifiers and a plurality of output circuits; each storage cell corresponds to a sense amplifier and an output circuit; And the adder as described in any one of claims 1-8, the first latch in the adder is the latch in the sense amplifier, and the second latch is the latch in the output circuit.

10. An electronic device, characterized in that: include: The memory as claimed in claim 9.

11. A data operation method of an adder, characterized in that: Applied to an adder, the method comprises: Get the initial addition result of the addend and the augend ignoring the carry; According to the carry value of the addend and the augend, the added values ​​between the starting point added value and the end point added value and the added values ​​at both end points in the initial addition result are flipped, and the remaining added values ​​are not flipped to obtain the final addition result; The starting added value is the next added value with a carry value of 1 in the initial added result, and the ending added value is the first added value with a value of 0 after the added value with a carry value of 1 in the initial added result.

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