Method for thermally loading slave core system by master core in AMP mode

Abstract

The invention belongs to the technical field of computer system software, and particularly relates to a method for thermally loading a slave core system by a master core in an AMP mode, which is used for thermally loading a bare computer executable program or a system binary mirror image file of a slave processor core on the basis of a master processor core in the AMP mode of an ARM (Advanced RISC Machines) platform. And the master processing core writes the binary file of the slave processor core to be executed or the execution address of the bare computer application program into the ARM on-chip storage OCM in a memory reading and writing manner, and activates the operation when the binary file or the execution address of the bare computer application program needs to be loaded to the slave processor core. Redundant design of a hardware platform can be avoided to a certain extent, and hardware and BSP research and development cost in the initial stage of a project is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer system software, and in particular relates to a method for hot loading a slave core system with a master core in an AMP mode. Background Art

[0002] With the development of embedded application fields, full and reasonable use of hardware resources is a more important goal of project research and development. At the same time, with the development of various heterogeneous fusion hardware platforms, the flexible and reasonable use of multi-core processor AMP mode is still a research hotspot in the industry. In the traditional way, when different operating systems need to be run at the same time, the hardware PCB needs to design two or more processor chips. The ARM architecture provides an advanced AMP mode that can run different operating systems simultaneously or in time-sharing on different processor cores, or the main core runs the main operating system and the slave core runs a small real-time operating system, or the main core runs the main operating system and the slave core runs the bare metal program. Summary of the invention

[0003] In view of this, the present invention provides a method for hot loading a slave core system with a master core in AMP mode, which can meet the requirement scenarios that different processor cores in the AMP mode of the ARM architecture run operating systems of different forms, or the master processor runs an operating system, and the slave processor runs a bare metal binary executable program.

[0004] The technical solution of the present invention:

[0005] A method for hot loading a slave core system with a master core in an AMP mode is used to hot load a bare metal executable program or a system binary image file of a slave core based on a master processor core in an AMP mode of an ARM platform; the method for hot loading a slave core system with a master core comprises the following steps:

[0006] S101: When the main processing core detects that the slave processor core program or the system image has been updated, the slave processor program or the system binary image to be updated is read into a program storage space; the storage space is a dedicated space reserved in the storage space manageable by the main processing core;

[0007] S102: The APP on the main processor core parses the program or system image to be updated, converts the program or system image file to be updated from the elf format to the bin format, and loads the converted bin file to the link address corresponding to the DDR by using a memory mapping method;

[0008] S103: Write the program or system image to be updated by the slave processor into the on-chip memory OCM by using the read-write memory method, and start activating the program or system image in the memory OCM when the slave processor needs to be hot-updated and loaded.

[0009] Furthermore, the method for starting to activate the program or system image in S103 is: disabling the OCM cache attribute, jumping to the assembly instruction after CPU1 is reset, executing the assembly instruction, entering the ARM wfe state and waiting for the sev wake-up instruction.

[0010] Further, a bare metal executable program or a system binary image file is obtained from the processor core.

[0011] Furthermore, the storage space managed by the main processor core is an application partition divided by a non-volatile storage device.

[0012] Furthermore, before executing S103, the following steps are also included: configuring a main operating system in AMP mode for the main processor core and running it.

[0013] Furthermore, the memory address spaces of the master processor core and the slave processor core do not overlap or conflict.

[0014] Furthermore, the operating system running on the main processor core configures the MEMORY range used by the bare metal executable program or system binary image file of the slave processor core, and the bare metal executable program or system binary image file of the slave processor core specifies the link memory address range of the application or system image by modifying the link script.

[0015] Beneficial effects of the present invention:

[0016] The main processor of the present invention is adapted to a stable embedded Linux operating system to realize the software basis of the method, and the AMP mode of ARMv8 provides the hardware characteristics of the method. In the main processor embedded Linux system, a simple shell script is used to restart the slave processor core. In the main processor embedded Linux system, a C language program is written to make the slave processor core enter the WFE state, and the slave processor binary program is moved to the DDR address to be executed through memory mapping, and finally the slave processor is directly restarted in the program. The highlight of this design is that only a shell script and a C language program need to be developed to realize this function, the method verification is reliable and stable, and the slave processor can realize simultaneous / time-sharing operation of the corresponding binary code. In addition, the design can also be used for the main processor core to hot update the slave processor core system version. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1A schematic diagram of an operating framework of a method for hot loading a slave core system with a master core in an AMP mode;

[0019] Figure 2 A flowchart of a method for hot loading a slave core system with a master core in AMP mode is provided. DETAILED DESCRIPTION

[0020] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0021] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0022] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0025] In one embodiment of the present invention, a method for hot loading a slave core system in a master core in AMP mode is provided, which is used to hot load a bare metal executable program or a system binary image file of a slave processor core based on a master processor core in AMP mode of an ARM platform; Figure 1 , 2 , the method for hot loading a slave core system with a master core comprises the following steps:

[0026] S101: When the main processing core detects that the slave processor core program or the system image has been updated, the slave processor program or the system binary image to be updated is read into a program storage space; the storage space is a dedicated space reserved in the storage space manageable by the main processing core;

[0027] S102: The APP on the main processor core parses the program or system image to be updated, converts the program or system image file to be updated from the elf format to the bin format, and loads the converted bin file to the link address corresponding to the DDR by using a memory mapping method;

[0028] S103: Write the program or system image to be updated by the slave processor into the on-chip memory OCM by using the read-write memory method, and start activating the program or system image in the memory OCM when the slave processor needs to be hot-updated and loaded.

[0029] In this embodiment, the method for starting to activate the program or system image in S103 is: disabling the OCMcache attribute, jumping to the assembly instruction after CPU1 is reset, executing the assembly instruction to enter the ARM wfe state and wait for the sev wake-up instruction.

[0030] In this embodiment, the bare metal executable program or system binary image file is from the processor core.

[0031] In this embodiment, the storage space managed by the main processor core is an application partition divided by a non-volatile storage device.

[0032] In this embodiment, before executing S103, the following steps are also included: configuring a main operating system in AMP mode for the main processor core and running it.

[0033] In this embodiment, the memory address spaces of the master processor core and the slave processor core do not overlap or conflict.

[0034] In this embodiment, the operating system running on the main processor core configures the MEMORY range used by the bare metal executable program or system binary image file of the slave processor core, and the bare metal executable program or system binary image file of the slave processor core specifies the link memory address range of the application or system image by modifying the link script.

[0035] In this embodiment, the ARM loads the main processor to adapt to the mainstream embedded operating system (generally adapted to the embedded Linux system);

[0036] When the main CPU is adapted to the Linux system, it is necessary to configure DDR space, OCM address, cache, etc.

[0037] The main processor application converts the bare metal executable program or system binary from the processing to the bin format;

[0038] The master processing core needs to perform a pre-soft reset operation on the slave processing core. It needs to write the WFE instruction to the starting address of a specific address value, then jump to the code address to execute the above specific address, and finally clear the value of the corresponding register;

[0039] The main processor core performs a hot reset on the slave core. The reset commands for systems adapted by processors from different manufacturers may be different. For example, the main processing system built by Zynq's petalinux can use the poke instruction to read and write hardware register addresses; for example, Tianmai Linux needs to include the construction of the devmem command to read and write memory addresses;

[0040] Develop C language application based on main processor operating system (embedded Linux). Open the binary program in bin format to be hot loaded from the processor core in read-only mode, and then use memory mapping to map the file to the actual memory DDR. Move the file read and write position, and copy the file according to the page size in the for loop structure;

[0041] The main processor core senses that the slave processor core has a hot load signal, that is, executes a jump instruction to start the bare metal application or operating system of the slave processor core;

[0042] The execution process of this embodiment is as follows: the main processor core is loaded and run, the main processor receives the user's hot-load slave processor core binary program signal, and the main processor operating system executes the script file for resetting the slave processing function. At this time, the slave processor enters the wfe state. The main processor operating system executes the application program to implement the memory migration of the binary program to be hot-loaded, and resets the slave processor.

[0043] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for hot loading a slave core system with a master core in AMP mode, characterized in that: Used for hot loading a bare metal executable program or a system binary image file of a slave processor core based on a master processor core in the AMP mode of an ARM platform; the method for hot loading a slave core system with a master core comprises the following steps: S101: When the main processing core detects that the slave processor core program or the system image has been updated, the slave processor program or the system binary image to be updated is read into a program storage space; the storage space is a dedicated space reserved in the storage space manageable by the main processing core; S102: The APP on the main processor core parses the program or system image to be updated, converts the program or system image file to be updated from the elf format to the bin format, and loads the converted bin file to the link address corresponding to the DDR by using a memory mapping method; S103: Write the program or system image to be updated by the slave processor into the on-chip memory OCM by using the read-write memory method, and start activating the program or system image in the memory OCM when the slave processor needs to be hot-updated and loaded.

2. The method for hot loading a slave core system with a master core in AMP mode according to claim 1, characterized in that: The method for starting to activate the program or system image in S103 is: disabling the OCM cache attribute, jumping to the assembly instruction after CPU1 is reset, executing the assembly instruction, entering the ARM wfe state and waiting for the sev wake-up instruction.

3. The method for hot loading a slave core system with a master core in AMP mode according to claim 2, characterized in that: From a bare metal executable program or system binary image file of the processor core.

4. The method for hot loading a slave core system with a master core in AMP mode according to claim 3, characterized in that: The storage space managed by the main processor core is an application partition divided by a non-volatile storage device.

5. The method for hot loading a slave core system with a master core in AMP mode according to claim 4, characterized in that: Before executing S103, the following steps are also included: configuring a main operating system in AMP mode for the main processor core and running it.

6. The method for hot loading a slave core system with a master core in AMP mode according to claim 5, characterized in that: The memory address spaces of the master processor core and the slave processor core do not overlap or conflict.

7. The method for hot loading a slave core system with a master core in AMP mode according to claim 6, characterized in that: The operating system running on the main processor core configures the MEMORY range used by the bare metal executable program or system binary image file of the slave processor core, and the bare metal executable program or system binary image file of the slave processor core specifies the link memory address range of the application or system image by modifying the link script.

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