Instruction execution method and device, electronic equipment and storage medium

Abstract

The invention provides an instruction execution method and device, electronic equipment and a storage medium, and relates to the technical field of computers. Under the condition that response data corresponding to N instructions are received, first serial numbers corresponding to the N instructions are determined at first, then the N first serial numbers are matched with a current target serial number, and finally according to the matching result of the N first serial numbers and the target serial number, at least one of the following items is executed: values in a preset register are updated, and the values in the preset register are updated. And performing instruction response feedback, and updating the target number. Therefore, sequential response feedback under the scene of out-of-order execution of the instruction is realized, and the accuracy and reliability of the instruction execution method are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an instruction execution method, device, electronic device and storage medium. Background Art

[0002] In the prior art, certain software / hardware mechanisms (such as source / destination operand forwarding, barrier instructions, etc.) can usually be used to resolve the read / write dependency or causal dependency between instructions in the processor. However, the prior art methods cannot be applied to processors that execute or complete instructions out of order with dependencies. How to propose an instruction execution method that can be applied to processors that execute or complete instructions out of order with dependencies is a problem that needs to be solved urgently. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] The first embodiment of the present disclosure provides an instruction execution method, including:

[0005] In the case of receiving response data corresponding to N instructions respectively, determining first numbers corresponding to the N instructions respectively, where N is a positive integer;

[0006] Match the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be responded to;

[0007] According to the matching results of the N first numbers and the target numbers, at least one of the following is performed: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes a plurality of status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0008] The second aspect of the present disclosure provides an instruction execution device, including:

[0009] A first determining module, configured to determine first numbers corresponding to N instructions respectively when receiving response data corresponding to the N instructions respectively, wherein N is a positive integer;

[0010] A matching module, used for matching the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be returned;

[0011] An execution module is used to execute at least one of the following according to the matching results of the N first numbers and the target numbers: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0012] The third aspect of the present disclosure provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the instruction execution method provided in the first aspect of the present disclosure is implemented.

[0013] The fourth aspect embodiment of the present disclosure proposes a computer-readable storage medium storing computer execution instructions. When the computer execution instructions are executed by a processor, the instruction execution method proposed in the first aspect embodiment of the present disclosure is implemented.

[0014] The fifth aspect embodiment of the present disclosure proposes a chip, which includes a processing circuit and an interface circuit; wherein the interface circuit is used to obtain instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the instruction execution method proposed in the first aspect embodiment of the present disclosure.

[0015] The sixth aspect embodiment of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, implements the instruction execution method proposed in the first aspect embodiment of the present disclosure.

[0016] The instruction execution method, device, electronic device and storage medium provided by the present disclosure have the following beneficial effects:

[0017] In the embodiment of the present disclosure, when receiving response data corresponding to N instructions respectively, first determine the first numbers corresponding to the N instructions respectively, then match the N first numbers with the current target number respectively, and finally, according to the matching results of the N first numbers with the target number, perform at least one of the following: update the value in the preset register, perform instruction response feedback, and update the target number. Thus, when the processor receives response data corresponding to N instructions respectively, it matches the numbers corresponding to the N instructions respectively with the target number of the current response to be returned, and performs the corresponding operation according to the matching results, thereby realizing sequential response feedback in the scenario of out-of-order execution of instructions, and improving the accuracy and reliability of the instruction execution method.

[0018] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A flowchart of an instruction execution method provided by an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of the framework structure of the instruction execution method provided in the embodiment of the present disclosure;

[0022] Figure 3 A flowchart of an instruction execution method provided by another embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a process for updating the value of a status bit in a register in an instruction execution method provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of a process of executing instruction response feedback in an instruction execution method provided in an embodiment of the present disclosure;

[0025] Figure 6 A flowchart of an instruction execution method provided by another embodiment of the present disclosure;

[0026] Figure 7 A flowchart of an instruction execution method provided by another embodiment of the present disclosure;

[0027] Figure 8 A flowchart of an instruction execution method provided by another embodiment of the present disclosure;

[0028] Fig. 9 A flowchart of an instruction execution method provided by another embodiment of the present disclosure;

[0029] Fig.10 A schematic diagram of an implementation of an instruction execution method in a multi-threaded scenario provided by an embodiment of the present disclosure;

[0030] Fig.11 A schematic diagram of the structure of an instruction execution device provided by another embodiment of the present disclosure;

[0031] Fig.12 A block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown;

[0032] Fig.13 It is a schematic diagram of the structure of the chip proposed in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0034] The following describes the instruction execution method, device, electronic device and storage medium of the embodiments of the present disclosure with reference to the accompanying drawings.

[0035] Figure 1 A flowchart of an instruction execution method provided by an embodiment of the present disclosure.

[0036] It should be noted that the instruction execution method of the embodiment of the present disclosure can be applied to an instruction execution device. In some possible embodiments, the device can be configured in an electronic device or a chip so that the electronic device or the chip can execute the instruction execution method proposed in the embodiment of the present disclosure.

[0037] like Figure 1 As shown, the instruction execution method may include the following steps:

[0038] Step 101, when response data corresponding to N instructions are received, first serial numbers corresponding to the N instructions are determined, wherein N is a positive integer.

[0039] It should be noted that the instruction execution method proposed in the embodiment of the present disclosure can be applied to a processor with a single instruction multiple thread (SIMT) architecture, and the present disclosure does not limit this.

[0040] It should be noted that the instructions in the instruction execution method provided by the present disclosure may be any type of instructions with dependency relationships. For example, the instructions may be memory access instructions with dependency relationships.

[0041] It should be noted that, when the instruction is a memory access instruction, the response data corresponding to the instruction may be the response data returned by the storage system.

[0042] The first number may be an instruction sequence number, which may be an execution sequence number between instructions having a dependency relationship.

[0043] It should be noted that the first numbers of the instructions corresponding to the N response data received by the processor can be random numbers or sequential numbers, and the present disclosure does not limit this.

[0044] In the present disclosure, when the processor receives response data corresponding to N instructions respectively, in order to determine whether to execute the instruction response feedback, the processor may first determine the first numbers corresponding to the N instructions respectively.

[0045] Step 102, matching the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be responded to currently.

[0046] In the present disclosure, after determining the first numbers corresponding to N instructions respectively, the processor can first determine the number corresponding to the first instruction to be returned in response, and then match these N first numbers with the current target number respectively, so as to determine whether these N instructions contain the instruction corresponding to the target number, and thus determine whether to execute the instruction response feedback.

[0047] Step 103, according to the matching results of the N first numbers and the target number, perform at least one of the following: update the value in the preset register, perform instruction response feedback, and update the target number.

[0048] The preset register includes a plurality of status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0049] In some embodiments, the preset register may also include 1 status bit, which is not limited in the present disclosure.

[0050] The register may be a status register, which may be used to store the response status of the instruction.

[0051] The value of the status bit can be any pre-set form. For example, the value of the status bit can be the number "1", which is used to indicate that the corresponding instruction has been responded to and the processor has received the response data of the corresponding instruction. The value of the status bit can be the number "0", which is used to indicate that the corresponding instruction has not been responded to and the processor has not received the response data of the corresponding instruction, etc., and the present disclosure does not limit this.

[0052] In the present disclosure, when the processor updates the value of the status bit in a preset register based on the matching results of N first numbers and the target numbers, since the processor has received the response data of the instructions corresponding to the N first numbers, at this time, the value of the status bit corresponding to the N first numbers can be updated to a responded state. For example, the value of the status bit corresponding to the N first numbers can be updated to "1" to indicate that the instruction with the corresponding number has been responded to, and the value of the status bit of other instructions that have not been responded to can be set to "0" to indicate that the corresponding instruction has not been responded, that is, the processor has not received the response data of the corresponding instruction. The present disclosure does not limit this.

[0053] Optionally, when the N first numbers do not match the target numbers, the processor can determine that the instructions corresponding to the N first numbers are not the numbers of the first instructions to be returned in response. At this time, the processor can only update the values ​​of the first status bits in the register corresponding to the N first numbers to the first value without providing instruction response feedback.

[0054] The first value may be response data indicating that a command with a corresponding number has been obtained, and may be in any pre-set form. For example, the first value may be the number 1, etc., which is not limited in the present disclosure.

[0055] In the present disclosure, when there is a first number among the N first numbers that matches the target number, the processor can first update the values ​​of the status bits corresponding to the N first numbers to indicate that the response data of the instruction with the corresponding number has been received, and then perform instruction response feedback. After the instruction response feedback is completed, the target number is updated to the number of the first instruction to be returned for the next response.

[0056] In the embodiment of the present disclosure, when receiving response data corresponding to N instructions respectively, first determine the first numbers corresponding to the N instructions respectively, then match the N first numbers with the current target number respectively, and finally, according to the matching results of the N first numbers with the target number, perform at least one of the following: update the value in the preset register, perform instruction response feedback, and update the target number. Thus, when the processor receives response data corresponding to N instructions respectively, it matches the numbers corresponding to the N instructions respectively with the target number of the current response to be returned, and performs the corresponding operation according to the matching results, thereby realizing sequential response feedback in the scenario of out-of-order execution of instructions, and improving the accuracy and reliability of the instruction execution method.

[0057] Combine the following Figure 2 , the SMIT processor framework of the instruction execution method proposed in the present disclosure is illustrated by way of example. Figure 2 A schematic diagram of the framework structure of the instruction execution method provided in an embodiment of the present disclosure.

[0058] Figure 2 Taking memory access instructions as an example, the framework of the instruction execution method proposed in the present disclosure includes a scheduler 201, a memory access unit 202 and a storage system 203, wherein the memory access unit 202 includes an instruction sequence numbering module 2021, a request information cache module 2022 and a response sequencing module 2023.

[0059] Among them, the scheduler 201 can be used to send memory access instructions and receive response data of memory access instructions; the instruction sequence numbering module 2021 can number the memory access instructions sent by the scheduler according to the execution order between the instructions; the request information cache module 2022 can store the associated information of the memory access instructions, such as register address, instruction data transformation and format processing and other information; the response sequencing module 2023 can sequence the response feedback of the instructions; the storage system 203 can receive memory access instructions, execute memory access requests, and return the response data of the instructions.

[0060] like Figure 2 As shown, the instruction execution method proposed in the present disclosure is that first, the scheduler 201 sends a memory access instruction to the memory access unit 202. After receiving the memory access instruction, the memory access unit 202 numbers the instruction in sequence through the instruction sequence numbering module 2021, and then stores the associated information of the instruction such as the register address, the data conversion and format processing of the instruction through the request information cache module 2022, and then sends the memory access instruction to the storage system 203. After receiving the memory access instruction, the storage system 203 executes the memory access request, and returns the response data of the memory access instruction to the memory access unit 202 after completion. After receiving the response data of the memory access instruction, the memory access unit 202 obtains the associated information of the memory access instruction from the request cache information module, and feeds back the response of the memory access instruction to the scheduler 201 in sequence, thereby realizing instruction sequence response feedback in the scenario of out-of-order execution, which is not limited by the present disclosure.

[0061] It should be noted that when the storage system 203 executes a memory access request, instructions may be executed out of order, and the response order may be different from the request order, which is not limited in the present disclosure.

[0062] Figure 3 A flowchart of an instruction execution method provided by another embodiment of the present disclosure.

[0063] like Figure 3 As shown, the instruction execution method may include the following steps:

[0064] Step 301, when response data corresponding to N instructions are received, first serial numbers corresponding to the N instructions are determined, where N is a positive integer.

[0065] Step 302: Match the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be responded to.

[0066] The specific implementation form of step 302 can refer to the detailed description of other embodiments of the present disclosure, and will not be repeated here.

[0067] Step 303, when any first number matches the target number, take the first state bit corresponding to the target number as the starting point, traverse the values ​​of the second state bits in the register, and determine the number of consecutive state bits whose values ​​in the register are the first value, wherein the second number corresponding to the second state bit is greater than the target number.

[0068] The second status bit is a status bit corresponding to other numbers in the register except the target number, that is, a status bit corresponding to the second number.

[0069] In the present disclosure, after the processor matches N first numbers with the current target number respectively, when any first number matches the target number, it can be determined that any first number is the number corresponding to the first instruction to be returned in response. At this time, the processor can use the first state bit corresponding to the target number as the starting point, traverse the values ​​of each second state bit in the register, and determine the number of consecutive state bits whose values ​​in the register are the first value, that is, determine the number of instructions with the state bit corresponding to the target number in the register as the starting point, the processor has received response data, and the corresponding numbers are continuous, thereby providing conditions for realizing sequential response feedback when instructions are executed out of order.

[0070] In the present disclosure, when the processor takes the first state bit corresponding to the target number as the starting point, traverses the values ​​of each second state bit in the register, and determines the number of consecutive state bits whose values ​​contained in the register are the first value, the processor can read the value of each second state bit in sequence. When the value of the first state bit read is not the first value, the processor stops reading and takes the target number as the starting point, determines the number of state bits that have been read as the number of consecutive state bits whose values ​​contained in the register are the first value. The present disclosure does not limit this.

[0071] Optionally, when the processor takes the first state bit corresponding to the target number as the starting point, traverses the values ​​of the second state bits in the register, and determines the number of consecutive state bits whose values ​​are the first value contained in the register, it can also use the counting function Count Leading One to determine the number of consecutive state bits whose values ​​are the first value contained in the register with the first state bit corresponding to the target number as the starting point. The present disclosure does not limit this.

[0072] Step 304: determine a plurality of serial numbers corresponding to the consecutive status bits.

[0073] In the present disclosure, after determining the number of consecutive state bits whose values ​​of the state bits in the register are the first value and taking the first state bit corresponding to the target number as the starting point, the processor can determine multiple numbers corresponding to these consecutive state bits respectively, thereby providing conditions for instruction sequence response feedback.

[0074] Step 305, based on the order of numbers from small to large, return the response data of the instructions corresponding to the multiple numbers respectively.

[0075] In the present disclosure, after determining the multiple numbers corresponding to the consecutive status bits, the processor can return the response data of the instructions corresponding to the multiple numbers in sequence based on the order of the numbers from small to large, thereby realizing sequential response feedback to the instructions and improving the reliability of the instruction execution method.

[0076] It should be noted that since the scheduler can count after sending each instruction, after receiving the response data of the instructions corresponding to these multiple numbers, the scheduler can subtract the number of received response data from the count value to obtain a new count value. If the new count value is greater than the specified value of the barrier instruction (waitcnt), the scheduler will continue to wait for a response. Otherwise, the scheduler can continue to send subsequent instructions, wherein the specified value of the barrier instruction (waitcnt) can be set as needed, and the present disclosure does not limit this.

[0077] Step 306: Update the values ​​of the status bits corresponding to the multiple numbers in the register to the second value.

[0078] The second value may be used to indicate that the corresponding numbered instruction has responded to feedback, or that the processor has not received response data for the corresponding numbered instruction, and may be in any pre-set form. For example, the second value may be the number "0", which is not limited in the present disclosure.

[0079] In the present disclosure, after the processor returns the response data of the instructions corresponding to multiple numbers in sequence based on the order from small to large, taking the first value as 1 and the second value as 0 as an example, a mask mask with a low bit of 1 and a high bit of 0 can be constructed, wherein the low bits correspond to the status bits of the multiple numbers, and the high bits correspond to the status bits of other numbers in the register, and then the mask is inverted and then ANDed with the value of the corresponding status bit in the register, and the values ​​of the status bits corresponding to the multiple numbers in the register are updated to 0. That is to say, based on the number of the multiple numbers, a right shift trigger signal is first sent, the values ​​of the status bits of the multiple numbers are read out, inverted, and then ANDed with the value of the corresponding status bit in the register, and the values ​​of the status bits corresponding to the multiple numbers in the register are updated to the second value, and then the status bits in the register are sorted in order of number according to the left shift trigger signal, and the present disclosure does not limit this.

[0080] Combine the following Figure 4 , the process of updating the value of the status bit in the register in the instruction execution method provided by the present disclosure is illustrated by way of example, Figure 4 A schematic diagram of a process for updating the value of a status bit in a register in an instruction execution method provided in an embodiment of the present disclosure.

[0081] Figure 4 In the example, a register contains status bits corresponding to N numbers, and the first value of the status bit is 1, the second value is 0, and the number pointed to by the pointer is the target number, which can be used to record the target number. Among them, LSB is the abbreviation of Least Significant Bit (LSB), and Count Leading One is a counting function, which can be used to determine the number of consecutive status bits whose value of the status bit is 1.

[0082] like Figure 4 As shown, the current target number in the register is 3. When the processor receives response data of multiple instructions, if the multiple response data include the response data of the instruction corresponding to number 3, the value of the status bit corresponding to number 3 can be updated to 1, and each number and the corresponding status bit in the register are cyclically shifted right by 3 bits until the status bit corresponding to number 3 is located at the lowest bit in the register, that is, the first position. Then, through the counting function Count LeadingOne, starting from the least significant bit in the status bit in the register, that is, the status bit corresponding to number 3, the number of consecutive status bits with a value of 1 is determined, as shown in FIG. Figure 4 The values ​​of the status bits corresponding to numbers 3 and 4 in the register are 1, and the number of continuous status bits is determined to be 2. At this time, the response data of the instructions corresponding to numbers 3 and 4 can be fed back in order of numbers from small to large. Then, based on the number of continuous status bits and the number of status bits contained in the register, a binary mask 0b00000011 is constructed, starting from the least significant bit, with the 2 low-order values ​​of the continuous status bits being 1 and the remaining N-2 bits being 0. The mask is inverted and ANDed with the values ​​of the corresponding status bits in the register. The values ​​of the status bits corresponding to the numbers for which instruction response feedback has been performed are set to 0, that is, the values ​​of the status bits corresponding to numbers 3 and 4 are set to 0. Finally, each number and the corresponding status bit in the register are cyclically shifted left by 3 bits to return to their original position, and based on the number of continuous status bits 2, the pointer is shifted right by two bits to point to number 5. At this time, the target number in the register is updated from number 3 to number 5.

[0083] Step 307: Update the target number based on the number of the multiple numbers and determine the updated target number.

[0084] In the present disclosure, after the processor updates the values ​​of the status bits corresponding to the multiple numbers in the register to the second value, it can update the target number based on the number of the multiple numbers and determine the updated target number, thereby improving the accuracy of instruction execution.

[0085] Combine the following Figure 5, the process of executing instruction response feedback of the instruction execution method provided by the present disclosure is illustrated by way of example, Figure 5 A schematic diagram of the process of executing instruction response feedback in the instruction execution method provided in an embodiment of the present disclosure.

[0086] Figure 5 In the example, a register contains status bits corresponding to N numbers, the first value of the status bit is number 1, and the second value is number 0. The number pointed to by the pointer is the target number, which can be used to record the target number.

[0087] like Figure 5 As shown in the figure, from the value of the status bit in the register, it can be seen that the processor has currently received the response data corresponding to the instructions numbered 6, 4, 2, and 1, respectively. Since the target number pointed to by the pointer is 0, it is necessary to continue waiting to accumulate the response data of the instructions. Then, after receiving the response data corresponding to the instruction numbered 0, since number 0 is the current target number, the instruction response feedback can be executed at this time. When the processor performs instruction response feedback, it first takes number 0 as the starting point and determines the number of continuous status bits with the corresponding value of 1, which is calculated by Figure 5 The values ​​of the status bits of number 0, number 1, and number 2 in are all 1 and continuous. It can be determined that the response data of the instructions of number 0, number 1, and number 2 have been received. It can be determined that the number of continuous status bits is 3. The processor can feedback the response data corresponding to the instructions of number 0, number 1, and number 2 in the order from small to large, and then update the values ​​of the status bits corresponding to number 0, number 1, and number 2 to 0, and move the pointer by the number of continuous status bits, that is, Figure 5 The pointer is moved by 3 numbers to point to number 3. At this time, the target number can be updated from number 0 to number 3, thereby realizing sequential response feedback when instructions are executed out of order, and improving the reliability of the instruction execution method.

[0088] In the embodiment of the present disclosure, when response data corresponding to N instructions are received, the processor first determines the first numbers corresponding to the N instructions, and then matches the N first numbers with the current target number respectively. When any first number matches the target number, the processor takes the first state bit corresponding to the target number as the starting point, traverses the values ​​of the second state bits in the register, determines the number of consecutive state bits whose values ​​in the register are the first value, then determines multiple numbers corresponding to the consecutive state bits, and returns the response data of the instructions corresponding to the multiple numbers in order from small to large, and finally updates the values ​​of the state bits corresponding to the multiple numbers in the register to the second value, and updates the target number based on the number of multiple numbers to determine the updated target number. Therefore, when receiving response data corresponding to multiple instructions respectively, the processor matches the numbers corresponding to these multiple instructions respectively with the number of the first instruction to be returned in response. When the numbers corresponding to these instructions include the number of the first instruction to be returned in response, taking the status bit of the number as the starting point, the number of consecutive status bits in the register whose corresponding value is the first value and the corresponding numbers are determined, and the response data of the corresponding instructions are returned in sequence according to the order of the numbers. Thereafter, the value of the corresponding status in the register is updated to the second value, and based on the number of returned instructions, the number of the next instruction to be returned in response is determined, thereby realizing sequential response feedback of instructions and improving the accuracy of instruction execution.

[0089] Figure 6 A flowchart of an instruction execution method provided by another embodiment of the present disclosure.

[0090] like Figure 6 As shown, the instruction execution method may include the following steps:

[0091] Step 601, when response data corresponding to N instructions are received, first serial numbers corresponding to the N instructions are determined, where N is a positive integer.

[0092] Step 602: Match the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be responded to.

[0093] Step 603, when any first number matches the target number, take the first state bit corresponding to the target number as the starting point, traverse the values ​​of the second state bits in the register, and determine the number of consecutive state bits whose values ​​in the register are the first value, wherein the second number corresponding to the second state bit is greater than the target number.

[0094] Step 604: determine a plurality of serial numbers corresponding to the consecutive status bits.

[0095] Step 505, based on the order of numbers from small to large, the response data of the instructions corresponding to the multiple numbers are returned in sequence.

[0096] Step 606: Update the values ​​of the status bits corresponding to the multiple numbers in the register to the second value.

[0097] The specific implementation forms of steps 601 to 606 may refer to the detailed description of other embodiments of the present disclosure and will not be repeated here.

[0098] Step 607, determining the sum of the number of multiple numbers and the target number.

[0099] In the present disclosure, after the processor updates the values ​​of the status bits corresponding to the multiple numbers in the register to the second value, when updating the target number, the processor may first determine the sum of the number of the multiple numbers and the target number.

[0100] Step 608: If the sum is less than or equal to the total number of status bits contained in the register, determine the sum as the updated target number.

[0101] In the present disclosure, after the processor determines the sum of the number of multiple numbers and the target number, if the sum is less than or equal to the total number of status bits contained in the register, it can be determined that the sum of the number of multiple numbers and the target number is legal, and the register contains the same number as the sum. At this time, the sum can be determined as the updated target number.

[0102] Optionally, when the sum is greater than the total number of status bits contained in the register, the processor can determine that the sum of the number of these multiple numbers and the target number is illegal, the sum has exceeded the number in the register, and there is no number identical to the sum in the register. At this time, the difference between the sum and the total number of status bits can be determined as the updated target number.

[0103] In the embodiment of the present disclosure, when response data corresponding to N instructions are received, the processor first determines the first numbers corresponding to the N instructions, and matches the N first numbers with the current target number respectively. When any first number matches the target number, the processor takes the first state bit corresponding to the target number as the starting point, traverses the values ​​of the second state bits in the register, determines the number of consecutive state bits whose values ​​are the first value contained in the register, and then determines multiple numbers corresponding to the consecutive state bits, and returns the response data of the instructions corresponding to the multiple numbers in order from small to large. Thereafter, the values ​​of the state bits corresponding to the multiple numbers in the register are updated to the second value, and the sum of the number of the multiple numbers and the target number is determined. Finally, when the sum is less than or equal to the total number of state bits contained in the register, the sum is determined as the updated target number. Therefore, when the processor receives response data corresponding to multiple instructions, and when the numbers corresponding to these multiple instructions include the target number of the instruction to be returned in response, it determines the number and number of continuous status bits whose corresponding values ​​are the first value, starting from the status bit corresponding to the number, and returns the response data of the instructions corresponding to the multiple numbers in sequence based on the numbering sequence, then updates the value of the corresponding status bit to the second value, and when the sum of the number of these multiple numbers and the target number is less than or equal to the total number of status bits contained in the register, determines the sum as the updated target number, thereby improving the reliability of instruction execution.

[0104] Figure 7 A flowchart of an instruction execution method provided by another embodiment of the present disclosure.

[0105] like Figure 7 As shown, the instruction execution method may include the following steps:

[0106] Step 701, in response to receiving an instruction to be executed, determining a maximum identifier in a preset lookup table and a third number associated with the maximum identifier, wherein the lookup table is used to store associated information of unexecuted instructions.

[0107] The instruction to be executed may be an instruction to be accessed, which is not limited in the present disclosure.

[0108] The identifier in the lookup table can be used to represent the unexecuted instruction, and it can be any pre-set form. For example, the identifier in the lookup table can be an OST ID, which is not limited in the present disclosure.

[0109] Among them, OST is the abbreviation of outstanding; ID is the abbreviation of identity.

[0110] The unexecuted instructions stored in the lookup table may be instructions for which the processor has not received response data.

[0111] The third number may be the sequential number of the instruction corresponding to the maximum identifier in the lookup table.

[0112] The associated information of the instruction may include information such as register address, data conversion and format processing of the instruction, etc., which is not limited in the present disclosure.

[0113] In the present disclosure, in response to receiving an instruction to be executed, the processor may first determine the maximum identifier in a preset lookup table and the third number associated with the maximum identifier in order to match the request and response of the instruction.

[0114] Step 702, determining the target identifier and the fourth number of the instruction to be executed according to the maximum identifier and the third number respectively.

[0115] In the present disclosure, after determining the maximum identifier in a preset lookup table and the third number associated with the maximum identifier, the processor can determine the target identifier and the fourth number of the instruction to be executed based on the maximum identifier and the third number, respectively. For example, the maximum identifier plus 1 can be determined as the target identifier, and the third number plus 1 can be determined as the fourth number. When the third number has reached the maximum OST number of instructions that the scheduler can support, the numbering can be re-circulated to determine the fourth number. The present disclosure does not limit this.

[0116] Step 703: associate the instruction to be executed with the target identifier and the fourth serial number and store them in a lookup table.

[0117] In the present disclosure, after determining the target identifier and the fourth number of the instruction to be executed, the processor can associate the instruction to be executed with the target identifier and the fourth number and store them in a lookup table, so that the request and response of the instruction to be executed can be matched, thereby improving the accuracy of instruction execution.

[0118] Optionally, after the processor returns the response data of the instructions corresponding to the multiple numbers in sequence, it can determine that the instructions corresponding to the multiple numbers have been executed. At this time, the instructions and identifiers corresponding to the multiple numbers in the lookup table can be cleared.

[0119] In the disclosed embodiment, first, in response to receiving the instruction to be executed, the maximum identifier in the preset lookup table and the third number associated with the maximum identifier are determined, and then the target identifier and the fourth number of the instruction to be executed are determined according to the maximum identifier and the third number, respectively, and finally the instruction to be executed, the target identifier and the fourth number are associated and stored in the lookup table. Thus, by determining the target identifier and the corresponding number of the instruction to be executed according to the maximum identifier and the number corresponding to the maximum identifier in the lookup table, and storing the instruction to be executed, the target identifier and the corresponding number in the lookup table in association, the execution request and the response of the instruction are matched, and the accuracy of the instruction execution is improved.

[0120] Figure 8 A flowchart of an instruction execution method provided by another embodiment of the present disclosure.

[0121] like Figure 8 As shown, the instruction execution method may include the following steps:

[0122] Step 801, when the register includes status bit sequences corresponding to multiple threads respectively, in response to receiving an instruction to be executed, based on the thread identifier associated with the instruction to be executed, determine the maximum identifier associated in the lookup table and the third number associated with the maximum identifier.

[0123] The thread identifier can be used to characterize the thread, and can be a pre-set identifier in any form. For example, the thread identifier can be the name of the thread, etc., which is not limited in the present disclosure.

[0124] It should be noted that, when the register includes status bit sequences corresponding to multiple threads, the status bit sequence corresponding to each thread can correspond to a lookup table, or a lookup table can include status bit sequences corresponding to multiple threads, and the present disclosure does not limit this.

[0125] In the present disclosure, when a register includes status bit sequences corresponding to multiple threads respectively, the processor, in response to receiving an instruction to be executed, can determine the maximum identifier associated in the lookup table corresponding to the thread identifier and the third number associated with the maximum identifier based on the thread identifier associated with the instruction to be executed.

[0126] Step 802, determining the target identifier and the fourth number of the instruction to be executed according to the maximum identifier and the third number respectively.

[0127] Step 803: associate the instruction to be executed with the target identifier and the fourth serial number and store them in a lookup table.

[0128] The specific implementation forms of step 802 to step 803 may refer to the detailed description of other embodiments of the present disclosure and will not be repeated here.

[0129] In the embodiment of the present disclosure, in the case where the register includes status bit sequences corresponding to multiple threads respectively, first, in response to receiving the instruction to be executed, based on the thread identifier associated with the instruction to be executed, the maximum identifier associated in the lookup table and the third number associated with the maximum identifier are determined, and then the target identifier and the fourth number of the instruction to be executed are determined according to the maximum identifier and the third number respectively, and finally the instruction to be executed, the target identifier and the fourth number are stored in the lookup table in association. Thus, in the case where the register includes status bit sequences corresponding to multiple threads respectively, the processor determines the maximum identifier associated in the lookup table and the number associated therewith based on the thread identifier associated with the instruction to be executed, and determines the target identifier and the number of the instruction to be executed based on the maximum identifier and the number associated therewith, and stores the instruction to be executed, the target identifier and the number in association therewith in the lookup table, thereby providing conditions for implementing the execution method under multi-threading and improving the adaptability of instruction execution.

[0130] Fig. 9 A flowchart of an instruction execution method provided by another embodiment of the present disclosure.

[0131] like Fig. 9 As shown, the instruction execution method may include the following steps:

[0132] Step 901, when response data corresponding to N instructions are received, first serial numbers corresponding to the N instructions are determined, where N is a positive integer.

[0133] The specific implementation form of step 901 can refer to the detailed description of other embodiments of the present disclosure and will not be repeated here.

[0134] Step 902: When the register includes status bit sequences corresponding to multiple threads, target threads associated with N instructions and target numbers corresponding to each target thread are determined respectively.

[0135] In the present disclosure, after determining the first numbers corresponding to N instructions respectively, the processor can respectively determine the target threads associated with the N instructions and the target numbers corresponding to each target thread when the register includes status bit sequences corresponding to multiple threads respectively, thereby providing a data basis for determining whether to execute instruction response feedback.

[0136] Step 903: Match each first number with the target number corresponding to the target thread associated with it.

[0137] In the present disclosure, after the processor determines the target threads associated with N instructions respectively and the target number corresponding to each target thread, it can match each first number with the target number corresponding to the target thread associated with it, thereby improving the reliability and accuracy of executing instructions in a multi-threaded environment.

[0138] Step 904, based on the matching results of the N first numbers and the target number, execute at least one of the following: update the value in the preset register, provide instruction response feedback, and update the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0139] In the present disclosure, after matching each first number with the target number corresponding to the target thread associated with it, the processor can execute at least one of the following according to the matching result of each first number with the target number corresponding to the target thread associated with it: updating the value in a preset register, providing instruction response feedback, and updating the target number, thereby realizing a multi-threaded concurrent instruction execution method, which is not limited in the present disclosure.

[0140] The specific implementation form of step 904 can refer to the detailed description of other embodiments of the present disclosure and will not be repeated here.

[0141] Combine the following Fig.10 , an example is given to illustrate the implementation process of the instruction execution method provided by the present disclosure in a multi-threaded scenario, Fig.10 A schematic diagram of an implementation of an instruction execution method in a multi-threaded scenario provided in an embodiment of the present disclosure.

[0142] Fig.10 In the embodiment, the status bit sequences and corresponding pointers corresponding to four threads are respectively included in the register, namely, the status bit sequences and pointers corresponding to thread 0, thread 1, thread 2 and thread 3 respectively are taken as an example for explanation, wherein the pointer is used to record the target number of the status bit sequence of the corresponding thread.

[0143] like Fig.10 As shown, in a multi-threaded scenario, the register in the instruction execution method provided by the present invention may include status bit sequences and pointers corresponding to multiple threads respectively. When the response data of the instruction is received, the value of the status bit and the pointer in the corresponding status bit sequence can be read first according to the thread identifier associated with the instruction. When the number corresponding to the received instruction is the target number recorded by the pointer, the instruction response feedback is executed, and the status bit and the pointer corresponding to the instruction for which the instruction response feedback has been performed are updated, and then the updated status and pointer are written back to the register, thereby realizing the concurrent execution of the sequential response feedback of instructions under multi-threading.

[0144] In the embodiment of the present disclosure, when receiving response data corresponding to N instructions respectively, the processor first determines the first numbers corresponding to the N instructions respectively, and when the register includes status bit sequences corresponding to multiple threads respectively, determines the target threads associated with the N instructions respectively, and the target numbers corresponding to each target thread respectively, and then matches each first number with the target number corresponding to the target thread associated with it, and finally, according to the matching results of the N first numbers with the target numbers, performs at least one of the following: updates the preset register value, performs instruction response feedback, and updates the target number. Thus, when the processor receives response data corresponding to multiple instructions respectively, in the case of multi-threading, it determines the threads and corresponding target numbers associated with these multiple instructions respectively, matches the numbers corresponding to these multiple instructions respectively with the target numbers of the associated threads, and performs corresponding operations based on the matching results, thereby realizing instruction sequence response feedback under multi-threading and improving the accuracy of instruction execution.

[0145] In order to implement the above embodiments, the present disclosure also proposes an instruction execution device.

[0146] Fig.11 A schematic diagram of the structure of an instruction execution device provided in another embodiment of the present disclosure.

[0147] like Fig.11 As shown, the instruction execution device 1100 may include: a first determination module 1101 , a matching module 1102 , and an execution module 1103 .

[0148] The first determining module 1101 is used to determine the first serial numbers corresponding to the N instructions respectively when receiving the response data corresponding to the N instructions respectively, where N is a positive integer;

[0149] A matching module 1102 is used to match the N first numbers with the current target number respectively, wherein the target number is the number corresponding to the first instruction to be responded to;

[0150] The execution module 1103 is used to execute at least one of the following according to the matching results between the N first numbers and the target number: updating the value in the preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0151] Optionally, the execution module 1103 is specifically used to:

[0152] When none of the N first numbers matches the target number, the values ​​of the first state bits in the register corresponding to the N first numbers are updated to the first value.

[0153] Optionally, the execution module 1103 is specifically used to:

[0154] In the case where any first number matches the target number, taking the first state bit corresponding to the target number as the starting point, traversing the values ​​of the second state bits in the register, and determining the number of consecutive state bits whose values ​​in the register are the first value, wherein the second number corresponding to the second state bit is greater than the target number;

[0155] Determine a plurality of numbers corresponding to consecutive status bits respectively;

[0156] Based on the order of numbers from small to large, the response data of the commands corresponding to multiple numbers are returned in sequence.

[0157] Optionally, the execution module 1103 is further used to:

[0158] Update the values ​​of the status bits corresponding to the plurality of numbers in the register to the second value;

[0159] The target number is updated based on the number of the plurality of numbers, and the updated target number is determined.

[0160] Optionally, the execution module 1103 is further used to:

[0161] Determine the sum of the number of multiple numbers and the target number;

[0162] In the case where the sum is less than or equal to the total number of status bits contained in the register, the sum is determined as the updated target number.

[0163] Optionally, the execution module 1103 is further used to:

[0164] In the case where the sum is greater than the total number of status bits contained in the register, the difference between the sum and the total number of status bits is determined as the updated target number.

[0165] Optionally, it also includes:

[0166] A second determination module (not shown in the figure) is used to determine the maximum identifier in a preset lookup table and a third number associated with the maximum identifier in response to receiving the instruction to be executed, wherein the lookup table is used to store the associated information of the unexecuted instructions;

[0167] A third determination module (not shown in the figure), used to determine the target identifier and the fourth number of the instruction to be executed according to the maximum identifier and the third number respectively;

[0168] The storage module (not shown in the figure) is used to associate the instruction to be executed with the target identifier and the fourth number and store them in the lookup table.

[0169] Optionally, the execution module 1103 is further used to:

[0170] Clear the instructions and identifiers corresponding to multiple numbers in the lookup table.

[0171] Optionally, the register includes status bit sequences corresponding to a plurality of threads respectively, and the second determination module (not shown in the figure) is specifically used for:

[0172] Based on the thread identifier associated with the instruction to be executed, the maximum identifier associated in the lookup table and the third number associated with the maximum identifier are determined.

[0173] Optionally, the matching module 1102 is specifically configured to:

[0174] Determine the target threads associated with the N instructions respectively, and the target number corresponding to each target thread;

[0175] Each first number is matched with a target number corresponding to a target thread associated with the first number.

[0176] The functions and specific implementation principles of the above modules in the embodiments of the present disclosure can be referred to the above method embodiments, and will not be repeated here.

[0177] The instruction execution device of the disclosed embodiment, when receiving response data corresponding to N instructions respectively, first determines the first numbers corresponding to the N instructions respectively, then matches the N first numbers with the current target numbers respectively, and finally performs at least one of the following according to the matching results of the N first numbers with the target numbers: updates the value in the preset register, performs instruction response feedback, and updates the target number. Thus, when the processor receives response data corresponding to N instructions respectively, it matches the numbers corresponding to the N instructions respectively with the target number of the current response to be returned, and performs the corresponding operation according to the matching results, thereby realizing sequential response feedback in the scenario of out-of-order execution of instructions, and improving the accuracy and reliability of the instruction execution method.

[0178] Fig.12 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Fig.12 The electronic device 1200 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0179] like Fig.12 As shown, the electronic device 1200 is in the form of a general purpose computing device. The components of the electronic device 1200 may include, but are not limited to: one or more processors or processing units 1216, a system memory 1228, and a bus 1218 connecting different system components (including the system memory 1228 and the processing unit 1216).

[0180] Bus 1218 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

[0181] The electronic device 1200 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 1200, including volatile and non-volatile media, removable and non-removable media.

[0182] The memory 1228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1230 and / or cache 1232. The electronic device 1200 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 1234 may be used to read and write non-removable, non-volatile magnetic media ( Fig.12 not shown, usually called a "hard drive"). Although Fig.12 Not shown, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to the bus 1218 via one or more data medium interfaces. The memory 1228 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0183] A program / utility 1240 having a set (at least one) of program modules 1242 may be stored, for example, in the memory 1228, such program modules 1242 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 1242 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0184] The electronic device 1200 may also communicate with one or more external devices 1214 (e.g., keyboard, pointing device, display 1224, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 1200, and / or communicate with any device that enables the electronic device 1200 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed via an input / output (I / O) interface 1222. In addition, the electronic device 1200 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 1220. As shown, the network adapter 1220 communicates with other modules of the electronic device 1200 via a bus 1218. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 1200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0185] The processing unit 1216 executes various functional applications and data processing by running programs stored in the system memory 1228, such as implementing the methods mentioned in the above embodiments.

[0186] In order to implement the above embodiments, the present disclosure further proposes a computer-readable storage medium storing computer execution instructions. When the computer execution instructions are executed by a processor, the instruction execution method proposed in the above embodiments of the present disclosure is implemented.

[0187] In order to implement the above embodiments, the present disclosure further proposes a computer program product, including a computer program. When the computer program is executed by a processor, it implements the instruction execution method proposed in the above embodiments of the present disclosure.

[0188] Fig.13 is a schematic diagram of the structure of the chip proposed in the embodiment of the present disclosure. Fig.13 The structure of the chip 1300 is shown, but is not limited to this.

[0189] The chip 1300 includes a processing circuit 1301 , and the processing circuit 1301 is configured to execute any of the above methods.

[0190] In some embodiments, the chip 1300 further includes one or more interface circuits 1302. Optionally, the interface circuit 1302 is connected to the memory 1303. The interface circuit 1302 can be used to receive signals from the memory 1303 or other devices, and the interface circuit 1302 can be used to send signals to the memory 1303 or other devices. For example, the interface circuit 1302 can read instructions stored in the memory 1303 and send the instructions to the processing circuit 1301.

[0191] In some embodiments, the interface circuit 1302 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1301 performs other steps.

[0192] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0193] In some embodiments, the chip 1300 further includes one or more memories 1303 for storing instructions. Alternatively, all or part of the memory 1303 may be outside the chip 1300.

[0194] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0195] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0196] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0197] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0198] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0199] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0200] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0201] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A method for executing an instruction, characterized in that: include: In the case of receiving response data corresponding to N instructions respectively, determining first numbers corresponding to the N instructions respectively, where N is a positive integer; Match the N first numbers with the target number respectively, wherein the target number is the number corresponding to the first instruction to be returned as a response; According to the matching results of the N first numbers and the target numbers, at least one of the following is performed: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

2. The method according to claim 1, characterized in that The performing at least one of the following according to the matching results of the N first numbers and the target number includes: In a case where none of the N first numbers matches the target number, the values ​​of the first status bits in the register respectively corresponding to the N first numbers are updated to the first value.

3. The method according to claim 1, characterized in that The performing at least one of the following according to the matching results of the N first numbers and the target number includes: In the case where any first number matches the target number, taking the first state bit corresponding to the target number as the starting point, traversing the values ​​of the second state bits in the register, and determining the number of consecutive state bits whose values ​​are the first value contained in the register, wherein the second number corresponding to the second state bit is greater than the target number; Determine a plurality of serial numbers corresponding to the consecutive status bits respectively; Based on the order of numbers from small to large, response data of the instructions corresponding to the multiple numbers are returned in sequence.

4. The method according to claim 3, characterized in that After returning the response data of the instructions corresponding to the multiple numbers respectively in sequence, the method further includes: updating the values ​​of the status bits respectively corresponding to the plurality of numbers in the register to second values; The target number is updated based on the number of the plurality of numbers, and an updated target number is determined.

5. The method according to claim 4, characterized in that The updating of the target number based on the number of the multiple numbers to determine the updated target number includes: Determine the sum of the number of the plurality of numbers and the target number; In the case that the sum is less than or equal to the total number of status bits contained in the register, the sum is determined as the updated target number.

6. The method according to claim 5, characterized in that After determining the sum of the number of the plurality of numbers and the target number, the method further includes: In the case where the sum is greater than the total number of status bits contained in the register, the difference between the sum and the total number of status bits is determined as the updated target number.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: In response to receiving an instruction to be executed, determining a maximum identifier in a preset lookup table and a third number associated with the maximum identifier, wherein the lookup table is used to store associated information of unexecuted instructions; Determining a target identifier and a fourth number of the instruction to be executed according to the maximum identifier and the third number respectively; The instruction to be executed is associated with the target identifier and the fourth serial number and stored in the lookup table.

8. The method according to claim 7, characterized in that After returning the response data of the instructions corresponding to the multiple numbers respectively in sequence, the method further includes: The instructions and identifiers respectively corresponding to the plurality of numbers in the lookup table are cleared.

9. The method according to claim 7, characterized in that The register includes status bit sequences corresponding to the plurality of threads respectively, and the determining of the maximum identifier in the preset lookup table and the third number associated with the maximum identifier includes: Based on the thread identifier associated with the instruction to be executed, the maximum identifier associated in the lookup table and the third number associated with the maximum identifier are determined.

10. The method according to claim 9, characterized in that The matching of the N first numbers with the target numbers respectively includes: Determine the target threads associated with the N instructions respectively, and the target number corresponding to each of the target threads; Each of the first numbers is matched with a target number corresponding to the target thread associated with it.

11. An instruction execution device, characterized in that: The device comprises: A first determining module, configured to determine first numbers corresponding to N instructions respectively when receiving response data corresponding to the N instructions respectively, wherein N is a positive integer; A matching module, used for matching the N first numbers with a target number respectively, wherein the target number is a number corresponding to the first instruction to be returned as a response; An execution module is used to execute at least one of the following according to the matching results of the N first numbers and the target number: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

12. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the program, the instruction execution method described in any one of claims 1 to 10 is implemented.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction execution method according to any one of claims 1 to 10 is implemented.

14. A chip, characterized in that: The chip includes a processing circuit and an interface circuit; wherein the interface circuit is used to obtain instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the instruction execution method as described in any one of claims 1-10.

15. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the instruction execution method according to any one of claims 1 to 10.

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